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22720 commits

Author SHA1 Message Date
andi6
19e34b7f6e x64: modify addr limit to support 64 bits addr backtrace 
Signed-off-by: andi6 <andi6@xiaomi.com>
 2024-10-11 15:32:28 +08:00
cuiziwei
5e96e72cb6 X86_64: Add libcxx availability macros. 
Signed-off-by: cuiziwei <cuiziwei@xiaomi.com>
 2024-10-11 13:53:10 +08:00
cuiziwei
1816d752af arch/x86_64:Fix build cxx warning. 
Signed-off-by: cuiziwei <cuiziwei@xiaomi.com>
 2024-10-11 13:46:27 +08:00
lipengfei28
274ca2ea65 arch: arm64: Fix ARM64_CONTEXT_REGS number 
This commit fixes the regression in https://github.com/apache/nuttx/pull/14063

Signed-off-by: lipengfei28 <lipengfei28@xiaomi.com>
 2024-10-11 13:26:54 +08:00
anjiahao
5076b0c74c risc-v:Unify module compilation options 
Signed-off-by: anjiahao <anjiahao@xiaomi.com>
 2024-10-11 11:20:45 +08:00
yinshengkai
211a56910a syslog: support syslog redirection to sched_note 
Signed-off-by: yinshengkai <yinshengkai@xiaomi.com>
 2024-10-11 01:30:11 +08:00
Xu Xingliang
f68d594420 arch/arm64: rename register names to align with arm32 
Signed-off-by: Xu Xingliang <xuxingliang@xiaomi.com>
Signed-off-by: lipengfei28 <lipengfei28@xiaomi.com>
 2024-10-11 01:17:24 +08:00
wangmingrong1
ec3c27df0d makefile/clang: Compare versions for upward compatibility 
Signed-off-by: wangmingrong1 <wangmingrong1@xiaomi.com>
 2024-10-11 00:45:39 +08:00
yinshengkai
02eb280302 arch/perf: modify the return value of up_perf_gettime to clock_t 
When using alarm_arch implementation, 64-bit time can be returned. Using unsign long will cause precision loss.

Signed-off-by: yinshengkai <yinshengkai@xiaomi.com>
 2024-10-10 23:17:14 +08:00
p-szafonimateusz
ed71aa810e arch/x86_64/intel64/intel64_irq.c: fix busy irq logic 
use correct macro for cpu_set_t busy variable and remove obsolote check

also remove not needed #include <sched.h> and "Public data"

Signed-off-by: p-szafonimateusz <p-szafonimateusz@xiaomi.com>
 2024-10-10 22:57:04 +08:00
yinshengkai
8abbd3cde5 nuttx-names.in: add feof 
When running gcov in sim, nuttx feof is called and causes crash

Signed-off-by: yinshengkai <yinshengkai@xiaomi.com>
 2024-10-10 22:55:04 +08:00
liwenxiang1
fee7e0ce81 arch/x86_64:Add macros related to CPUID 
Signed-off-by: liwenxiang1 <liwenxiang1@xiaomi.com>
 2024-10-10 15:07:45 +02:00
ouyangxiangzhen
d0779e0eef arch/x86_64: Fix up_timer compilation error 
This commit fix up_timer compilation error.

Signed-off-by: ouyangxiangzhen <ouyangxiangzhen@xiaomi.com>
 2024-10-10 15:07:22 +02:00
ouyangxiangzhen
e6548ead20 arch/x86_64: Fix up_timer_start 
Fix according to up_alarm_start.

Signed-off-by: ouyangxiangzhen <ouyangxiangzhen@xiaomi.com>
 2024-10-10 15:07:22 +02:00
yinshengkai
d375a09c0a libs: add gprof arm64 support 
Signed-off-by: yinshengkai <yinshengkai@xiaomi.com>
 2024-10-10 18:46:51 +08:00
yinshengkai
eb8449cb0c sched/gprof: add gprof support 
gprof can analyze code hot spots based on scheduled sampling.
After adding the "-pg" parameter when compiling, you can view the code call graph.

Signed-off-by: yinshengkai <yinshengkai@xiaomi.com>
 2024-10-10 18:46:51 +08:00
Eren Terzioglu
f774afb4d9 esp32[s3|s2]: Add temperature sensor thread support 2024-10-10 18:45:01 +08:00
Eren Terzioglu
7556614732 esp32[c3|c6|h2]: Add temperature sensor thread support 2024-10-10 18:45:01 +08:00
Eren Terzioglu
4060f6ba80 esp32[s2|s3]: Add UORB support for internal temperature sensor 2024-10-10 18:45:01 +08:00
Eren Terzioglu
929f9ccfa2 esp32[c3|c6|h2]: Add UORB support for internal temperature sensor 2024-10-10 18:45:01 +08:00
hujun5
7216d566a6 sim: only POSIX implementation (ARCH_HAVE_MULTICPU) is provided 
This commit fixes the regression from https://github.com/apache/nuttx/pull/13886

Signed-off-by: hujun5 <hujun5@xiaomi.com>
 2024-10-10 18:38:25 +08:00
liwenxiang1
24f54ba712 arch/x86_64: cache convert all asm() to __asm__() 
asm() is not supported by -std=c99, __asm__() is more portable

Signed-off-by: liwenxiang1 <liwenxiang1@xiaomi.com>
 2024-10-10 18:36:09 +08:00
andi6
2ed88f8813 x64: add acrn ioapic init support 
if we two step to set interrupt trigger and disable interrupt,
acrn will inject #GP exception

Signed-off-by: andi6 <andi6@xiaomi.com>
 2024-10-10 17:49:40 +08:00
liwenxiang1
8d2fc5c9ee arch/x86_64:Add nanosecond delay interface to TSC 
Signed-off-by: liwenxiang1 <liwenxiang1@xiaomi.com>
 2024-10-10 17:13:01 +08:00
cuiziwei
f86644141b x86_64:Fix ld error. 
LD: nuttx.elf
ld:in function `std::__1::ios_base::imbue(std::__1::locale const&)':
nuttx/libs/libxx/libcxx/src/ios.cpp:129: undefined reference to `_Unwind_Resume'

Signed-off-by: cuiziwei <cuiziwei@xiaomi.com>
 2024-10-10 16:51:38 +08:00
wangming9
1c2856dfcb arch/arm64: Fixed up_getusrsp getting stack Pointers 
Signed-off-by: wangming9 <wangming9@xiaomi.com>
Signed-off-by: lipengfei28 <lipengfei28@xiaomi.com>
 2024-10-10 15:40:03 +08:00
wangming9
b0ea6840e1 arch/arm64: Use serr to print fatal error messages. 
Summary:
sinfo cannot print fatal error messages when CONFIG_DEBUG_SCHED_INFO is turned off.

Signed-off-by: wangming9 <wangming9@xiaomi.com>
 2024-10-10 15:40:03 +08:00
wangming9
27d77b1aca arch/arm64: Fixed GIC3 for goldfish platform 
Signed-off-by: wangming9 <wangming9@xiaomi.com>
 2024-10-10 15:40:03 +08:00
wangming9
b3e640cf3f arch/arm64: GICv2 detection is compatible with different qemu versions 
Summary:
- GICv2 cannot be detected on the golsfish platform
- Golsfish uses version 2.12.0 of qemu with a GICC_IIDR value of 0,
  read ICPIDR2 to determine the GIC version

Signed-off-by: wangming9 <wangming9@xiaomi.com>
 2024-10-10 15:40:03 +08:00
Bowen Wang
a847ee1675 qmeu_boot: add rpmsg syslog init for arm64 qemu chip 
Signed-off-by: Bowen Wang <wangbowen6@xiaomi.com>
 2024-10-10 15:40:03 +08:00
wangming9
e48b81ebe9 arch/arm64: Supports cluster PMU 
Summary:
Some processors implement cluster PMUs, such as Cortex-R82.

Signed-off-by: wangming9 <wangming9@xiaomi.com>
 2024-10-10 15:40:03 +08:00
wangming9
fa96350574 arch/arm64: Modify the method for obtaining the CPU frequency 
Summary:
1、cntfrq_el0 is used to store the timer frequency, which may
   be different from the CPU frequency.
2、Do not use up_perf interface for SMP.

Signed-off-by: wangming9 <wangming9@xiaomi.com>
 2024-10-10 15:40:03 +08:00
yangguangcai
e9b77833e3 goldfish:config pl031. 
Signed-off-by: yangguangcai <yangguangcai@xiaomi.com>
 2024-10-10 15:40:03 +08:00
liwenxiang1
f858026819 arch/x86_64:Add allsymbol functionality 
Signed-off-by: liwenxiang1 <liwenxiang1@xiaomi.com>
 2024-10-10 14:56:08 +08:00
Huang Qi
20cba94a86 risc-v/espressif: Fix alert message in esp_setup_irq() 
Correct the alert message in `esp_setup_irq()` if
irq number allocation fails, the parameter number is not
matched with format specifier.

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2024-10-10 13:41:34 +08:00
liwenxiang1
e3b3a6145a arch/x86_64: idle convert all asm() to __asm__() 
Signed-off-by: liwenxiang1 <liwenxiang1@xiaomi.com>
 2024-10-10 13:40:39 +08:00
liwenxiang1
1af831e139 arch/x86_64: cpuid expect 32 bit variables 
Signed-off-by: liwenxiang1 <liwenxiang1@xiaomi.com>
 2024-10-10 12:03:27 +08:00
liwenxiang1
2448e8a59e arch/x86_64:Add perf tool 
Signed-off-by: liwenxiang1 <liwenxiang1@xiaomi.com>
 2024-10-10 12:01:16 +08:00
liwenxiang1
f81c7dbc93 arch/x86_64:Use the checkstack function 
Signed-off-by: liwenxiang1 <liwenxiang1@xiaomi.com>
 2024-10-10 11:40:15 +08:00
hujun5
e249dd2672 arch: support customized up_cpu_index() in AMP mode 
Some app with same code runs on different cores in AMP mode,
need the physical core on which the function is called.

Signed-off-by: hujun5 <hujun5@xiaomi.com>
Signed-off-by: fangxinyong <fangxinyong@xiaomi.com>
 2024-10-10 02:38:40 +08:00
ligd
ff99745b22 arm-m: support zero interrupt back to game 
Signed-off-by: ligd <liguiding1@xiaomi.com>
 2024-10-10 01:01:17 +08:00
ligd
a9da6ab4b5 arm-M: set current regs for crash dump 
Signed-off-by: ligd <liguiding1@xiaomi.com>
 2024-10-10 01:01:17 +08:00
ligd
780acd7827 armv6/7/8m: use pendsv to handle context switch 
This PR support Nested interrupt in armv6/7/8m:

There are two types of nested interrupt model:

Zero latency nested interrupt
Interrupt           Priority            Note
Data abort          Highest
SVC                 0x50
High irq1           0x60             ISR can't access system API
irq_save()          0x70
High irq2           0x80             ISR can't access system API
normal irq3         0xB0
We have already support this mode before this PR

Nested interrupt which interrupt level lower than up_irq_save()
Interrupt           Priority            Note
Data abort          Highest
SVC                 0x70
irq_save()          0x80
High irq1           0x90              ISR can access system API
High irq2           0xA0              ISR can access system API
normal irq3         0xB0
Now, this PR can support this mode

Signed-off-by: ligd <liguiding1@xiaomi.com>
 2024-10-10 01:01:17 +08:00
ligd
f221c9ecb4 armv6m: add up_trigger_irq() support 
Signed-off-by: ligd <liguiding1@xiaomi.com>
 2024-10-10 01:01:17 +08:00
ligd
f20ae064b0 armv7/8m: unmask all the IRQ when thread start 
NVIC_SYSH_PRIORITY_MIN not the basepri loweest prio
spec says:
basepri 0 - Disables masking by BASEPRI

Signed-off-by: ligd <liguiding1@xiaomi.com>
 2024-10-10 01:01:17 +08:00
liwenxiang1
4c19e75ff5 libs/x86_64:Add the setjmp/longjmp function 
Signed-off-by: liwenxiang1 <liwenxiang1@xiaomi.com>
 2024-10-09 22:24:03 +08:00
wangmingrong1
47fc3a67f7 sim/kconfig: delete non-existent dependencie 
Signed-off-by: wangmingrong1 <wangmingrong1@xiaomi.com>
 2024-10-09 21:27:47 +08:00
yinshengkai
034af29aab arch: adjust gcov configuration name 
Signed-off-by: yinshengkai <yinshengkai@xiaomi.com>
 2024-10-09 21:27:47 +08:00
liwenxiang1
8fe6c0ee8e arch/x86_64: Map the new page table with read-write permissions 
Signed-off-by: liwenxiang1 <liwenxiang1@xiaomi.com>
 2024-10-09 20:51:58 +08:00
Filipe Cavalcanti
42b7097cc2 xtensa/esp32s3: fix missing peripheral initialization for watchdog timer 2024-10-09 20:49:48 +08:00