1. Since the implementation of gcov has changed since clang17, versions before clang17 need to use the libunwind.a file
Signed-off-by: wangmingrong1 <wangmingrong1@xiaomi.com>
1. CONFIG_ARCH_COVERAGE has been replaced by CONFIG_SCHED_GCOV
2. Delete the SIM-specific GCOV_ALL configuration and change it to a universal configuration for all architectures
Signed-off-by: wangmingrong1 <wangmingrong1@xiaomi.com>
tmpfile.rename(args.output)
^^^^^^^^^^^^^^
AttributeError: '_io.BufferedRandom' object has no attribute 'rename'. Did you mean: 'name'?
Signed-off-by: anjiahao <anjiahao@xiaomi.com>
1. enable CONFIG_BUILTIN_COMPILER_RT to built libclang_rt.builtins-xxx.a and no longer use the compiler's built-in
2. Modify clang version acquisition to get two decimal points
3. It has been ported to support four architectures: ARM, ARM64, RISCV, and x86_64, among which ARM has been validated
Signed-off-by: wangmingrong1 <wangmingrong1@xiaomi.com>
To skip the style issue:
arch/arm/src/phy62xx/uart.c:59:15: error: Mixed case identifier found
arch/arm/src/phy62xx/uart.c:64:2: error: Mixed case identifier found
arch/arm/src/phy62xx/uart.c:65:2: error: Mixed case identifier found
arch/arm/src/phy62xx/uart.c:70:2: error: Mixed case identifier found
arch/arm/src/phy62xx/uart.c:71:2: error: Mixed case identifier found
arch/arm/src/phy62xx/uart.c:75:2: error: Mixed case identifier found
arch/arm/src/phy62xx/uart.c:77:7: error: Mixed case identifier found
Signed-off-by: chao an <anchao@lixiang.com>
This PR splits the CI Build Job sim-01 and adds sim-03:
Before the Split: Simulator Jobs take up to 1.5 hours to complete
- sim-01 (1 hour 31 mins): adb, citest, lvgl, matter
- sim-02 (28 mins): posix_test, sqlite
After the Split: Simulator Jobs will complete within 1 hour
- sim-01 (58 mins): adb, citest
- sim-02 (35 mins): lvgl, matter
- sim-03 (28 mins): posix_test, sqlite
This will help us comply with the ASF Policy for GitHub Actions, as explained here: https://github.com/apache/nuttx/issues/14376
The error was introduced by #14393, which was intended to fix this
line for MacOS. This commit makes this line dependent on the host
OS to avoid any compilation errors.
nucleo-144 combines 3 different ST boards. This approach is inconsistent with
the support for the rest of the nucleo boards, where each board is in separate folders.
Also nucleo-144 is no longer reserved for STM32F7 chips but other families also use this format.
After this commit nucleo-144 is divided into 3 boards:
- nucleo-f746zg
- nucleo-f767zi
- nucleo-f722ze
This PR creates the new CI Build Jobs `arm64-01` and `x86_64-01`. The new jobs will split and offload the Arm64 and x86_64 Build Targets from `other`. This will reduce our usage of GitHub Runners, to comply with the ASF Policy for GitHub Actions. (Recently we see more PRs for Arm64 and x86_64)
Before the Split: Simple PRs (One Arch and/or One Board) for Arm64 and x86_64 require almost 1 hour for CI Build
- `other` (57 mins): AVR, SPARC, x86, PinePhone, QEMU Arm64, QEMU x86_64
After the Split: Simple PRs for Arm64 and x86_64 will complete under 30 mins
- `other` (24 mins): AVR, SPARC, x86
- `arm64-01` (29 mins): PinePhone, QEMU Arm64
- `x86_64-01` (9 mins): QEMU x86_64
To skip more unnecessary builds: Our Build Rules `arch.yml` shall ignore the label "Area: Documentation", so that a Simple PR + Docs is still a Simple PR. Previously we experienced longer CI Build Times, just because we added docs to our Simple PR. (Now our PR shall be built exactly like a Simple PR)
The updated CI code is explained here: https://github.com/apache/nuttx/issues/13775
Renamed savedefconfig -> refreshsilent name more consistent with the refresh stage for cmake on github.
Added new savedefconfig to fix
https://github.com/apache/nuttx/issues/14281
Flag --diff will output the changes content.
Flag --check-only will return exit code. It can be used together with --diff.
Run isort again to format the code in place, to make the behavior same as before.
Signed-off-by: xuxingliang <xuxingliang@xiaomi.com>
Config multi line output to mode 3, so isort and black can agree with
each other:
```
3 - Vertical Hanging Indent
from third_party import (
lib1,
lib2,
lib3,
lib4,
)
```
Signed-off-by: xuxingliang <xuxingliang@xiaomi.com>
Use showsize.sh to show custom elf file top10 size
tools/showsize.sh vela_ap.elf
tools/showsize.sh vela_audio.elf
Signed-off-by: Bowen Wang <wangbowen6@xiaomi.com>
When using include command in defconfig, it is necessary to support overwriting the configuration in other files
kconfig-conf only prints warnings, but does not return errors
Signed-off-by: yinshengkai <yinshengkai@xiaomi.com>
When some coverage files cannot be parsed correctly,
skip the current error file and continue to generate coverage report
Signed-off-by: yinshengkai <yinshengkai@xiaomi.com>
To speed up the CI Workflow, this PR splits the CI Build Jobs for RISC-V into smaller jobs. Each job will now complete within 1 hour.
Before the PR: There are 2 jobs for RISC-V, each requiring more than 1.5 hours
- `risc-v-01` (1 hour 42 mins): BL602, Ox64, ESP32-C3 / C6 / H2
- `risc-v-02` (1 hour 41 mins): K230, Icicle, QEMU, RV32M1-Vega
After the PR: The build is spread across 6 jobs for RISC-V, each job completes within 1 hour
- `risc-v-01` (19 mins): BL602, Ox64
- `risc-v-02` (44 mins): ESP32-C3
- `risc-v-03` (45 mins): ESP32-C6, ESP32-H2
- `risc-v-04` (31 mins): K230, Icicle
- `risc-v-05` (41 mins): QEMU CITest
- `risc-v-06` (38 mins): Rest of QEMU, RV32M1-Vega
Following the same convention as the Arm32 Build Jobs, the above jobs are sorted by Target Name. Performance of the RISC-V Build Jobs is discussed in https://github.com/apache/nuttx/issues/13775
Check g_altpath. If only the CURRENT path is included,
the obj target use its own full path, otherwise just use the filename.
add default value current path for obj-path.
Signed-off-by: xuxin19 <xuxin19@xiaomi.com>
patches ending with cmake should be checked.
Currently, any non-cmake files containing cmake keywords will be checked.
Signed-off-by: xuxin19 <xuxin19@xiaomi.com>
CI Build Job `arm-05` (runtime 2 hours) has become the Performance Bottleneck for CI Workflow. That's because `arm-05` builds too many targets for nRF, RP2040, SAM 3, SAM A and SAM D. This PR splits `arm-05` into multiple smaller jobs, to reduce the CI Build Duration.
Before the PR: `arm-05` is overloaded, build requires 2 hours
- `arm-05` (2 hours): nRF, RP2040, SAM 3, SAM A, SAM D
- `arm-06` (56 mins): STM32 [a-m]*
After the PR: `arm-05` is offloaded (to `arm-06` and `arm-07`), completes within 1 hour
- `arm-05` (47 mins): nRF
- `arm-06` (1 hour): Reserve for RP2040 exclusively
- `arm-07` (1 hour 15 mins): SAM 3, SAM A, SAM D, STM32 [a-m]*
Build Jobs are sorted by Target Name. So we cascade the changes and rename the Build Jobs: `arm-07` becomes `arm-08`, `arm-08` becomes `arm-09` etc. Then `arm-13` becomes a new job `arm-14`. (Which we added to `build.yml`)
Performance of `arm-05` is discussed in https://github.com/apache/nuttx/issues/13775 and https://github.com/apache/nuttx/issues/12773
Add heap current used to note.
Plot it in segger sysview data plot.
Signed-off-by: xuxingliang <xuxingliang@xiaomi.com>
Signed-off-by: Neo Xu <neo.xu1990@gmail.com>
