the author has submitted the CLA and the license can be migrated to ASF
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
both co-authors have submitted the CLA and the license can be migrated to ASF
Co-authored-by: Dong Heng <dongheng@espressif.com>
Co-authored-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
Most tools used for compliance and SBOM generation use SPDX identifiers
This change brings us a step closer to an easy SBOM generation.
Copyright and Author information is missing from the License and was filled with
commit authorship
Signed-off-by: Jakub Janousek <janouja9@fel.cvut.cz>
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
Most tools used for compliance and SBOM generation use SPDX identifiers
This change brings us a step closer to an easy SBOM generation.
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
Since the SCRATCH register is used to store the percpu pointer,
which should not be accessed by other CPUs, we can replace the
critical section with irqsave/irqrestore.
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
This patch allow public arch level code use them, make it possible to access system register in common code, such as percpu.
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
The corespi fpga block supports just one frame length, which is defined when
the block is instantiated on the FPGA.
This adds support for emulating different frame lengths if they are multiples
of 8-bit. That is, with 8-bit corespi one can do 8,16 and 24-bit transfers.
This is implemented by simply writing several 8-bit frames for a single word
when needed.
Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
SPI TX_DONE interrupt can be received after a semaphore timeout,
but before interrupts are disabled. This will leave the semaphore
to the signaled state.
After a timeout the semaphore is always reset to non-signaled state
to fix this race condition.
Signed-off-by: Tero Salminen <tero.salminen@unikie.com>
After https://github.com/apache/nuttx/pull/15075, the static
assertion at `nuttx/arch/xtensa/src/esp32s3/esp32s3_libc_stubs.c`
was being triggered when building any of the ESP32-S3's defconfigs.
This commit updates the reserved size to reflect the changes
introduced by the related PR.
continue work of a68b00206b
| commit a68b00206b
| Author: hujun5 <hujun5@xiaomi.com>
| Date: Mon Dec 9 20:48:09 2024 +0800
|
| cxd56_rtc.c: use small lock in arch/arm/src/cxd56xx/cxd56_rtc.c
|
| reason:
| We hope to remove all instances of spin_lock_irqsave(NULL).
|
| Signed-off-by: hujun5 <hujun5@xiaomi.com>
Signed-off-by: chao an <anchao@lixiang.com>
Used STM32H7 spi driver as a base. The register set is nearly identical. All registers are named the same with the same offset. There are some bits within the registers that are different but are not referenced in stm32_spi.c. Therfore this driver may just work as is. I did modify the clock source selection for each SPI peripheral, but not much else. Differences in the registers were applied in hardware/stm32h5xxx_spi.h.
Added functionality to SPI to configure the SPI RCC clock.
Added SPI info to Kconfig, updated stm32_spi.c to select and set the RCC clock, and other minor updates.
Updated Pin Map for SPI, added CFG1_BPASS support
Fixed redefinition of GPIO_SPI6_SCK_2
Added SPI_MAX_KER_CK definition.
This definition was needed because the H50 chips allow a kernel clock of 250 MHz. However the datasheets for all other chips (H52, H53, H56, H57) have a max of 125 MHz.
Changed SPI Clock Source Configuration
Moved setting of SPIx clock sources to stm32h5xx_rcc.c. STM32_SPIx_FREQUENCY and STM32_RCC_CCIPR3_SPIxSEL are now defined in board.h. Added error checking in stm32_spi.c to make sure STM32_SPIx_FREQUENCY and STM32_RCC_CCIPR3_SPIxSEL are actually defined.
Style updates
Removed SPI Clock selection from Kconfig
Update arch/arm/src/stm32h5/stm32_spi.h
Co-authored-by: hartmannathan <59230071+hartmannathan@users.noreply.github.com>
Update arch/arm/src/stm32h5/Kconfig
Co-authored-by: hartmannathan <59230071+hartmannathan@users.noreply.github.com>
Update arch/arm/src/stm32h5/stm32_spi.h
Co-authored-by: hartmannathan <59230071+hartmannathan@users.noreply.github.com>
L2 needs to be zeroed to make the ECC happy. However, if there's
more than one bootloader in the chain, the cache doesn't need to
be wiped every time. One time is enough. Thus, make this optional
so that it's initialized only when really needed.
Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
There is a race condition when timeout and completion interrupts occur at the same time.
Fix this and simplify the eventwait code.
Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
reason:
svc call may trigger hardfault
Background
The origin of this issue is our desire to eliminate the function of storing
"regs" in g_current_regs and instead utilize (*running_task)->xcp.regs for storage.
The benefits of this approach include faster storage speed and
avoiding multiple accesses to g_current_regs during context switching,
thus ensuring that whether returning from an interrupt or an exception,
we consistently use this_task()->xcp.regs
Issue Encountered
However, when storing registers, we must ensure that (running_task)->xcp.regs is invalid
so that it can be safely overwritten.
According to the existing logic, the only scenario where (running_task)->xcp.regs
is valid is during restore_context. We must accurately identify this scenario.
Initially, we used the condition (running_task)==NULL for this purpose, but we deemed
this approach unsatisfactory as it did not align well with the actual logic.
(running_task) should not be NULL. Consequently, we adopted other arch-specific methods for judgment,
but due to special logic in some arch, the judgment was not accurate, leading to this issue.
Solution:
For armv6-m, we haven't found a more suitable solution, so we are sticking with (*running_task)==NULL.
For armv7-m/armv8-m, by removing support for primask, we can achieve accurate judgment.
PRIMASK is a design in armv6-m, that's why arm introduce BASEPRI from armv7-m.
It's wrong to provide this option for armv7-m/armv8-m arch.
Signed-off-by: hujun5 <hujun5@xiaomi.com>
Most tools used for compliance and SBOM generation use SPDX identifiers
This change brings us a step closer to an easy SBOM generation.
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
This is continue work of https://github.com/apache/nuttx/pull/13726
We can utilize percpu storage to hold information about the
current running task. If we intend to implement this feature, we would
need to define two macros that help us manage this percpu information
effectively.
up_this_task: This macro is designed to read the contents of the percpu
register to retrieve information about the current
running task.This allows us to quickly access
task-specific data without having to disable interrupts,
access global variables and obtain the current cpu index.
up_update_task: This macro is responsible for updating the contents of
the percpu register.It is typically called during
initialization or when a context switch occurs to ensure
that the percpu register reflects the information of the
newly running task.
Signed-off-by: hujun5 <hujun5@xiaomi.com>
Most tools used for compliance and SBOM generation use SPDX identifiers
This change brings us a step closer to an easy SBOM generation.
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
