drivers/bch/bchdev_driver.c: Fix BIOC_FLUSH

Don't fail if the lowerhalf mtd driver doesn't support BIOC_FLUSH; This is normal - if the lowerhalf has nothing to do, it doesn't handle the IOCTL. Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
gcov: Disable stack checking
2024-12-19 19:22:22 +08:00 · 2024-12-19 19:22:12 +08:00 · 2024-12-19 19:22:12 +08:00 · 2024-12-19 19:22:12 +08:00 · 2024-12-19 19:21:27 +08:00 · 2024-12-19 19:20:19 +08:00
427 changed files with 1874 additions and 2355 deletions
--- a/CMakeLists.txt
+++ b/CMakeLists.txt
@ -751,7 +751,7 @@ endif()
 # Generate system map using the compiler toolchain. Conventionally, the tool
 # which dump symbols are called nm, though, some compiler toolchain may have a
 # different name.
-if(NOT WIN32)
+if(NOT CMAKE_HOST_WIN32)
  add_custom_command(
    OUTPUT System.map
    COMMAND
--- a/Documentation/applications/testing/drivertest/index.rst
+++ b/Documentation/applications/testing/drivertest/index.rst
@ -1,3 +1,5 @@
 ======================================
-``drivertest`` vela cmocka driver test
+``drivertest`` cmocka driver test
 ======================================
+
+This is a test for specific driver or chip based on cmocka.
--- a/Documentation/guides/renode.rst
+++ b/Documentation/guides/renode.rst
@ -7,20 +7,9 @@ framework dedicated for complex embedded systems.

 This page contains notes on running some of NuttX boards on Renode.

-ARM-v7m
-=======
-
-Renode doesn't correctly handle ``SVC`` instruction escalation to HardFault
-when ``PRIMASK=1`` which crashs NuttX in the first ``up_exit()`` call.
-We can work around this problem by enabling BASEPRI::
-
-  CONFIG_ARMV7M_USEBASEPRI=y
-
 stm32f4discovery
 ================

-``CONFIG_ARMV7M_USEBASEPRI=y`` must be set.
-
 Renode doesn't support CCM memory, so we have to disable it
 with ``CONFIG_MM_REGIONS=1``.

@ -55,8 +44,6 @@ Doesn't work. No BASEPRI implementation for ``Cotex-M0`` in NuttX.
 nrf52840-dk
 ===========

-``CONFIG_ARMV7M_USEBASEPRI=y`` must be set.
-
 At default Renode uses UART with EasyDMA enabled (UARTE) which is not supported
 by Nuttx yet. We can get around this by creating our own machine description
 based on Renode default implementation::
@ -101,7 +88,7 @@ Known issues:
 stm32f746g-disco
 ================

-``CONFIG_ARMV7M_USEBASEPRI=y`` and ``CONFIG_ARMV7M_BASEPRI_WAR=y`` must be set.
+``CONFIG_ARMV7M_BASEPRI_WAR=y`` must be set.

 Renode script::

@ -131,8 +118,6 @@ Known issues:
 nucleo-h743zi
 =============

-``CONFIG_ARMV7M_USEBASEPRI=y`` must be set.
-
 Renode doesn't support ``PWR_CSR1_ACTVOSRDY`` bit so we have to disable
 it with ``CONFIG_STM32H7_PWR_IGNORE_ACTVOSRDY=y``.

--- a/Documentation/guides/usingkernelthreads.rst
+++ b/Documentation/guides/usingkernelthreads.rst
@ -43,18 +43,18 @@ Kernel Threads
 ==============

 Kernel threads are really like tasks except that they run inside the operating 
-system and are started with ``kernel_thread()`` which is prototyped in 
+system and are started with ``kthread_create()`` which is prototyped in 
 ``include/nuttx/kthread.h``. The differ from tasks in that (1) in PROTECTED and 
 KERNEL builds, they have full supervisor privileges, and (2) they have full 
 access to all internal OS resources.

 In order to build the task into the OS as a kernel thread, you simply have to: 
 (1) place the kernel thread code in your board source code directory, and (2) 
-start it with ``kernel_thread()`` in your board bring-up logic. There a few 
+start it with ``kthread_create()`` in your board bring-up logic. There a few 
 examples of this in the NuttX source tree. Here is one: 
 `https://github.com/apache/nuttx/blob/master/boards/arm/stm32/viewtool-stm32f107/src/stm32_highpri.c <https://github.com/apache/nuttx/blob/master/boards/arm/stm32/viewtool-stm32f107/src/stm32_highpri.c>`_

 So that is another trick that you can use to architecture optimal solutions: 
 Create parts of your applications as kernel threads: They need to reside in 
-your board/src directory and the need to be started with ``kernel_thread()`` in 
-your board bring-up logic. And that is it.
+your board/src directory and the need to be started with ``kthread_create()`` in 
+your board bring-up logic. And that is it.
--- a/Documentation/guides/zerolatencyinterrupts.rst
+++ b/Documentation/guides/zerolatencyinterrupts.rst
@ -1,5 +1,5 @@
 =====================================================================
-High Performance: Zero Latency Interrupts, Maskable nested interrupts
+High Performance: Zero Latency Interrupts, Maskable Nested Interrupts
 =====================================================================

 Generic Interrupt Handling
@ -125,9 +125,11 @@ The following table shows the priority levels of the Cortex-M family:
  Low  prio IRQ          0xB0
  PendSV                 0xE0

-As you can see, the priority levels of the zero-latency interrupts can
-beyond the critical section and SVC.
-But High prio IRQ can't call OS API.
+Lower priority *numbers* mean a higher priority on this architecture.
+
+As you can see, the zero-latency interrupts have higher priority than
+the critical section and SVC, but with the tradeoff that High prio IRQ
+can't call OS APIs in ISR.


 Maskable Nested Interrupts
@ -162,9 +164,11 @@ The following table shows the priority levels of the Cortex-M family:
  Low  prio IRQ           0xB0
  PendSV                  0xE0

+Lower priority *numbers* mean a higher priority on this architecture.
+
 As you can see, the priority levels of the maskable nested interrupts
-are between the critical section and the low-priority interrupts.
-And High prio IRQ can call OS API in ISR.
+are between the critical section and the low-priority interrupts. In
+this case, High prio IRQ can call OS APIs in ISR.


 Nested Interrupt Handling
@ -216,8 +220,7 @@ Configuration Options

 ``CONFIG_ARCH_HIPRI_INTERRUPT``

-If ``CONFIG_ARMV7M_USEBASEPRI`` is selected, then interrupts will be
-disabled by setting the *BASEPRI* register to
+The OS disables interrupts by setting the *BASEPRI* register to
 ``NVIC_SYSH_DISABLE_PRIORITY`` so that most interrupts will not have
 execution priority. *SVCall* must have execution priority in all
 cases.
@ -255,8 +258,8 @@ priority interrupt response time.
 Hence, if you need to disable the high priority interrupt, you will
 have to disable the interrupt either at the peripheral that generates
 the interrupt or at the interrupt controller, the *NVIC*. Disabling
-global interrupts via the *BASEPRI* register cannot affect high
-priority interrupts.
+global interrupts via the *BASEPRI* register must not be allowed to
+affect high priority interrupts.

 Dependencies
 ------------
@ -287,7 +290,7 @@ There are two ways to do this:
 * Alternatively, you could keep your vectors in FLASH but in order to
  this, you would have to develop your own custom vector table.

-Second, you need to set the priority of your interrupt to *NVIC* to
+Second, you need to set the priority of your interrupt in *NVIC* to
 ``NVIC_SYSH_HIGH_PRIORITY`` using the standard interface:
 ``int up_prioritize_irq(int irq, int priority);``

--- a/Documentation/platforms/arm/stm32f3/boards/stm32f3discovery/index.rst
+++ b/Documentation/platforms/arm/stm32f3/boards/stm32f3discovery/index.rst
@ -109,8 +109,7 @@ Debugging
 If you are going to use a debugger, you should make sure that the following
 settings are selection in your configuration file::

-  CONFIG_DEBUG_SYMBOLS=y     : Enable debug symbols in the build
-  CONFIG_ARMV7M_USEBASEPRI=y : Use the BASEPRI register to disable interrupts
+  CONFIG_DEBUG_SYMBOLS=y : Enable debug symbols in the build

 STM32 ST-LINK Utility
 ---------------------
--- a/Documentation/platforms/arm/stm32l1/boards/stm32ldiscovery/index.rst
+++ b/Documentation/platforms/arm/stm32l1/boards/stm32ldiscovery/index.rst
@ -225,8 +225,7 @@ Debugging
 If you are going to use a debugger, you should make sure that the following
 settings are selection in your configuration file::

-    CONFIG_DEBUG_SYMBOLS=y     : Enable debug symbols in the build
-    CONFIG_ARMV7M_USEBASEPRI=y : Use the BASEPRI register to disable interrupts
+    CONFIG_DEBUG_SYMBOLS=y : Enable debug symbols in the build

 STM32 ST-LINK Utility
 ---------------------
--- a/arch/Kconfig
+++ b/arch/Kconfig
@ -1279,11 +1279,6 @@ config ARCH_HIPRI_INTERRUPT
 		is extended to any other family, then this discussion will have to
 		be generalized.

-		If ARMV7M_USEBASEPRI is selected, then interrupts will be disabled
-		by setting the BASEPRI register to NVIC_SYSH_DISABLE_PRIORITY so
-		that most interrupts will not have execution priority.  SVCall must
-		have execution priority in all cases.
-
 		In the normal cases, interrupts are not nest-able and all interrupts
 		run at an execution priority between NVIC_SYSH_PRIORITY_MIN and
 		NVIC_SYSH_PRIORITY_MAX (with NVIC_SYSH_PRIORITY_MAX reserved for
--- a/arch/arm/include/armv7-m/irq.h
+++ b/arch/arm/include/armv7-m/irq.h
@ -65,11 +65,7 @@
 */

 #define REG_R13             (0)  /* R13 = SP at time of interrupt */
-#ifdef CONFIG_ARMV7M_USEBASEPRI
-#  define REG_BASEPRI       (1)  /* BASEPRI */
-#else
-#  define REG_PRIMASK       (1)  /* PRIMASK */
-#endif
+#define REG_BASEPRI         (1)  /* BASEPRI */
 #define REG_R4              (2)  /* R4 */
 #define REG_R5              (3)  /* R5 */
 #define REG_R6              (4)  /* R6 */
@ -385,13 +381,9 @@ static inline void raisebasepri(uint32_t basepri)
 static inline void up_irq_disable(void) always_inline_function;
 static inline void up_irq_disable(void)
 {
-#ifdef CONFIG_ARMV7M_USEBASEPRI
  /* Probably raising priority */

  raisebasepri(NVIC_SYSH_DISABLE_PRIORITY);
-#else
-  __asm__ __volatile__ ("\tcpsid  i\n");
-#endif
 }

 /* Save the current primask state & disable IRQs */
@ -400,31 +392,11 @@ static inline irqstate_t up_irq_save(void)
 always_inline_function noinstrument_function;
 static inline irqstate_t up_irq_save(void)
 {
-#ifdef CONFIG_ARMV7M_USEBASEPRI
  /* Probably raising priority */

  uint8_t basepri = getbasepri();
  raisebasepri(NVIC_SYSH_DISABLE_PRIORITY);
  return (irqstate_t)basepri;
-
-#else
-
-  unsigned short primask;
-
-  /* Return the current value of primask register and set
-   * bit 0 of the primask register to disable interrupts
-   */
-
-  __asm__ __volatile__
-    (
-     "\tmrs    %0, primask\n"
-     "\tcpsid  i\n"
-     : "=r" (primask)
-     :
-     : "memory");
-
-  return primask;
-#endif
 }

 /* Enable IRQs */
@ -444,27 +416,9 @@ static inline void up_irq_restore(irqstate_t flags)
 always_inline_function noinstrument_function;
 static inline void up_irq_restore(irqstate_t flags)
 {
-#ifdef CONFIG_ARMV7M_USEBASEPRI
  /* In this case, we are always retaining or lowering the priority value */

  setbasepri((uint32_t)flags);
-
-#else
-  /* If bit 0 of the primask is 0, then we need to restore
-   * interrupts.
-   */
-
-  __asm__ __volatile__
-    (
-      "\ttst    %0, #1\n"
-      "\tbne.n  1f\n"
-      "\tcpsie  i\n"
-      "1:\n"
-      :
-      : "r" (flags)
-      : "cc", "memory");
-
-#endif
 }

 /* Get/set IPSR */
--- a/arch/arm/include/armv7-m/nvicpri.h
+++ b/arch/arm/include/armv7-m/nvicpri.h
@ -33,12 +33,7 @@
 * Pre-processor Prototypes
 ****************************************************************************/

-/* If CONFIG_ARMV7M_USEBASEPRI is selected, then interrupts will be disabled
- * by setting the BASEPRI register to NVIC_SYSH_DISABLE_PRIORITY so that most
- * interrupts will not have execution priority.  SVCall must have execution
- * priority in all cases.
- *
- * In the normal cases, interrupts are not nest-able and all interrupts run
+/* In the normal cases, interrupts are not nest-able and all interrupts run
 * at an execution priority between NVIC_SYSH_PRIORITY_MIN and
 * NVIC_SYSH_PRIORITY_MAX (with NVIC_SYSH_PRIORITY_MAX reserved for SVCall).
 *
--- a/arch/arm/include/armv8-m/irq.h
+++ b/arch/arm/include/armv8-m/irq.h
@ -65,11 +65,7 @@
 */

 #define REG_R13             (0)  /* R13 = SP at time of interrupt */
-#ifdef CONFIG_ARMV8M_USEBASEPRI
-#  define REG_BASEPRI       (1)  /* BASEPRI */
-#else
-#  define REG_PRIMASK       (1)  /* PRIMASK */
-#endif
+#define REG_BASEPRI         (1)  /* BASEPRI */
 #define REG_R4              (2)  /* R4 */
 #define REG_R5              (3)  /* R5 */
 #define REG_R6              (4)  /* R6 */
@ -358,13 +354,9 @@ static inline void setbasepri(uint32_t basepri)
 static inline void up_irq_disable(void) always_inline_function;
 static inline void up_irq_disable(void)
 {
-#ifdef CONFIG_ARMV8M_USEBASEPRI
  /* Probably raising priority */

  raisebasepri(NVIC_SYSH_DISABLE_PRIORITY);
-#else
-  __asm__ __volatile__ ("\tcpsid  i\n");
-#endif
 }

 /* Save the current primask state & disable IRQs */
@ -373,31 +365,11 @@ static inline irqstate_t up_irq_save(void)
 always_inline_function noinstrument_function;
 static inline irqstate_t up_irq_save(void)
 {
-#ifdef CONFIG_ARMV8M_USEBASEPRI
  /* Probably raising priority */

  uint8_t basepri = getbasepri();
  raisebasepri(NVIC_SYSH_DISABLE_PRIORITY);
  return (irqstate_t)basepri;
-
-#else
-
-  unsigned short primask;
-
-  /* Return the current value of primask register and set
-   * bit 0 of the primask register to disable interrupts
-   */
-
-  __asm__ __volatile__
-    (
-     "\tmrs    %0, primask\n"
-     "\tcpsid  i\n"
-     : "=r" (primask)
-     :
-     : "memory");
-
-  return primask;
-#endif
 }

 /* Enable IRQs */
@ -417,27 +389,9 @@ static inline void up_irq_restore(irqstate_t flags)
 always_inline_function noinstrument_function;
 static inline void up_irq_restore(irqstate_t flags)
 {
-#ifdef CONFIG_ARMV8M_USEBASEPRI
  /* In this case, we are always retaining or lowering the priority value */

  setbasepri((uint32_t)flags);
-
-#else
-  /* If bit 0 of the primask is 0, then we need to restore
-   * interrupts.
-   */
-
-  __asm__ __volatile__
-    (
-      "\ttst    %0, #1\n"
-      "\tbne.n  1f\n"
-      "\tcpsie  i\n"
-      "1:\n"
-      :
-      : "r" (flags)
-      : "cc", "memory");
-
-#endif
 }

 /* Get/set IPSR */
--- a/arch/arm/include/armv8-m/nvicpri.h
+++ b/arch/arm/include/armv8-m/nvicpri.h
@ -33,12 +33,7 @@
 * Pre-processor Prototypes
 ****************************************************************************/

-/* If CONFIG_ARMV8M_USEBASEPRI is selected, then interrupts will be disabled
- * by setting the BASEPRI register to NVIC_SYSH_DISABLE_PRIORITY so that most
- * interrupts will not have execution priority.  SVCall must have execution
- * priority in all cases.
- *
- * In the normal cases, interrupts are not nest-able and all interrupts run
+/* In the normal cases, interrupts are not nest-able and all interrupts run
 * at an execution priority between NVIC_SYSH_PRIORITY_MIN and
 * NVIC_SYSH_PRIORITY_MAX (with NVIC_SYSH_PRIORITY_MAX reserved for SVCall).
 *
--- a/arch/arm/include/types.h
+++ b/arch/arm/include/types.h
@ -112,7 +112,7 @@ typedef unsigned int            _size_t;
 */

 #ifdef __thumb2__
-#if defined(CONFIG_ARMV7M_USEBASEPRI) || defined(CONFIG_ARCH_ARMV6M) || defined(CONFIG_ARMV8M_USEBASEPRI)
+#if defined(CONFIG_ARCH_ARMV6M) || defined(CONFIG_ARCH_ARMV7M) || defined(CONFIG_ARCH_ARMV8M)
 typedef unsigned char           irqstate_t;
 #else
 typedef unsigned short          irqstate_t;
--- a/arch/arm/src/armv6-m/arm_doirq.c
+++ b/arch/arm/src/armv6-m/arm_doirq.c
@ -65,7 +65,7 @@ uint32_t *arm_doirq(int irq, uint32_t *regs)
   * is invalid, and we can safely overwrite it.
   */

-  if (!(NVIC_IRQ_SVCALL == irq && regs[REG_R0] == SYS_restore_context))
+  if (*running_task != NULL)
    {
      tcb->xcp.regs = regs;
    }
--- a/arch/arm/src/armv6-m/arm_sigdeliver.c
+++ b/arch/arm/src/armv6-m/arm_sigdeliver.c
@ -165,6 +165,7 @@ retry:
  rtcb->irqcount--;
 #endif

+  g_running_tasks[this_cpu()] = NULL;
  rtcb->xcp.regs = rtcb->xcp.saved_regs;
  arm_fullcontextrestore();
  UNUSED(regs);
--- a/arch/arm/src/armv7-m/Kconfig
+++ b/arch/arm/src/armv7-m/Kconfig
@ -13,30 +13,10 @@ config ARMV7M_HAVE_DCACHE
 	bool
 	default n

-config ARMV7M_USEBASEPRI
-	bool "Use BASEPRI Register"
-	default ARCH_HIPRI_INTERRUPT
-	depends on ARCH_CORTEXM3 || ARCH_CORTEXM4 || ARCH_CORTEXM7
-	---help---
-		Use the BASEPRI register to enable and disable interrupts. By
-		default, the PRIMASK register is used for this purpose. This
-		usually results in hardfaults when supervisor calls are made.
-		Though, these hardfaults are properly handled by the RTOS, the
-		hardfaults can confuse some debuggers. With the BASEPRI
-		register, these hardfaults, will be avoided. For more details see
-		https://cwiki.apache.org/confluence/display/NUTTX/ARMv7-M+Hardfaults%2C+SVCALL%2C+and+Debuggers
-
-		WARNING:  If CONFIG_ARCH_HIPRI_INTERRUPT is selected, then you
-		MUST select CONFIG_ARMV7M_USEBASEPRI.  The Kconfig dependencies
-		here will permit to select an invalid configuration because it
-		cannot enforce that requirement.  If you create this invalid
-		configuration, you will encounter some problems that may be
-		very difficult to debug.
-
 config ARMV7M_BASEPRI_WAR
 	bool "Cortex-M7 r0p1 Errata 837070 Workaround"
 	default n
-	depends on ARMV7M_USEBASEPRI && ARCH_CORTEXM7
+	depends on ARCH_CORTEXM7
 	---help---
 		Enable workaround for r0p1 Errata 837070: Increasing priority using
 		write to BASEPRI does not take effect immediately.
--- a/arch/arm/src/armv7-m/arm_exception.S
+++ b/arch/arm/src/armv7-m/arm_exception.S
@ -71,14 +71,6 @@

 #  if defined(CONFIG_BUILD_PROTECTED) && CONFIG_ARCH_INTERRUPTSTACK < 8
 #    error Interrupt stack must be used with high priority interrupts in protected mode
-#  endif
-
-  /* Use the BASEPRI to control interrupts is required if nested, high
-   * priority interrupts are supported.
-   */
-
-#  ifndef CONFIG_ARMV7M_USEBASEPRI
-#    error CONFIG_ARMV7M_USEBASEPRI must be used with CONFIG_ARCH_HIPRI_INTERRUPT
 #  endif
 #endif

@ -151,11 +143,8 @@ exception_common:
 	mov		r2, r1					/* R2=Copy of the main/process stack pointer */
 	add		r2, #HW_XCPT_SIZE			/* R2=MSP/PSP before the interrupt was taken */
 								/* (ignoring the xPSR[9] alignment bit) */
-#ifdef CONFIG_ARMV7M_USEBASEPRI
+
 	mrs		r3, basepri				/* R3=Current BASEPRI setting */
-#else
-	mrs		r3, primask				/* R3=Current PRIMASK setting */
-#endif

 #ifdef CONFIG_ARCH_FPU

@ -237,11 +226,7 @@ exception_common:

 	/* Restore the interrupt state */

-#ifdef CONFIG_ARMV7M_USEBASEPRI
 	msr		basepri, r3				/* Restore interrupts priority masking */
-#else
-	msr		primask, r3				/* Restore interrupts */
-#endif

 	msr		control, r12				/* Restore control */

--- a/arch/arm/src/armv7-m/arm_hardfault.c
+++ b/arch/arm/src/armv7-m/arm_hardfault.c
@ -42,10 +42,6 @@
 * Pre-processor Definitions
 ****************************************************************************/

-/* If CONFIG_ARMV7M_USEBASEPRI=n, then debug output from this file may
- * interfere with context switching!
- */
-
 #ifdef CONFIG_DEBUG_HARDFAULT_ALERT
 #  define hfalert(format, ...) _alert(format, ##__VA_ARGS__)
 #else
@ -79,50 +75,7 @@ int arm_hardfault(int irq, void *context, void *arg)
  uint32_t cfsr = getreg32(NVIC_CFAULTS);

  UNUSED(cfsr);
-
-  /* Get the value of the program counter where the fault occurred */
-
-#ifndef CONFIG_ARMV7M_USEBASEPRI
-  uint32_t *regs = (uint32_t *)context;
-  uint16_t *pc = (uint16_t *)regs[REG_PC] - 1;
-
-  /* Check if the pc lies in known FLASH memory.
-   * REVISIT:  What if the PC lies in "unknown" external memory?  Best
-   * use the BASEPRI register if you have external memory.
-   */
-
-#ifdef CONFIG_BUILD_PROTECTED
-  /* In the kernel build, SVCalls are expected in either the base, kernel
-   * FLASH region or in the user FLASH region.
-   */
-
-  if (((uintptr_t)pc >= (uintptr_t)_START_TEXT &&
-       (uintptr_t)pc <  (uintptr_t)_END_TEXT) ||
-      ((uintptr_t)pc >= (uintptr_t)USERSPACE->us_textstart &&
-       (uintptr_t)pc <  (uintptr_t)USERSPACE->us_textend))
-#else
-  /* SVCalls are expected only from the base, kernel FLASH region */
-
-  if ((uintptr_t)pc >= (uintptr_t)_START_TEXT &&
-      (uintptr_t)pc <  (uintptr_t)_END_TEXT)
-#endif
-    {
-      /* Fetch the instruction that caused the Hard fault */
-
-      uint16_t insn = *pc;
-      hfinfo("  PC: %p INSN: %04x\n", pc, insn);
-
-      /* If this was the instruction 'svc 0', then forward processing
-       * to the SVCall handler
-       */
-
-      if (insn == INSN_SVC0)
-        {
-          hfinfo("Forward SVCall\n");
-          return arm_svcall(irq, context, arg);
-        }
-    }
-#endif
+  UNUSED(hfsr);

  if (hfsr & NVIC_HFAULTS_FORCED)
    {
--- a/arch/arm/src/armv7-m/arm_initialstate.c
+++ b/arch/arm/src/armv7-m/arm_initialstate.c
@ -161,19 +161,9 @@ void up_initial_state(struct tcb_s *tcb)
  /* Enable or disable interrupts, based on user configuration */

 #ifdef CONFIG_SUPPRESS_INTERRUPTS
-
-#ifdef CONFIG_ARMV7M_USEBASEPRI
  xcp->regs[REG_BASEPRI] = NVIC_SYSH_DISABLE_PRIORITY;
-#else
-  xcp->regs[REG_PRIMASK] = 1;
-#endif
-
 #else /* CONFIG_SUPPRESS_INTERRUPTS */
-
-#ifdef CONFIG_ARMV7M_USEBASEPRI
  xcp->regs[REG_BASEPRI] = 0;
-#endif
-
 #endif /* CONFIG_SUPPRESS_INTERRUPTS */
 }

--- a/arch/arm/src/armv7-m/arm_itm.c
+++ b/arch/arm/src/armv7-m/arm_itm.c
@ -1,9 +1,13 @@
 /****************************************************************************
 * arch/arm/src/armv7-m/arm_itm.c
 *
- *   Copyright (c) 2009 - 2013 ARM LIMITED
+ * SPDX-License-Identifier: BSD-3-Clause
+ * SPDX-FileCopyrightText: 2014 Pierre-noel Bouteville. All rights reserved.
+ * SPDX-FileCopyrightText: 2014 Gregory Nutt. All rights reserved.
+ * SPDX-FileCopyrightText: 2009 - 2013 ARM LIMITED
+ * SPDX-FileContributor: Pierre-noel Bouteville <pnb990@gmail.com>
+ * SPDX-FileContributor: Gregory Nutt <gnutt@nuttx.org>
 *
- *  All rights reserved.
 *  Redistribution and use in source and binary forms, with or without
 *  modification, are permitted provided that the following conditions are
 *  met:
@ -29,11 +33,6 @@
 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
- *   Copyright (C) 2014 Pierre-noel Bouteville . All rights reserved.
- *   Copyright (C) 2014 Gregory Nutt. All rights reserved.
- *   Authors: Pierre-noel Bouteville <pnb990@gmail.com>
- *            Gregory Nutt <gnutt@nuttx.org>
- *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
--- a/arch/arm/src/armv7-m/arm_saveusercontext.S
+++ b/arch/arm/src/armv7-m/arm_saveusercontext.S
@ -91,11 +91,7 @@ up_saveusercontext:
 	/* Save r13, primask, r4~r11 */

 	mov		r2, sp
-#ifdef CONFIG_ARMV7M_USEBASEPRI
 	mrs		r3, basepri
-#else
-	mrs		r3, primask
-#endif
 	stmia		r0!, {r2-r11}

 	/* Save EXC_RETURN to 0xffffffff */
--- a/arch/arm/src/armv7-m/arm_schedulesigaction.c
+++ b/arch/arm/src/armv7-m/arm_schedulesigaction.c
@ -138,11 +138,7 @@ void up_schedule_sigaction(struct tcb_s *tcb)
       */

      tcb->xcp.regs[REG_PC]         = (uint32_t)arm_sigdeliver;
-#ifdef CONFIG_ARMV7M_USEBASEPRI
      tcb->xcp.regs[REG_BASEPRI]    = NVIC_SYSH_DISABLE_PRIORITY;
-#else
-      tcb->xcp.regs[REG_PRIMASK]    = 1;
-#endif
      tcb->xcp.regs[REG_XPSR]       = ARMV7M_XPSR_T;
 #ifdef CONFIG_BUILD_PROTECTED
      tcb->xcp.regs[REG_LR]         = EXC_RETURN_THREAD;
--- a/arch/arm/src/armv7-m/arm_sigdeliver.c
+++ b/arch/arm/src/armv7-m/arm_sigdeliver.c
@ -89,11 +89,7 @@ retry:

  while (rtcb->irqcount > 0)
    {
-#ifdef CONFIG_ARMV7M_USEBASEPRI
      leave_critical_section((uint8_t)regs[REG_BASEPRI]);
-#else
-      leave_critical_section((uint16_t)regs[REG_PRIMASK]);
-#endif
    }
 #endif /* CONFIG_SMP */

@ -139,11 +135,7 @@ retry:
      (rtcb->flags & TCB_FLAG_SIGNAL_ACTION) == 0)
    {
 #ifdef CONFIG_SMP
-#  ifdef CONFIG_ARMV7M_USEBASEPRI
      leave_critical_section((uint8_t)regs[REG_BASEPRI]);
-#  else
-      leave_critical_section((uint16_t)regs[REG_PRIMASK]);
-#  endif
 #endif
      goto retry;
    }
@ -169,11 +161,7 @@ retry:
  /* We need to keep the IRQ lock until task switching */

  rtcb->irqcount++;
-#ifdef CONFIG_ARMV7M_USEBASEPRI
  leave_critical_section((uint8_t)regs[REG_BASEPRI]);
-#else
-  leave_critical_section((uint16_t)regs[REG_PRIMASK]);
-#endif
  rtcb->irqcount--;
 #endif

--- a/arch/arm/src/armv7-m/arm_tcbinfo.c
+++ b/arch/arm/src/armv7-m/arm_tcbinfo.c
@ -57,13 +57,8 @@ static const uint16_t g_reg_offs[] =
 #if 0
  UINT16_MAX,                         /* msp */
  TCB_REG_OFF(REG_R13),
-#  ifdef CONFIG_ARMV7M_USEBASEPRI
  UINT16_MAX,                         /* primask */
  TCB_REG_OFF(REG_BASEPRI),
-#  else
-  TCB_REG_OFF(REG_PRIMASK),
-  UINT16_MAX,                         /* basepri */
-#  endif
  UINT16_MAX,                         /* faultmask */
  UINT16_MAX,                         /* control */

--- a/arch/arm/src/armv7-m/dwt.h
+++ b/arch/arm/src/armv7-m/dwt.h
@ -1,9 +1,10 @@
 /****************************************************************************
 * arch/arm/src/armv7-m/dwt.h
 *
- *   Copyright (c) 2009 - 2013 ARM LIMITED
- *
- *  All rights reserved.
+ * SPDX-License-Identifier: BSD-3-Clause
+ * SPDX-FileCopyrightText: 2014 Pierre-noel Bouteville. All rights reserved.
+ * SPDX-FileCopyrightText: 2009 - 2013 ARM LIMITED
+ * SPDX-FileContributor: Pierre-noel Bouteville <pnb990@gmail.com>
 *
 *  Redistribution and use in source and binary forms, with or without
 *  modification, are permitted provided that the following conditions
@ -30,9 +31,6 @@
 *  NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
 *  SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
- *   Copyright (C) 2014 Pierre-noel Bouteville . All rights reserved.
- *   Author: Pierre-noel Bouteville <pnb990@gmail.com>
- *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
--- a/arch/arm/src/armv7-m/etm.h
+++ b/arch/arm/src/armv7-m/etm.h
@ -1,7 +1,12 @@
 /****************************************************************************
 * arch/arm/src/armv7-m/etm.h
 *
- *  Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ * SPDX-License-Identifier: BSD-3-Clause
+ * SPDX-FileCopyrightText: 2014 Pierre-noel Bouteville. All rights reserved.
+ * SPDX-FileCopyrightText: 2014 Gregory Nutt. All rights reserved.
+ * SPDX-FileCopyrightText: 2014 2014 Silicon Laboratories, Inc.
+ * SPDX-FileContributor: Pierre-noel Bouteville <pnb990@gmail.com>
+ * SPDX-FileContributor: Gregory Nutt <gnutt@nuttx.org>
 *
 * Permission is granted to anyone to use this software for any purpose,
 * including commercial applications, and to alter it and redistribute it
@ -24,11 +29,6 @@
 * incidental, or special damages, or any other relief, or for any claim by
 * any third party, arising from your use of this Software.
 *
- *   Copyright (C) 2014 Pierre-noel Bouteville . All rights reserved.
- *   Copyright (C) 2014 Gregory Nutt. All rights reserved.
- *   Authors: Pierre-noel Bouteville <pnb990@gmail.com>
- *            Gregory Nutt <gnutt@nuttx.org>
- *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
--- a/arch/arm/src/armv7-m/itm.h
+++ b/arch/arm/src/armv7-m/itm.h
@ -1,9 +1,11 @@
 /****************************************************************************
 * arch/arm/src/armv7-m/itm.h
 *
- *   Copyright (c) 2009 - 2013 ARM LIMITED
+ * SPDX-License-Identifier: BSD-3-Clause
+ * SPDX-FileCopyrightText: 2014 Pierre-noel Bouteville. All rights reserved.
+ * SPDX-FileCopyrightText: 2009 - 2013 ARM LIMITED
+ * SPDX-FileContributor: Pierre-noel Bouteville <pnb990@gmail.com>
 *
- *  All rights reserved.
 *  Redistribution and use in source and binary forms, with or without
 *  modification, are permitted provided that the following conditions
 *  are met:
@ -29,9 +31,6 @@
 *  NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
 *  SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
- *   Copyright (C) 2014 Pierre-noel Bouteville . All rights reserved.
- *   Author: Pierre-noel Bouteville <pnb990@gmail.com>
- *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
--- a/arch/arm/src/armv7-m/tpi.h
+++ b/arch/arm/src/armv7-m/tpi.h
@ -1,9 +1,11 @@
 /****************************************************************************
 * arch/arm/src/armv7-m/tpi.h
 *
- *   Copyright (c) 2009 - 2013 ARM LIMITED
+ * SPDX-License-Identifier: BSD-3-Clause
+ * SPDX-FileCopyrightText: 2014 Pierre-noel Bouteville. All rights reserved.
+ * SPDX-FileCopyrightText: 2009 - 2013 ARM LIMITED
+ * SPDX-FileContributor: Pierre-noel Bouteville <pnb990@gmail.com>
 *
- *  All rights reserved.
 *  Redistribution and use in source and binary forms, with or without
 *  modification, are permitted provided that the following conditions
 *  are met:
@ -29,9 +31,6 @@
 *  NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
 *  SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
- *   Copyright (C) 2014 Pierre-noel Bouteville . All rights reserved.
- *   Author: Pierre-noel Bouteville <pnb990@gmail.com>
- *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
--- a/arch/arm/src/armv8-m/Kconfig
+++ b/arch/arm/src/armv8-m/Kconfig
@ -13,25 +13,6 @@ config ARMV8M_HAVE_DCACHE
 	bool
 	default n

-config ARMV8M_USEBASEPRI
-	bool "Use BASEPRI Register"
-	default ARCH_HIPRI_INTERRUPT
-	---help---
-		Use the BASEPRI register to enable and disable interrupts. By
-		default, the PRIMASK register is used for this purpose. This
-		usually results in hardfaults when supervisor calls are made.
-		Though, these hardfaults are properly handled by the RTOS, the
-		hardfaults can confuse some debuggers. With the BASEPRI
-		register, these hardfaults, will be avoided. For more details see
-		https://cwiki.apache.org/confluence/display/NUTTX/ARMv7-M+Hardfaults%2C+SVCALL%2C+and+Debuggers
-
-		WARNING:  If CONFIG_ARCH_HIPRI_INTERRUPT is selected, then you
-		MUST select CONFIG_ARMV8M_USEBASEPRI.  The Kconfig dependencies
-		here will permit to select an invalid configuration because it
-		cannot enforce that requirement.  If you create this invalid
-		configuration, you will encounter some problems that may be
-		very difficult to debug.
-
 config ARMV8M_ICACHE
 	bool "Use I-Cache"
 	default n
--- a/arch/arm/src/armv8-m/arm_cache.c
+++ b/arch/arm/src/armv8-m/arm_cache.c
@ -1,14 +1,11 @@
 /****************************************************************************
 * arch/arm/src/armv8-m/arm_cache.c
 *
- *   Copyright (C) 2015, 2018-2019 Gregory Nutt. All rights reserved.
- *   Author: Gregory Nutt <gnutt@nuttx.org>
- *           Bob Feretich <bob.feretich@rafresearch.com>
- *
- * Some logic in this header file derives from the ARM CMSIS core_cm7.h
- * header file which has a compatible 3-clause BSD license:
- *
- *   Copyright (c) 2009 - 2014 ARM LIMITED.  All rights reserved.
+ * SPDX-License-Identifier: BSD-3-Clause
+ * SPDX-FileCopyrightText: 2015, 2018-2019 Gregory Nutt. All rights reserved.
+ * SPDX-FileCopyrightText: 2009 - 2014 ARM LIMITED.  All rights reserved.
+ * SPDX-FileContributor: Gregory Nutt <gnutt@nuttx.org>
+ * SPDX-FileContributor: Bob Feretich <bob.feretich@rafresearch.com>
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
--- a/arch/arm/src/armv8-m/arm_exception.S
+++ b/arch/arm/src/armv8-m/arm_exception.S
@ -72,14 +72,6 @@

 #  if defined(CONFIG_BUILD_PROTECTED) && CONFIG_ARCH_INTERRUPTSTACK < 8
 #    error Interrupt stack must be used with high priority interrupts in protected mode
-#  endif
-
-  /* Use the BASEPRI to control interrupts is required if nested, high
-   * priority interrupts are supported.
-   */
-
-#  ifndef CONFIG_ARMV8M_USEBASEPRI
-#    error CONFIG_ARMV8M_USEBASEPRI must be used with CONFIG_ARCH_HIPRI_INTERRUPT
 #  endif
 #endif

@ -154,11 +146,7 @@ exception_common:
 	stmdb		r1!, {r0}
 #endif

-#ifdef CONFIG_ARMV8M_USEBASEPRI
 	mrs		r3, basepri				/* R3=Current BASEPRI setting */
-#else
-	mrs		r3, primask				/* R3=Current PRIMASK setting */
-#endif

 #ifdef CONFIG_ARCH_FPU

@ -258,11 +246,7 @@ exception_common:

 	/* Restore the interrupt state */

-#ifdef CONFIG_ARMV8M_USEBASEPRI
 	msr		basepri, r3				/* Restore interrupts priority masking */
-#else
-	msr		primask, r3				/* Restore interrupts */
-#endif

 	msr		control, r12

--- a/arch/arm/src/armv8-m/arm_hardfault.c
+++ b/arch/arm/src/armv8-m/arm_hardfault.c
@ -42,10 +42,6 @@
 * Pre-processor Definitions
 ****************************************************************************/

-/* If CONFIG_ARMV8M_USEBASEPRI=n, then debug output from this file may
- * interfere with context switching!
- */
-
 #ifdef CONFIG_DEBUG_HARDFAULT_ALERT
 #  define hfalert(format, ...) _alert(format, ##__VA_ARGS__)
 #else
@ -82,50 +78,7 @@ int arm_hardfault(int irq, void *context, void *arg)
 #endif /* CONFIG_DEBUG_SECUREFAULT */

  UNUSED(cfsr);
-
-  /* Get the value of the program counter where the fault occurred */
-
-#ifndef CONFIG_ARMV8M_USEBASEPRI
-  uint32_t *regs = (uint32_t *)context;
-  uint16_t *pc = (uint16_t *)regs[REG_PC] - 1;
-
-  /* Check if the pc lies in known FLASH memory.
-   * REVISIT:  What if the PC lies in "unknown" external memory?  Best
-   * use the BASEPRI register if you have external memory.
-   */
-
-#ifdef CONFIG_BUILD_PROTECTED
-  /* In the kernel build, SVCalls are expected in either the base, kernel
-   * FLASH region or in the user FLASH region.
-   */
-
-  if (((uintptr_t)pc >= (uintptr_t)_START_TEXT &&
-       (uintptr_t)pc <  (uintptr_t)_END_TEXT) ||
-      ((uintptr_t)pc >= (uintptr_t)USERSPACE->us_textstart &&
-       (uintptr_t)pc <  (uintptr_t)USERSPACE->us_textend))
-#else
-  /* SVCalls are expected only from the base, kernel FLASH region */
-
-  if ((uintptr_t)pc >= (uintptr_t)_START_TEXT &&
-      (uintptr_t)pc <  (uintptr_t)_END_TEXT)
-#endif
-    {
-      /* Fetch the instruction that caused the Hard fault */
-
-      uint16_t insn = *pc;
-      hfinfo("  PC: %p INSN: %04x\n", pc, insn);
-
-      /* If this was the instruction 'svc 0', then forward processing
-       * to the SVCall handler
-       */
-
-      if (insn == INSN_SVC0)
-        {
-          hfinfo("Forward SVCall\n");
-          return arm_svcall(irq, context, arg);
-        }
-    }
-#endif
+  UNUSED(hfsr);

  if (hfsr & NVIC_HFAULTS_FORCED)
    {
--- a/arch/arm/src/armv8-m/arm_initialstate.c
+++ b/arch/arm/src/armv8-m/arm_initialstate.c
@ -168,17 +168,11 @@ void up_initial_state(struct tcb_s *tcb)

 #ifdef CONFIG_SUPPRESS_INTERRUPTS

-#ifdef CONFIG_ARMV8M_USEBASEPRI
  xcp->regs[REG_BASEPRI] = NVIC_SYSH_DISABLE_PRIORITY;
-#else
-  xcp->regs[REG_PRIMASK] = 1;
-#endif

 #else /* CONFIG_SUPPRESS_INTERRUPTS */

-#ifdef CONFIG_ARMV8M_USEBASEPRI
  xcp->regs[REG_BASEPRI] = 0;
-#endif

 #endif /* CONFIG_SUPPRESS_INTERRUPTS */
 }
--- a/arch/arm/src/armv8-m/arm_saveusercontext.S
+++ b/arch/arm/src/armv8-m/arm_saveusercontext.S
@ -83,11 +83,7 @@ up_saveusercontext:
 	/* Save r13, primask, r4~r11 */

 	mov		r2, sp
-#ifdef CONFIG_ARMV7M_USEBASEPRI
 	mrs		r3, basepri
-#else
-	mrs		r3, primask
-#endif
 	stmia		r0!, {r2-r11}

 	/* Save EXC_RETURN to 0xffffffff */
--- a/arch/arm/src/armv8-m/arm_schedulesigaction.c
+++ b/arch/arm/src/armv8-m/arm_schedulesigaction.c
@ -138,11 +138,7 @@ void up_schedule_sigaction(struct tcb_s *tcb)
       */

      tcb->xcp.regs[REG_PC]         = (uint32_t)arm_sigdeliver;
-#ifdef CONFIG_ARMV8M_USEBASEPRI
      tcb->xcp.regs[REG_BASEPRI]    = NVIC_SYSH_DISABLE_PRIORITY;
-#else
-      tcb->xcp.regs[REG_PRIMASK]    = 1;
-#endif
      tcb->xcp.regs[REG_XPSR]       = ARMV8M_XPSR_T;
 #ifdef CONFIG_BUILD_PROTECTED
      tcb->xcp.regs[REG_LR]         = EXC_RETURN_THREAD;
--- a/arch/arm/src/armv8-m/arm_sigdeliver.c
+++ b/arch/arm/src/armv8-m/arm_sigdeliver.c
@ -89,11 +89,7 @@ retry:

  while (rtcb->irqcount > 0)
    {
-#ifdef CONFIG_ARMV8M_USEBASEPRI
      leave_critical_section((uint8_t)regs[REG_BASEPRI]);
-#else
-      leave_critical_section((uint16_t)regs[REG_PRIMASK]);
-#endif
    }
 #endif /* CONFIG_SMP */

@ -139,11 +135,7 @@ retry:
      (rtcb->flags & TCB_FLAG_SIGNAL_ACTION) == 0)
    {
 #ifdef CONFIG_SMP
-#  ifdef CONFIG_ARMV8M_USEBASEPRI
      leave_critical_section((uint8_t)regs[REG_BASEPRI]);
-#  else
-      leave_critical_section((uint16_t)regs[REG_PRIMASK]);
-#  endif
 #endif
      goto retry;
    }
@ -169,11 +161,7 @@ retry:
  /* We need to keep the IRQ lock until task switching */

  rtcb->irqcount++;
-#ifdef CONFIG_ARMV8M_USEBASEPRI
  leave_critical_section((uint8_t)regs[REG_BASEPRI]);
-#else
-  leave_critical_section((uint16_t)regs[REG_PRIMASK]);
-#endif
  rtcb->irqcount--;
 #endif

--- a/arch/arm/src/armv8-m/arm_tcbinfo.c
+++ b/arch/arm/src/armv8-m/arm_tcbinfo.c
@ -57,13 +57,8 @@ static const uint16_t g_reg_offs[] =
 #if 0
  UINT16_MAX,                       /* msp */
  TCB_REG_OFF(REG_R13),
-#  ifdef CONFIG_ARMV8M_USEBASEPRI
  UINT16_MAX,                       /* primask */
  TCB_REG_OFF(REG_BASEPRI),
-#  else
-  TCB_REG_OFF(REG_PRIMASK),
-  UINT16_MAX,                       /* basepri */
-#  endif
  UINT16_MAX,                       /* faultmask */
  UINT16_MAX,                       /* control */

--- a/arch/arm/src/armv8-m/dwt.h
+++ b/arch/arm/src/armv8-m/dwt.h
@ -1,9 +1,11 @@
 /****************************************************************************
 * arch/arm/src/armv8-m/dwt.h
 *
- *   Copyright (c) 2009 - 2013 ARM LIMITED
+ * SPDX-License-Identifier: BSD-3-Clause
+ * SPDX-FileCopyrightText: 2014 Pierre-noel Bouteville. All rights reserved.
+ * SPDX-FileCopyrightText: 2009 - 2013 ARM LIMITED
+ * SPDX-FileContributor: Pierre-noel Bouteville <pnb990@gmail.com>
 *
- *  All rights reserved.
 *  Redistribution and use in source and binary forms, with or without
 *  modification, are permitted provided that the following conditions
 *  are met:
@ -29,9 +31,6 @@
 *  NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
 *  SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
- *   Copyright (C) 2014 Pierre-noel Bouteville . All rights reserved.
- *   Author: Pierre-noel Bouteville <pnb990@gmail.com>
- *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
--- a/arch/arm/src/armv8-m/etm.h
+++ b/arch/arm/src/armv8-m/etm.h
@ -1,7 +1,12 @@
 /****************************************************************************
 * arch/arm/src/armv8-m/etm.h
 *
- *  Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ * SPDX-License-Identifier: BSD-3-Clause
+ * SPDX-FileCopyrightText: 2014 Pierre-noel Bouteville. All rights reserved.
+ * SPDX-FileCopyrightText: 2014 Gregory Nutt. All rights reserved.
+ * SPDX-FileCopyrightText: 2014 Silicon Laboratories, Inc.
+ * SPDX-FileContributor: Pierre-noel Bouteville <pnb990@gmail.com>
+ * SPDX-FileContributor: Gregory Nutt <gnutt@nuttx.org>
 *
 * Permission is granted to anyone to use this software for any purpose,
 * including commercial applications, and to alter it and redistribute it
@ -24,11 +29,6 @@
 * incidental, or special damages, or any other relief, or for any claim by
 * any third party, arising from your use of this Software.
 *
- *   Copyright (C) 2014 Pierre-noel Bouteville . All rights reserved.
- *   Copyright (C) 2014 Gregory Nutt. All rights reserved.
- *   Authors: Pierre-noel Bouteville <pnb990@gmail.com>
- *            Gregory Nutt <gnutt@nuttx.org>
- *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
--- a/arch/arm/src/armv8-m/itm.h
+++ b/arch/arm/src/armv8-m/itm.h
@ -1,9 +1,11 @@
 /****************************************************************************
 * arch/arm/src/armv8-m/itm.h
 *
- *   Copyright (c) 2009 - 2013 ARM LIMITED
+ * SPDX-License-Identifier: BSD-3-Clause
+ * SPDX-FileCopyrightText: 2014 Pierre-noel Bouteville. All rights reserved.
+ * SPDX-FileCopyrightText: 2009 - 2013 ARM LIMITED
+ * SPDX-FileContributor: Pierre-noel Bouteville <pnb990@gmail.com>
 *
- *  All rights reserved.
 *  Redistribution and use in source and binary forms, with or without
 *  modification, are permitted provided that the following conditions
 *  are met:
@ -29,9 +31,6 @@
 *  NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
 *  SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
- *   Copyright (C) 2014 Pierre-noel Bouteville . All rights reserved.
- *   Author: Pierre-noel Bouteville <pnb990@gmail.com>
- *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
--- a/arch/arm/src/armv8-m/tpi.h
+++ b/arch/arm/src/armv8-m/tpi.h
@ -1,9 +1,11 @@
 /****************************************************************************
 * arch/arm/src/armv8-m/tpi.h
 *
- *   Copyright (c) 2009 - 2013 ARM LIMITED
+ * SPDX-License-Identifier: BSD-3-Clause
+ * SPDX-FileCopyrightText: 2014 Pierre-noel Bouteville. All rights reserved.
+ * SPDX-FileCopyrightText: 2009 - 2013 ARM LIMITED
+ * SPDX-FileContributor: Pierre-noel Bouteville <pnb990@gmail.com>
 *
- *  All rights reserved.
 *  Redistribution and use in source and binary forms, with or without
 *  modification, are permitted provided that the following conditions
 *  are met:
@ -29,9 +31,6 @@
 *  NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
 *  SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
- *   Copyright (C) 2014 Pierre-noel Bouteville . All rights reserved.
- *   Author: Pierre-noel Bouteville <pnb990@gmail.com>
- *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
--- a/arch/arm/src/at32/at32_gpio.h
+++ b/arch/arm/src/at32/at32_gpio.h
@ -50,7 +50,7 @@

 /* Bit-encoded input to at32_configgpio() */

-#if defined(CONFIG_AT32_AT32F43XX) 
+#if defined(CONFIG_AT32_AT32F43XX)
 /* Each port bit of the general-purpose I/O (GPIO) ports can be
 * individually configured by software in several modes:
 *
--- a/arch/arm/src/at32/at32_irq.c
+++ b/arch/arm/src/at32/at32_irq.c
@ -183,7 +183,6 @@ static int at32_reserved(int irq, void *context, void *arg)
 *
 ****************************************************************************/

-#ifdef CONFIG_ARMV7M_USEBASEPRI
 static inline void at32_prioritize_syscall(int priority)
 {
  uint32_t regval;
@ -195,7 +194,6 @@ static inline void at32_prioritize_syscall(int priority)
  regval |= (priority << NVIC_SYSH_PRIORITY_PR11_SHIFT);
  putreg32(regval, NVIC_SYSH8_11_PRIORITY);
 }
-#endif

 /****************************************************************************
 * Name: at32_irqinfo
@ -328,9 +326,8 @@ void up_irqinitialize(void)
 #ifdef CONFIG_ARCH_IRQPRIO
  /* up_prioritize_irq(AT32_IRQ_PENDSV, NVIC_SYSH_PRIORITY_MIN); */
 #endif
-#ifdef CONFIG_ARMV7M_USEBASEPRI
+
  at32_prioritize_syscall(NVIC_SYSH_SVCALL_PRIORITY);
-#endif

  /* If the MPU is enabled, then attach and enable the Memory Management
   * Fault handler.
--- a/arch/arm/src/at32/at32_serial.c
+++ b/arch/arm/src/at32/at32_serial.c
@ -196,6 +196,7 @@ struct up_dev_s
  struct uart_dev_s dev;       /* Generic UART device */
  uint16_t          ie;        /* Saved interrupt mask bits value */
  uint16_t          sr;        /* Saved status bits */
+  spinlock_t        lock;      /* Spinlock */

  /* Has been initialized and HW is setup. */

@ -1087,10 +1088,10 @@ static inline void up_serialout(struct up_dev_s *priv, int offset,
 }

 /****************************************************************************
- * Name: up_setusartint
+ * Name: up_setusartint_nolock
 ****************************************************************************/

-static inline void up_setusartint(struct up_dev_s *priv, uint16_t ie)
+static inline void up_setusartint_nolock(struct up_dev_s *priv, uint16_t ie)
 {
  uint32_t cr;

@ -1117,16 +1118,18 @@ static inline void up_setusartint(struct up_dev_s *priv, uint16_t ie)
 * Name: up_restoreusartint
 ****************************************************************************/

+#if defined(HAVE_RS485) || CONSOLE_UART > 0
 static void up_restoreusartint(struct up_dev_s *priv, uint16_t ie)
 {
  irqstate_t flags;

-  flags = spin_lock_irqsave(NULL);
+  flags = spin_lock_irqsave(&priv->lock);

-  up_setusartint(priv, ie);
+  up_setusartint_nolock(priv, ie);

-  spin_unlock_irqrestore(NULL, flags);
+  spin_unlock_irqrestore(&priv->lock, flags);
 }
+#endif

 /****************************************************************************
 * Name: up_disableusartint
@ -1136,7 +1139,7 @@ static void up_disableusartint(struct up_dev_s *priv, uint16_t *ie)
 {
  irqstate_t flags;

-  flags = spin_lock_irqsave(NULL);
+  flags = spin_lock_irqsave(&priv->lock);

  if (ie)
    {
@ -1175,9 +1178,9 @@ static void up_disableusartint(struct up_dev_s *priv, uint16_t *ie)

  /* Disable all interrupts */

-  up_setusartint(priv, 0);
+  up_setusartint_nolock(priv, 0);

-  spin_unlock_irqrestore(NULL, flags);
+  spin_unlock_irqrestore(&priv->lock, flags);
 }

 /****************************************************************************
@ -1490,6 +1493,8 @@ static int up_setup(struct uart_dev_s *dev)

  priv->ie    = 0;

+  spin_lock_init(&priv->lock);
+
  /* Mark device as initialized. */

  priv->initialized = true;
@ -2044,13 +2049,13 @@ static int up_ioctl(struct file *filep, int cmd, unsigned long arg)
        irqstate_t flags;
        uint32_t tx_break;

-        flags = enter_critical_section();
+        flags = spin_lock_irqsave(&priv->lock);

        /* Disable any further tx activity */

        priv->ie |= USART_CR1_IE_BREAK_INPROGRESS;

-        up_txint(dev, false);
+        up_txint_nolock(dev, false);

        /* Configure TX as a GPIO output pin and Send a break signal */

@ -2058,7 +2063,7 @@ static int up_ioctl(struct file *filep, int cmd, unsigned long arg)
                                  priv->tx_gpio);
        at32_configgpio(tx_break);

-        leave_critical_section(flags);
+        spin_unlock_irqrestore(&priv->lock, flags);
      }
      break;

@ -2066,7 +2071,7 @@ static int up_ioctl(struct file *filep, int cmd, unsigned long arg)
      {
        irqstate_t flags;

-        flags = enter_critical_section();
+        flags = spin_lock_irqsave(&priv->lock);

        /* Configure TX back to U(S)ART */

@ -2076,9 +2081,9 @@ static int up_ioctl(struct file *filep, int cmd, unsigned long arg)

        /* Enable further tx activity */

-        up_txint(dev, true);
+        up_txint_nolock(dev, true);

-        leave_critical_section(flags);
+        spin_unlock_irqrestore(&priv->lock, flags);
      }
      break;
 #  else
@ -2087,10 +2092,10 @@ static int up_ioctl(struct file *filep, int cmd, unsigned long arg)
        uint32_t cr1;
        irqstate_t flags;

-        flags = enter_critical_section();
+        flags = spin_lock_irqsave(&priv->lock);
        cr1   = up_serialin(priv, AT32_USART_CTRL1_OFFSET);
        up_serialout(priv, AT32_USART_CTRL1_OFFSET, cr1 | USART_CR1_SBK);
-        leave_critical_section(flags);
+        spin_unlock_irqrestore(&priv->lock, flags);
      }
      break;

@ -2099,10 +2104,10 @@ static int up_ioctl(struct file *filep, int cmd, unsigned long arg)
        uint32_t cr1;
        irqstate_t flags;

-        flags = enter_critical_section();
+        flags = spin_lock_irqsave(&priv->lock);
        cr1   = up_serialin(priv, AT32_USART_CTRL1_OFFSET);
        up_serialout(priv, AT32_USART_CTRL1_OFFSET, cr1 & ~USART_CR1_SBK);
-        leave_critical_section(flags);
+        spin_unlock_irqrestore(&priv->lock, flags);
      }
      break;
 #  endif
@ -2156,10 +2161,9 @@ static int up_receive(struct uart_dev_s *dev, unsigned int *status)
 ****************************************************************************/

 #if defined(SERIAL_HAVE_TXDMA_OPS) || defined(SERIAL_HAVE_NODMA_OPS)
-static void up_rxint(struct uart_dev_s *dev, bool enable)
+static void up_rxint_nolock(struct uart_dev_s *dev, bool enable)
 {
  struct up_dev_s *priv = (struct up_dev_s *)dev->priv;
-  irqstate_t flags;
  uint16_t ie;

  /* USART receive interrupts:
@ -2177,7 +2181,6 @@ static void up_rxint(struct uart_dev_s *dev, bool enable)
   * "           "        USART_STS_ROERR Overrun Error Detected
   */

-  flags = enter_critical_section();
  ie = priv->ie;
  if (enable)
    {
@ -2201,8 +2204,17 @@ static void up_rxint(struct uart_dev_s *dev, bool enable)

  /* Then set the new interrupt state */

-  up_restoreusartint(priv, ie);
-  leave_critical_section(flags);
+  up_setusartint_nolock(priv, ie);
+}
+
+static void up_rxint(struct uart_dev_s *dev, bool enable)
+{
+  struct up_dev_s *priv = (struct up_dev_s *)dev->priv;
+  irqstate_t flags;
+
+  flags = spin_lock_irqsave(&priv->lock);
+  up_rxint_nolock(dev, enable);
+  spin_unlock_irqrestore(&priv->lock, flags);
 }
 #endif

@ -2563,10 +2575,10 @@ static void up_dma_txint(struct uart_dev_s *dev, bool enable)

 #if defined(SERIAL_HAVE_RXDMA_OPS) || defined(SERIAL_HAVE_NODMA_OPS) || \
    defined(CONFIG_AT32_SERIALBRK_BSDCOMPAT)
-static void up_txint(struct uart_dev_s *dev, bool enable)
+
+static void up_txint_nolock(struct uart_dev_s *dev, bool enable)
 {
  struct up_dev_s *priv = (struct up_dev_s *)dev->priv;
-  irqstate_t flags;

  /* USART transmit interrupts:
   *
@ -2577,7 +2589,6 @@ static void up_txint(struct uart_dev_s *dev, bool enable)
   * USART_CTRL3_CTSCFIEN   USART_SR_CTS      CTS flag          (not used)
   */

-  flags = enter_critical_section();
  if (enable)
    {
      /* Set to receive an interrupt when the TX data register is empty */
@ -2599,12 +2610,11 @@ static void up_txint(struct uart_dev_s *dev, bool enable)
 #  ifdef CONFIG_AT32_SERIALBRK_BSDCOMPAT
      if (priv->ie & USART_CR1_IE_BREAK_INPROGRESS)
        {
-          leave_critical_section(flags);
          return;
        }
 #  endif

-      up_restoreusartint(priv, ie);
+      up_setusartint_nolock(priv, ie);

 #else
      /* Fake a TX interrupt here by just calling uart_xmitchars() with
@ -2618,11 +2628,20 @@ static void up_txint(struct uart_dev_s *dev, bool enable)
    {
      /* Disable the TX interrupt */

-      up_restoreusartint(priv, priv->ie & ~USART_CTRL1_TDBEIEN);
+      up_setusartint_nolock(priv, priv->ie & ~USART_CTRL1_TDBEIEN);
    }
-
-  leave_critical_section(flags);
 }
+
+static void up_txint(struct uart_dev_s *dev, bool enable)
+{
+  struct up_dev_s *priv = (struct up_dev_s *)dev->priv;
+  irqstate_t flags;
+
+  flags = spin_lock_irqsave(&priv->lock);
+  up_txint_nolock(dev, enable);
+  spin_unlock_irqrestore(&priv->lock, flags);
+}
+
 #endif

 /****************************************************************************
@ -2929,7 +2948,7 @@ void at32_serial_dma_poll(void)
 {
    irqstate_t flags;

-    flags = enter_critical_section();
+    flags = spin_lock_irqsave(&priv->lock);

 #ifdef CONFIG_USART1_RXDMA
  if (g_usart1priv.rxdma != NULL)
@ -2987,7 +3006,7 @@ void at32_serial_dma_poll(void)
    }
 #endif

-  leave_critical_section(flags);
+  spin_unlock_irqrestore(&priv->lock, flags);
 }
 #endif

--- a/arch/arm/src/at32/at32_tim.c
+++ b/arch/arm/src/at32/at32_tim.c
@ -263,7 +263,7 @@
    defined(CONFIG_AT32_TIM9)  || defined(CONFIG_AT32_TIM10) || \
    defined(CONFIG_AT32_TIM11) || defined(CONFIG_AT32_TIM12) || \
    defined(CONFIG_AT32_TIM13) || defined(CONFIG_AT32_TIM14) || \
-    defined(CONFIG_AT32_TIM20) 
+    defined(CONFIG_AT32_TIM20)

 /****************************************************************************
 * Private Types
--- a/arch/arm/src/at32/at32_uid.c
+++ b/arch/arm/src/at32/at32_uid.c
@ -29,7 +29,7 @@
 #include "hardware/at32_memorymap.h"
 #include "at32_uid.h"

-#ifdef AT32_SYSMEM_UID 
+#ifdef AT32_SYSMEM_UID

 /****************************************************************************
 * Public Functions
--- a/arch/arm/src/at32/hardware/at32_adc_v1.h
+++ b/arch/arm/src/at32/hardware/at32_adc_v1.h
@ -612,7 +612,7 @@

 /* Calibration value register */

-#define ADC_CALVAL_SHIFT             (0) 
+#define ADC_CALVAL_SHIFT             (0)
 #define ADC_CALVAL_MASK              (0x7f << ADC_CALVAL_SHIFT)
 #  define ADC_CALVAL(n)              (n << ADC_CALVAL_SHIFT)

--- a/arch/arm/src/at32/hardware/at32_can.h
+++ b/arch/arm/src/at32/hardware/at32_can.h
@ -307,7 +307,7 @@
 #define CAN_ESTS_BOF                        (1 << 0) /* Bus-off flag */

 #define CAN_ESTS_ETR_SHIFT                  (4)                       /* Error type record */
-#define CAN_ESTS_ETR_MASK                   (7 << CAN_ESTS_ETR_SHIFT) 
+#define CAN_ESTS_ETR_MASK                   (7 << CAN_ESTS_ETR_SHIFT)
 #define CAN_ESTS_ETR_NONE                   (0 << CAN_ESTS_ETR_SHIFT) /* No error */
 #define CAN_ESTS_ETR_STUFF                  (1 << CAN_ESTS_ETR_SHIFT) /* Stuff error */
 #define CAN_ESTS_ETR_FORM                   (2 << CAN_ESTS_ETR_SHIFT) /* Form error */
@ -318,7 +318,7 @@
 #define CAN_ESTS_ETR_SOFT                   (7 << CAN_ESTS_ETR_SHIFT) /* Set by soft */

 #define CAN_ESTS_TEC_SHIFT                  (16) /* Transmit error counter */
-#define CAN_ESTS_TEC_MASK                   (0xff << CAN_ESTS_TEC_SHIFT) 
+#define CAN_ESTS_TEC_MASK                   (0xff << CAN_ESTS_TEC_SHIFT)

 #define CAN_ESTS_REC_SHIFT                  (24) /* Receive error counter */
 #define CAN_ESTS_REC_MASK                   (0xff << CAN_ESTS_REC_SHIFT)
--- a/arch/arm/src/at32/hardware/at32f43xxx_rcc.h
+++ b/arch/arm/src/at32/hardware/at32f43xxx_rcc.h
@ -97,11 +97,11 @@
 /* PLL configuration register */

 #define CRM_PLL_CFG_PLL_MS_SHIFT        (0) /* PLL pre-division, range: 1~15 */
-#define CRM_PLL_CFG_PLL_MS_MASK         (15 << CRM_PLL_CFG_PLL_MS_SHIFT) 
+#define CRM_PLL_CFG_PLL_MS_MASK         (15 << CRM_PLL_CFG_PLL_MS_SHIFT)
 #  define CRM_PLL_CFG_PLL_MS(n)         ((n) << CRM_PLL_CFG_PLL_MS_SHIFT) /* n = 1..15 */

 #define CRM_PLL_CFG_PLL_NS_SHIFT        (6) /* PLL Multiplication Factor,range: 31~500 */
-#define CRM_PLL_CFG_PLL_NS_MASK         (0x1FF << CRM_PLL_CFG_PLL_NS_SHIFT) 
+#define CRM_PLL_CFG_PLL_NS_MASK         (0x1FF << CRM_PLL_CFG_PLL_NS_SHIFT)
 #  define CRM_PLL_CFG_PLL_NS(n)         ((n) << CRM_PLL_CFG_PLL_NS_SHIFT) /* n = 31..500 */

 #define CRM_PLL_CFG_PLL_FR_SHIFT        (16) /* PLL post-division */
@ -510,7 +510,7 @@
 #define CRM_MISC1_HICK_TO_SCLK              (1 << 14) /* HICK as system clock frequency select */

 #define CRM_MISC1_CLKOUT2_SEL2_SHIFT        (16) /* Clock output2 sel2 */
-#define CRM_MISC1_CLKOUT2_SEL2_MASK         (15 << CRM_MISC1_CLKOUT2_SEL2_SHIFT) 
+#define CRM_MISC1_CLKOUT2_SEL2_MASK         (15 << CRM_MISC1_CLKOUT2_SEL2_SHIFT)
 #  define CRM_MISC1_CLKOUT2_SEL2_USB        (0 << CRM_MISC1_CLKOUT2_SEL2_SHIFT) /* Select USB output */
 #  define CRM_MISC1_CLKOUT2_SEL2_ADC        (1 << CRM_MISC1_CLKOUT2_SEL2_SHIFT) /* Select ADC output */
 #  define CRM_MISC1_CLKOUT2_SEL2_HICK       (2 << CRM_MISC1_CLKOUT2_SEL2_SHIFT) /* Select HICK output */
--- a/arch/arm/src/at32/hardware/at32f43xxx_syscfg.h
+++ b/arch/arm/src/at32/hardware/at32f43xxx_syscfg.h
@ -71,13 +71,13 @@
 #define SCFG_CFG1_IR_POL                    (1 << 5) /* Infrared output polarity selection */

 #define SCFG_CFG1_IR_SRC_SEL_SHIFT          (6) /* Infrared modulation envelope signal source selection */
-#define SCFG_CFG1_IR_SRC_SEL_MASK           (3 << SCFG_CFG1_IR_SRC_SEL_SHIFT) 
+#define SCFG_CFG1_IR_SRC_SEL_MASK           (3 << SCFG_CFG1_IR_SRC_SEL_SHIFT)
 #  define SCFG_CFG1_IR_SRC_SEL_TMR10        (0 << SCFG_CFG1_IR_SRC_SEL_SHIFT) /* Source use TRM10 */
 #  define SCFG_CFG1_IR_SRC_SEL_USART1       (1 << SCFG_CFG1_IR_SRC_SEL_SHIFT) /* Source use USART1 */
 #  define SCFG_CFG1_IR_SRC_SEL_USART2       (2 << SCFG_CFG1_IR_SRC_SEL_SHIFT) /* Source use USART2 */

 #define SCFG_CFG1_SWAP_XMC_SHIFT            (6) /* Infrared modulation envelope signal source selection */
-#define SCFG_CFG1_SWAP_XMC_MASK             (3 << SCFG_CFG1_SWAP_XMC_SHIFT) 
+#define SCFG_CFG1_SWAP_XMC_MASK             (3 << SCFG_CFG1_SWAP_XMC_SHIFT)
 #  define SCFG_CFG1_SWAP_XMC_NONE           (0 << SCFG_CFG1_SWAP_XMC_SHIFT) /* No swap */
 #  define SCFG_CFG1_SWAP_XMC_SDRAM1         (1 << SCFG_CFG1_SWAP_XMC_SHIFT) /* SDRAM swap1 */
 #  define SCFG_CFG1_SWAP_XMC_QSPI2          (2 << SCFG_CFG1_SWAP_XMC_SHIFT) /* QSPI2 swap */
--- a/arch/arm/src/at32/hardware/at32f43xxx_uart.h
+++ b/arch/arm/src/at32/hardware/at32f43xxx_uart.h
@ -176,7 +176,7 @@
 #define USART_CTRL1_TCDT_MASK               (31 << USART_CTRL1_TCDT_SHIFT)
 #define USART_CTRL1_TCDT(X)                 ((X) << USART_CTRL1_TCDT_SHIFT)
 #define USART_CTRL1_TSDT_SHIFT              (21) /* transmit start delay time */
-#define USART_CTRL1_TSDT_MASK               (31 << USART_CTRL1_TSDT_SHIFT) 
+#define USART_CTRL1_TSDT_MASK               (31 << USART_CTRL1_TSDT_SHIFT)
 #define USART_CTRL1_TSDT(X)                 ((X) << USART_CTRL1_TSDT_SHIFT)
 #define USART_CTRL1_DBN1                    (1 << 28) /* Data bit num */

--- a/arch/arm/src/common/arm_exit.c
+++ b/arch/arm/src/common/arm_exit.c
@ -60,9 +60,18 @@ void up_exit(int status)

  nxtask_exit();

-  /* Scheduler parameters will update inside syscall */
+  /* Update g_running_tasks */

+#ifdef CONFIG_ARCH_ARMV6M
+  /* ARMV6M syscal may trigger hard fault， We use
+   * running_task != NULL to determine whether it is
+   * a context for restoration.
+   */
+
+  g_running_tasks[this_cpu()] = NULL;
+#else
  g_running_tasks[this_cpu()] = this_task();
+#endif

  /* Then switch contexts */

--- a/arch/arm/src/common/arm_modifyreg16.c
+++ b/arch/arm/src/common/arm_modifyreg16.c
@ -33,6 +33,12 @@

 #include "arm_internal.h"

+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+static spinlock_t g_modifyreg_lock = SP_UNLOCKED;
+
 /****************************************************************************
 * Public Functions
 ****************************************************************************/
@ -50,10 +56,10 @@ void modifyreg16(unsigned int addr, uint16_t clearbits, uint16_t setbits)
  irqstate_t flags;
  uint16_t   regval;

-  flags   = spin_lock_irqsave(NULL);
+  flags   = spin_lock_irqsave(&g_modifyreg_lock);
  regval  = getreg16(addr);
  regval &= ~clearbits;
  regval |= setbits;
  putreg16(regval, addr);
-  spin_unlock_irqrestore(NULL, flags);
+  spin_unlock_irqrestore(&g_modifyreg_lock, flags);
 }
--- a/arch/arm/src/csk6/csk6_irq.c
+++ b/arch/arm/src/csk6/csk6_irq.c
@ -87,7 +87,6 @@ static int csk6_reserved(int irq, void *context, void *arg)
 *
 ****************************************************************************/

-#ifdef CONFIG_ARMV8M_USEBASEPRI
 static inline void csk6_prioritize_syscall(int priority)
 {
  uint32_t regval;
@ -99,7 +98,6 @@ static inline void csk6_prioritize_syscall(int priority)
  regval |= (priority << NVIC_SYSH_PRIORITY_PR11_SHIFT);
  putreg32(regval, NVIC_SYSH8_11_PRIORITY);
 }
-#endif

 /****************************************************************************
 * Public Functions
@ -180,9 +178,7 @@ void up_irqinitialize(void)
  /* up_prioritize_irq(CSK6_IRQ_PENDSV, NVIC_SYSH_PRIORITY_MIN); */

 #endif
-#ifdef CONFIG_ARMV8M_USEBASEPRI
  csk6_prioritize_syscall(NVIC_SYSH_SVCALL_PRIORITY);
-#endif

  /* If the MPU is enabled, then attach and enable the Memory Management
   * Fault handler.
--- a/arch/arm/src/cxd32xx/cxd32_irq.c
+++ b/arch/arm/src/cxd32xx/cxd32_irq.c
@ -53,6 +53,12 @@

 #define INTC_EN(n) (CXD32_INTC_BASE + 0x10 + (((n) >> 5) << 2))

+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+static spinlock_t g_cxd32_lock = SP_UNLOCKED;
+
 /****************************************************************************
 * Public Data
 ****************************************************************************/
@ -74,7 +80,7 @@ static void cxd32_dumpnvic(const char *msg, int irq)
 {
  irqstate_t flags;

-  flags = enter_critical_section();
+  flags = spin_lock_irqsave(&g_cxd32_lock);
  irqinfo("NVIC (%s, irq=%d):\n", msg, irq);
  irqinfo("  INTCTRL:    %08x VECTAB: %08x\n", getreg32(NVIC_INTCTRL),
          getreg32(NVIC_VECTAB));
@ -103,7 +109,7 @@ static void cxd32_dumpnvic(const char *msg, int irq)
          getreg32(NVIC_IRQ48_51_PRIORITY),
          getreg32(NVIC_IRQ52_55_PRIORITY),
          getreg32(NVIC_IRQ56_59_PRIORITY));
-  leave_critical_section(flags);
+  spin_unlock_irqrestore(&g_cxd32_lock, flags);
 }
 #else
 #  define cxd32_dumpnvic(msg, irq)
@ -154,7 +160,6 @@ static int cxd32_reserved(int irq, void *context, void *arg)
 *
 ****************************************************************************/

-#ifdef CONFIG_ARMV7M_USEBASEPRI
 static inline void cxd32_prioritize_syscall(int priority)
 {
  uint32_t regval;
@ -166,7 +171,6 @@ static inline void cxd32_prioritize_syscall(int priority)
  regval |= (priority << NVIC_SYSH_PRIORITY_PR11_SHIFT);
  putreg32(regval, NVIC_SYSH8_11_PRIORITY);
 }
-#endif

 static int excinfo(int irq, uintptr_t *regaddr, uint32_t *bit)
 {
@ -282,9 +286,7 @@ void up_irqinitialize(void)

 #endif

-#ifdef CONFIG_ARMV7M_USEBASEPRI
  cxd32_prioritize_syscall(NVIC_SYSH_SVCALL_PRIORITY);
-#endif

  /* If the MPU is enabled, then attach and enable the Memory Management
   * Fault handler.
@ -312,21 +314,6 @@ void up_irqinitialize(void)

  cxd32_dumpnvic("initial", CXD32_IRQ_NIRQS);

-  /* If a debugger is connected, try to prevent it from catching hardfaults.
-   * If CONFIG_ARMV7M_USEBASEPRI, no hardfaults are expected in normal
-   * operation.
-   */
-
-#if defined(CONFIG_DEBUG_FEATURES) && !defined(CONFIG_ARMV7M_USEBASEPRI)
-    {
-      uint32_t regval;
-
-      regval  = getreg32(NVIC_DEMCR);
-      regval &= ~NVIC_DEMCR_VCHARDERR;
-      putreg32(regval, NVIC_DEMCR);
-    }
-#endif
-
  /* And finally, enable interrupts */

 #ifndef CONFIG_SUPPRESS_INTERRUPTS
@ -350,14 +337,14 @@ void up_disable_irq(int irq)

  if (irq >= CXD32_IRQ_EXTINT)
    {
-      irqstate_t flags = spin_lock_irqsave(NULL);
+      irqstate_t flags = spin_lock_irqsave(&g_cxd32_lock);
      irq -= CXD32_IRQ_EXTINT;
      bit  = 1 << (irq & 0x1f);

      regval  = getreg32(INTC_EN(irq));
      regval &= ~bit;
      putreg32(regval, INTC_EN(irq));
-      spin_unlock_irqrestore(NULL, flags);
+      spin_unlock_irqrestore(&g_cxd32_lock, flags);
      putreg32(bit, NVIC_IRQ_CLEAR(irq));
    }
  else
@ -389,14 +376,14 @@ void up_enable_irq(int irq)

  if (irq >= CXD32_IRQ_EXTINT)
    {
-      irqstate_t flags = spin_lock_irqsave(NULL);
+      irqstate_t flags = spin_lock_irqsave(&g_cxd32_lock);
      irq -= CXD32_IRQ_EXTINT;
      bit  = 1 << (irq & 0x1f);

      regval  = getreg32(INTC_EN(irq));
      regval |= bit;
      putreg32(regval, INTC_EN(irq));
-      spin_unlock_irqrestore(NULL, flags);
+      spin_unlock_irqrestore(&g_cxd32_lock, flags);
      putreg32(bit, NVIC_IRQ_ENABLE(irq));
    }
  else
--- a/arch/arm/src/cxd32xx/cxd32_uart.c
+++ b/arch/arm/src/cxd32xx/cxd32_uart.c
@ -112,6 +112,8 @@ struct uartdev
 * Private Data
 ****************************************************************************/

+static spinlock_t g_cxd32xx_lock = SP_UNLOCKED;
+
 static const struct uartdev g_uartdevs[] =
 {
  {
@ -270,7 +272,7 @@ void cxd32_setbaud(uintptr_t uartbase, uint32_t basefreq, uint32_t baud)
  uint32_t fbrd;
  uint32_t lcr_h;

-  irqstate_t flags = spin_lock_irqsave(NULL);
+  irqstate_t flags = spin_lock_irqsave(&g_cxd32xx_lock);

  div  = (uint64_t)(basefreq);
  div *= (uint64_t)(256);
@ -287,5 +289,5 @@ void cxd32_setbaud(uintptr_t uartbase, uint32_t basefreq, uint32_t baud)
  lcr_h = getreg32(uartbase + CXD32_UART_LCR_H);
  putreg32(lcr_h, uartbase + CXD32_UART_LCR_H);

-  spin_unlock_irqrestore(NULL, flags);
+  spin_unlock_irqrestore(&g_cxd32xx_lock, flags);
 }
--- a/arch/arm/src/cxd56xx/cxd56_gpioint.c
+++ b/arch/arm/src/cxd56xx/cxd56_gpioint.c
@ -95,6 +95,8 @@
 * Private Data
 ****************************************************************************/

+static spinlock_t g_cxd56_lock = SP_UNLOCKED;
+
 static xcpt_t g_isr[MAX_SLOT];
 static uint32_t g_bothedge = 0;

@ -114,7 +116,7 @@ static int alloc_slot(int pin, bool isalloc)
                                     : CXD56_TOPREG_IOCAPP_INTSEL0;
  int offset = (pin < PIN_IS_CLK) ? 1 : 56;

-  flags = spin_lock_irqsave(NULL);
+  flags = spin_lock_irqsave(&g_cxd56_lock);

  for (slot = 0; slot < MAX_SYS_SLOT; slot++)
    {
@ -144,12 +146,12 @@ static int alloc_slot(int pin, bool isalloc)
        }
      else
        {
-          spin_unlock_irqrestore(NULL, flags);
+          spin_unlock_irqrestore(&g_cxd56_lock, flags);
          return -ENXIO; /* no space */
        }
    }

-  spin_unlock_irqrestore(NULL, flags);
+  spin_unlock_irqrestore(&g_cxd56_lock, flags);

  if (PIN_IS_CLK <= pin)
    {
@ -309,13 +311,13 @@ static void invert_irq(int irq)
  irqstate_t flags;
  uint32_t val;

-  flags = spin_lock_irqsave(NULL);
+  flags = spin_lock_irqsave(&g_cxd56_lock);

  val = getreg32(CXD56_INTC_INVERT);
  val ^= (1 << (irq - CXD56_IRQ_EXTINT));
  putreg32(val, CXD56_INTC_INVERT);

-  spin_unlock_irqrestore(NULL, flags);
+  spin_unlock_irqrestore(&g_cxd56_lock, flags);
 }

 static bool inverted_irq(int irq)
@ -431,9 +433,9 @@ int cxd56_gpioint_config(uint32_t pin, uint32_t gpiocfg, xcpt_t isr,
      irq_attach(irq, NULL, NULL);
      g_isr[slot] = NULL;

-      flags = spin_lock_irqsave(NULL);
+      flags = spin_lock_irqsave(&g_cxd56_lock);
      g_bothedge &= ~(1 << slot);
-      spin_unlock_irqrestore(NULL, flags);
+      spin_unlock_irqrestore(&g_cxd56_lock, flags);
      return irq;
    }

@ -447,9 +449,9 @@ int cxd56_gpioint_config(uint32_t pin, uint32_t gpiocfg, xcpt_t isr,
    {
      /* set GPIO pseudo both edge interrupt */

-      flags = spin_lock_irqsave(NULL);
+      flags = spin_lock_irqsave(&g_cxd56_lock);
      g_bothedge |= (1 << slot);
-      spin_unlock_irqrestore(NULL, flags);
+      spin_unlock_irqrestore(&g_cxd56_lock, flags);

      /* detect the change from the current signal */

--- a/arch/arm/src/cxd56xx/cxd56_i2c.c
+++ b/arch/arm/src/cxd56xx/cxd56_i2c.c
@ -667,6 +667,7 @@ static int cxd56_i2c_transfer(struct i2c_master_s *dev,
      if (priv->error != OK)
        {
          ret = priv->error;
+          wostop = 0;
          break;
        }

--- a/arch/arm/src/cxd56xx/cxd56_irq.c
+++ b/arch/arm/src/cxd56xx/cxd56_irq.c
@ -100,6 +100,12 @@ const uint32_t g_cpu_intstack_top[CONFIG_SMP_NCPUS] =
 };
 #endif /* defined(CONFIG_SMP) && CONFIG_ARCH_INTERRUPTSTACK > 7 */

+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+static spinlock_t g_cxd56_lock = SP_UNLOCKED;
+
 /****************************************************************************
 * Private Functions
 ****************************************************************************/
@ -117,7 +123,7 @@ static void cxd56_dumpnvic(const char *msg, int irq)
 {
  irqstate_t flags;

-  flags = enter_critical_section();
+  flags = spin_lock_irqsave(&g_cxd56_lock);
  irqinfo("NVIC (%s, irq=%d):\n", msg, irq);
  irqinfo("  INTCTRL:    %08x VECTAB: %08x\n", getreg32(NVIC_INTCTRL),
          getreg32(NVIC_VECTAB));
@ -146,7 +152,7 @@ static void cxd56_dumpnvic(const char *msg, int irq)
          getreg32(NVIC_IRQ48_51_PRIORITY),
          getreg32(NVIC_IRQ52_55_PRIORITY),
          getreg32(NVIC_IRQ56_59_PRIORITY));
-  leave_critical_section(flags);
+  spin_unlock_irqrestore(&g_cxd56_lock, flags);
 }
 #else
 #  define cxd56_dumpnvic(msg, irq)
@ -197,7 +203,6 @@ static int cxd56_reserved(int irq, void *context, void *arg)
 *
 ****************************************************************************/

-#ifdef CONFIG_ARMV7M_USEBASEPRI
 static inline void cxd56_prioritize_syscall(int priority)
 {
  uint32_t regval;
@ -209,7 +214,6 @@ static inline void cxd56_prioritize_syscall(int priority)
  regval |= (priority << NVIC_SYSH_PRIORITY_PR11_SHIFT);
  putreg32(regval, NVIC_SYSH8_11_PRIORITY);
 }
-#endif

 static int excinfo(int irq, uintptr_t *regaddr, uint32_t *bit)
 {
@ -333,9 +337,7 @@ void up_irqinitialize(void)

 #endif

-#ifdef CONFIG_ARMV7M_USEBASEPRI
  cxd56_prioritize_syscall(NVIC_SYSH_SVCALL_PRIORITY);
-#endif

  /* If the MPU is enabled, then attach and enable the Memory Management
   * Fault handler.
@ -363,21 +365,6 @@ void up_irqinitialize(void)

  cxd56_dumpnvic("initial", CXD56_IRQ_NIRQS);

-  /* If a debugger is connected, try to prevent it from catching hardfaults.
-   * If CONFIG_ARMV7M_USEBASEPRI, no hardfaults are expected in normal
-   * operation.
-   */
-
-#if defined(CONFIG_DEBUG_FEATURES) && !defined(CONFIG_ARMV7M_USEBASEPRI)
-    {
-      uint32_t regval;
-
-      regval  = getreg32(NVIC_DEMCR);
-      regval &= ~NVIC_DEMCR_VCHARDERR;
-      putreg32(regval, NVIC_DEMCR);
-    }
-#endif
-
  /* And finally, enable interrupts */

 #ifndef CONFIG_SUPPRESS_INTERRUPTS
@ -424,14 +411,14 @@ void up_disable_irq(int irq)
      g_cpu_for_irq[irq] = -1;
 #endif

-      irqstate_t flags = spin_lock_irqsave(NULL);
+      irqstate_t flags = spin_lock_irqsave(&g_cxd56_lock);
      irq -= CXD56_IRQ_EXTINT;
      bit  = 1 << (irq & 0x1f);

      regval  = getreg32(INTC_EN(irq));
      regval &= ~bit;
      putreg32(regval, INTC_EN(irq));
-      spin_unlock_irqrestore(NULL, flags);
+      spin_unlock_irqrestore(&g_cxd56_lock, flags);
      putreg32(bit, NVIC_IRQ_CLEAR(irq));
    }
  else
@ -479,14 +466,14 @@ void up_enable_irq(int irq)
        }
 #endif

-      irqstate_t flags = spin_lock_irqsave(NULL);
+      irqstate_t flags = spin_lock_irqsave(&g_cxd56_lock);
      irq -= CXD56_IRQ_EXTINT;
      bit  = 1 << (irq & 0x1f);

      regval  = getreg32(INTC_EN(irq));
      regval |= bit;
      putreg32(regval, INTC_EN(irq));
-      spin_unlock_irqrestore(NULL, flags);
+      spin_unlock_irqrestore(&g_cxd56_lock, flags);
      putreg32(bit, NVIC_IRQ_ENABLE(irq));
    }
  else
--- a/arch/arm/src/cxd56xx/cxd56_rtc.c
+++ b/arch/arm/src/cxd56xx/cxd56_rtc.c
@ -113,6 +113,8 @@ struct rtc_backup_s
 * Private Data
 ****************************************************************************/

+static spinlock_t g_rtc_lock = SP_UNLOCKED;
+
 /* Callback to use when the alarm expires */

 #ifdef CONFIG_RTC_ALARM
@ -434,7 +436,7 @@ int up_rtc_settime(const struct timespec *tp)
  irqstate_t flags;
  uint64_t count;

-  flags = spin_lock_irqsave(NULL);
+  flags = spin_lock_irqsave(&g_rtc_lock);

 #ifdef RTC_DIRECT_CONTROL
  /* wait until previous write request is completed */
@ -457,7 +459,7 @@ int up_rtc_settime(const struct timespec *tp)
  g_rtc_save->offset = (int64_t)count - (int64_t)cxd56_rtc_count();
 #endif

-  spin_unlock_irqrestore(NULL, flags);
+  spin_unlock_irqrestore(&g_rtc_lock, flags);

  rtc_dumptime(tp, "Setting time");

@ -485,12 +487,12 @@ uint64_t cxd56_rtc_count(void)
   * 1st post -> 2nd pre, and should be operated in atomic.
   */

-  flags = spin_lock_irqsave(NULL);
+  flags = spin_lock_irqsave(&g_rtc_lock);

  val = (uint64_t)getreg32(CXD56_RTC0_RTPOSTCNT) << 15;
  val |= getreg32(CXD56_RTC0_RTPRECNT);

-  spin_unlock_irqrestore(NULL, flags);
+  spin_unlock_irqrestore(&g_rtc_lock, flags);

  return val;
 }
@ -512,12 +514,12 @@ uint64_t cxd56_rtc_almcount(void)
  uint64_t val;
  irqstate_t flags;

-  flags = spin_lock_irqsave(NULL);
+  flags = spin_lock_irqsave(&g_rtc_lock);

  val = (uint64_t)getreg32(CXD56_RTC0_SETALMPOSTCNT(0)) << 15;
  val |= (getreg32(CXD56_RTC0_SETALMPRECNT(0)) & 0x7fff);

-  spin_unlock_irqrestore(NULL, flags);
+  spin_unlock_irqrestore(&g_rtc_lock, flags);

  return val;
 }
@ -559,7 +561,7 @@ int cxd56_rtc_setalarm(struct alm_setalarm_s *alminfo)
    {
      /* The set the alarm */

-      flags = spin_lock_irqsave(NULL);
+      flags = spin_lock_irqsave(&g_rtc_lock);

      cbinfo->ac_cb  = alminfo->as_cb;
      cbinfo->ac_arg = alminfo->as_arg;
@ -590,7 +592,7 @@ int cxd56_rtc_setalarm(struct alm_setalarm_s *alminfo)

      while (RTCREG_ALM_BUSY_MASK & getreg32(CXD56_RTC0_ALMOUTEN(id)));

-      spin_unlock_irqrestore(NULL, flags);
+      spin_unlock_irqrestore(&g_rtc_lock, flags);

      rtc_dumptime(&alminfo->as_time, "New Alarm time");
      ret = OK;
@ -632,7 +634,7 @@ int cxd56_rtc_cancelalarm(enum alm_id_e alarmid)
    {
      /* Unset the alarm */

-      flags = spin_lock_irqsave(NULL);
+      flags = spin_lock_irqsave(&g_rtc_lock);

      cbinfo->ac_cb = NULL;

@ -665,7 +667,7 @@ int cxd56_rtc_cancelalarm(enum alm_id_e alarmid)
          putreg32(mask, CXD56_RTC0_ALMCLR);
        }

-      spin_unlock_irqrestore(NULL, flags);
+      spin_unlock_irqrestore(&g_rtc_lock, flags);

      ret = OK;
    }
--- a/arch/arm/src/cxd56xx/cxd56_uart.c
+++ b/arch/arm/src/cxd56xx/cxd56_uart.c
@ -129,6 +129,8 @@ struct uartdev
 * Private Data
 ****************************************************************************/

+static spinlock_t g_cxd32xx_lock = SP_UNLOCKED;
+
 static struct uartdev g_uartdevs[] =
 {
  {
@ -206,7 +208,7 @@ static void cxd56_uart_pincontrol(int ch, bool on)

 static void cxd56_uart_start(int ch)
 {
-  irqstate_t flags = enter_critical_section();
+  irqstate_t flags = spin_lock_irqsave(&g_cxd32xx_lock);

  cxd56_setbaud(CONSOLE_BASE, CONSOLE_BASEFREQ, CONSOLE_BAUD);

@ -214,7 +216,7 @@ static void cxd56_uart_start(int ch)

  putreg32(g_cr, g_uartdevs[ch].uartbase + CXD56_UART_CR);

-  leave_critical_section(flags);
+  spin_unlock_irqrestore(&g_cxd32xx_lock, flags);
 }

 /****************************************************************************
@ -230,7 +232,7 @@ static void cxd56_uart_stop(int ch)
 {
  uint32_t cr;

-  irqstate_t flags = enter_critical_section();
+  irqstate_t flags = spin_lock_irqsave(&g_cxd32xx_lock);

  while (UART_FR_BUSY & getreg32(g_uartdevs[ch].uartbase + CXD56_UART_FR));

@ -242,7 +244,7 @@ static void cxd56_uart_stop(int ch)
  g_lcr = getreg32(g_uartdevs[ch].uartbase + CXD56_UART_LCR_H);
  putreg32(0, g_uartdevs[ch].uartbase + CXD56_UART_LCR_H);

-  leave_critical_section(flags);
+  spin_unlock_irqrestore(&g_cxd32xx_lock, flags);
 }

 /****************************************************************************
@ -463,7 +465,7 @@ void cxd56_setbaud(uintptr_t uartbase, uint32_t basefreq, uint32_t baud)
  uint32_t div;
  uint32_t lcr_h;

-  irqstate_t flags = spin_lock_irqsave(NULL);
+  irqstate_t flags = spin_lock_irqsave(&g_cxd32xx_lock);

  if (uartbase == CXD56_UART2_BASE)
    {
@ -475,7 +477,7 @@ void cxd56_setbaud(uintptr_t uartbase, uint32_t basefreq, uint32_t baud)
    }
  else
    {
-      spin_unlock_irqrestore(NULL, flags);
+      spin_unlock_irqrestore(&g_cxd32xx_lock, flags);
      return;
    }

@ -502,7 +504,7 @@ void cxd56_setbaud(uintptr_t uartbase, uint32_t basefreq, uint32_t baud)
  putreg32(lcr_h, uartbase + CXD56_UART_LCR_H);

 finish:
-  spin_unlock_irqrestore(NULL, flags);
+  spin_unlock_irqrestore(&g_cxd32xx_lock, flags);
 }

 /****************************************************************************
--- a/arch/arm/src/efm32/efm32_flash.c
+++ b/arch/arm/src/efm32/efm32_flash.c
@ -1,7 +1,10 @@
 /****************************************************************************
 * arch/arm/src/efm32/efm32_flash.c
 *
- *  Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com
+ * SPDX-License-Identifier: BSD-3-Clause
+ * SPDX-FileCopyrightText: 2014 Silicon Laboratories, Inc.
+ * SPDX-FileCopyrightText: 2015 Pierre-Noel Bouteville.
+ * SPDX-FileContributor: Pierre-Noel Bouteville <pnb990@gmail.com>
 *
 * Permission is granted to anyone to use this software for any purpose,
 * including commercial applications, and to alter it and redistribute it
@ -24,9 +27,6 @@
 * incidental, or special damages, or any other relief, or for any claim by
 * any third party, arising from your use of this Software.
 *
- *   Copyright (C) 2015 Pierre-Noel Bouteville. All rights reserved.
- *   Author: Pierre-Noel Bouteville <pnb990@gmail.com>
- *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
--- a/arch/arm/src/efm32/efm32_irq.c
+++ b/arch/arm/src/efm32/efm32_irq.c
@ -178,7 +178,6 @@ static int efm32_reserved(int irq, void *context, void *arg)
 *
 ****************************************************************************/

-#ifdef CONFIG_ARMV7M_USEBASEPRI
 static inline void efm32_prioritize_syscall(int priority)
 {
  uint32_t regval;
@ -190,7 +189,6 @@ static inline void efm32_prioritize_syscall(int priority)
  regval |= (priority << NVIC_SYSH_PRIORITY_PR11_SHIFT);
  putreg32(regval, NVIC_SYSH8_11_PRIORITY);
 }
-#endif

 /****************************************************************************
 * Name: efm32_irqinfo
@ -328,11 +326,9 @@ void up_irqinitialize(void)
  irq_attach(EFM32_IRQ_SVCALL, arm_svcall, NULL);
  irq_attach(EFM32_IRQ_HARDFAULT, arm_hardfault, NULL);

-#ifdef CONFIG_ARMV7M_USEBASEPRI
  /* Set the priority of the SVCall interrupt */

  efm32_prioritize_syscall(NVIC_SYSH_SVCALL_PRIORITY);
-#endif

  /* If the MPU is enabled, then attach and enable the Memory Management
   * Fault handler.
--- a/arch/arm/src/efm32/hardware/efm32_acmp.h
+++ b/arch/arm/src/efm32/hardware/efm32_acmp.h
@ -1,7 +1,12 @@
 /****************************************************************************
 * arch/arm/src/efm32/hardware/efm32_acmp.h
 *
- *  Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ * SPDX-License-Identifier: BSD-3-Clause
+ * SPDX-FileCopyrightText: 2014 Silicon Laboratories, Inc.
+ * SPDX-FileCopyrightText: 2014 Pierre-noel Bouteville . All rights reserved.
+ * SPDX-FileCopyrightText: 2014 Gregory Nutt. All rights reserved.
+ * SPDX-FileContributor: Pierre-noel Bouteville <pnb990@gmail.com>
+ * SPDX-FileContributor: Gregory Nutt <gnutt@nuttx.org>
 *
 * Permission is granted to anyone to use this software for any purpose,
 * including commercial applications, and to alter it and redistribute it
@ -24,11 +29,6 @@
 * incidental, or special damages, or any other relief, or for any claim by
 * any third party, arising from your use of this Software.
 *
- *   Copyright (C) 2014 Pierre-noel Bouteville . All rights reserved.
- *   Copyright (C) 2014 Gregory Nutt. All rights reserved.
- *   Authors: Pierre-noel Bouteville <pnb990@gmail.com>
- *            Gregory Nutt <gnutt@nuttx.org>
- *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
--- a/arch/arm/src/efm32/hardware/efm32_adc.h
+++ b/arch/arm/src/efm32/hardware/efm32_adc.h
@ -1,7 +1,12 @@
 /****************************************************************************
 * arch/arm/src/efm32/hardware/efm32_adc.h
 *
- *  Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ * SPDX-License-Identifier: BSD-3-Clause
+ * SPDX-FileCopyrightText: 2014 Silicon Laboratories, Inc.
+ * SPDX-FileCopyrightText: 2014 Pierre-noel Bouteville . All rights reserved.
+ * SPDX-FileCopyrightText: 2014 Gregory Nutt. All rights reserved.
+ * SPDX-FileContributor: Pierre-noel Bouteville <pnb990@gmail.com>
+ * SPDX-FileContributor: Gregory Nutt <gnutt@nuttx.org>
 *
 * Permission is granted to anyone to use this software for any purpose,
 * including commercial applications, and to alter it and redistribute it
@ -24,11 +29,6 @@
 * incidental, or special damages, or any other relief, or for any claim by
 * any third party, arising from your use of this Software.
 *
- *   Copyright (C) 2014 Pierre-noel Bouteville . All rights reserved.
- *   Copyright (C) 2014 Gregory Nutt. All rights reserved.
- *   Authors: Pierre-noel Bouteville <pnb990@gmail.com>
- *            Gregory Nutt <gnutt@nuttx.org>
- *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
--- a/arch/arm/src/efm32/hardware/efm32_aes.h
+++ b/arch/arm/src/efm32/hardware/efm32_aes.h
@ -1,7 +1,12 @@
 /****************************************************************************
 * arch/arm/src/efm32/hardware/efm32_aes.h
 *
- *  Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ * SPDX-License-Identifier: BSD-3-Clause
+ * SPDX-FileCopyrightText: 2014 Silicon Laboratories, Inc.
+ * SPDX-FileCopyrightText: 2014 Pierre-noel Bouteville . All rights reserved.
+ * SPDX-FileCopyrightText: 2014 Gregory Nutt. All rights reserved.
+ * SPDX-FileContributor: Pierre-noel Bouteville <pnb990@gmail.com>
+ * SPDX-FileContributor: Gregory Nutt <gnutt@nuttx.org>
 *
 * Permission is granted to anyone to use this software for any purpose,
 * including commercial applications, and to alter it and redistribute it
@ -24,11 +29,6 @@
 * incidental, or special damages, or any other relief, or for any claim by
 * any third party, arising from your use of this Software.
 *
- *   Copyright (C) 2014 Pierre-noel Bouteville . All rights reserved.
- *   Copyright (C) 2014 Gregory Nutt. All rights reserved.
- *   Authors: Pierre-noel Bouteville <pnb990@gmail.com>
- *            Gregory Nutt <gnutt@nuttx.org>
- *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
--- a/arch/arm/src/efm32/hardware/efm32_burtc.h
+++ b/arch/arm/src/efm32/hardware/efm32_burtc.h
@ -1,7 +1,12 @@
 /****************************************************************************
 * arch/arm/src/efm32/hardware/efm32_burtc.h
 *
- *  Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ * SPDX-License-Identifier: BSD-3-Clause
+ * SPDX-FileCopyrightText: 2014 Silicon Laboratories, Inc.
+ * SPDX-FileCopyrightText: 2014 Pierre-noel Bouteville . All rights reserved.
+ * SPDX-FileCopyrightText: 2014 Gregory Nutt. All rights reserved.
+ * SPDX-FileContributor: Pierre-noel Bouteville <pnb990@gmail.com>
+ * SPDX-FileContributor: Gregory Nutt <gnutt@nuttx.org>
 *
 * Permission is granted to anyone to use this software for any purpose,
 * including commercial applications, and to alter it and redistribute it
@ -24,11 +29,6 @@
 * incidental, or special damages, or any other relief, or for any claim by
 * any third party, arising from your use of this Software.
 *
- *   Copyright (C) 2014 Pierre-noel Bouteville . All rights reserved.
- *   Copyright (C) 2014 Gregory Nutt. All rights reserved.
- *   Authors: Pierre-noel Bouteville <pnb990@gmail.com>
- *            Gregory Nutt <gnutt@nuttx.org>
- *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
--- a/arch/arm/src/efm32/hardware/efm32_calibrate.h
+++ b/arch/arm/src/efm32/hardware/efm32_calibrate.h
@ -1,7 +1,12 @@
 /****************************************************************************
 * arch/arm/src/efm32/hardware/efm32_calibrate.h
 *
- *  Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ * SPDX-License-Identifier: BSD-3-Clause
+ * SPDX-FileCopyrightText: 2014 Silicon Laboratories, Inc.
+ * SPDX-FileCopyrightText: 2014 Pierre-noel Bouteville . All rights reserved.
+ * SPDX-FileCopyrightText: 2014 Gregory Nutt. All rights reserved.
+ * SPDX-FileContributor: Pierre-noel Bouteville <pnb990@gmail.com>
+ * SPDX-FileContributor: Gregory Nutt <gnutt@nuttx.org>
 *
 * Permission is granted to anyone to use this software for any purpose,
 * including commercial applications, and to alter it and redistribute it
@ -24,11 +29,6 @@
 * incidental, or special damages, or any other relief, or for any claim by
 * any third party, arising from your use of this Software.
 *
- *   Copyright (C) 2014 Pierre-noel Bouteville . All rights reserved.
- *   Copyright (C) 2014 Gregory Nutt. All rights reserved.
- *   Authors: Pierre-noel Bouteville <pnb990@gmail.com>
- *            Gregory Nutt <gnutt@nuttx.org>
- *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
--- a/arch/arm/src/efm32/hardware/efm32_cmu.h
+++ b/arch/arm/src/efm32/hardware/efm32_cmu.h
@ -1,7 +1,12 @@
 /****************************************************************************
 * arch/arm/src/efm32/hardware/efm32_cmu.h
 *
- *    (C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com
+ * SPDX-License-Identifier: BSD-3-Clause
+ * SPDX-FileCopyrightText: 2014 Silicon Laboratories, Inc.
+ * SPDX-FileCopyrightText: 2014 Pierre-noel Bouteville . All rights reserved.
+ * SPDX-FileCopyrightText: 2014 Gregory Nutt. All rights reserved.
+ * SPDX-FileContributor: Pierre-noel Bouteville <pnb990@gmail.com>
+ * SPDX-FileContributor: Gregory Nutt <gnutt@nuttx.org>
 *
 * Permission is granted to anyone to use this software for any purpose,
 * including commercial applications, and to alter it and redistribute it
@ -24,11 +29,6 @@
 * incidental, or special damages, or any other relief, or for any claim by
 * any third party, arising from your use of this Software.
 *
- *   Copyright (C) 2014 Pierre-noel Bouteville . All rights reserved.
- *   Copyright (C) 2014 Gregory Nutt. All rights reserved.
- *   Authors: Pierre-noel Bouteville <pnb990@gmail.com>
- *            Gregory Nutt <gnutt@nuttx.org>
- *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
--- a/arch/arm/src/efm32/hardware/efm32_dac.h
+++ b/arch/arm/src/efm32/hardware/efm32_dac.h
@ -1,7 +1,12 @@
 /****************************************************************************
 * arch/arm/src/efm32/hardware/efm32_dac.h
 *
- *  Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ * SPDX-License-Identifier: BSD-3-Clause
+ * SPDX-FileCopyrightText: 2014 Silicon Laboratories, Inc.
+ * SPDX-FileCopyrightText: 2014 Pierre-noel Bouteville . All rights reserved.
+ * SPDX-FileCopyrightText: 2014 Gregory Nutt. All rights reserved.
+ * SPDX-FileContributor: Pierre-noel Bouteville <pnb990@gmail.com>
+ * SPDX-FileContributor: Gregory Nutt <gnutt@nuttx.org>
 *
 * Permission is granted to anyone to use this software for any purpose,
 * including commercial applications, and to alter it and redistribute it
@ -24,11 +29,6 @@
 * incidental, or special damages, or any other relief, or for any claim by
 * any third party, arising from your use of this Software.
 *
- *   Copyright (C) 2014 Pierre-noel Bouteville . All rights reserved.
- *   Copyright (C) 2014 Gregory Nutt. All rights reserved.
- *   Authors: Pierre-noel Bouteville <pnb990@gmail.com>
- *            Gregory Nutt <gnutt@nuttx.org>
- *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
--- a/arch/arm/src/efm32/hardware/efm32_devinfo.h
+++ b/arch/arm/src/efm32/hardware/efm32_devinfo.h
@ -1,7 +1,12 @@
 /****************************************************************************
 * arch/arm/src/efm32/hardware/efm32_devinfo.h
 *
- *  Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ * SPDX-License-Identifier: BSD-3-Clause
+ * SPDX-FileCopyrightText: 2014 Silicon Laboratories, Inc.
+ * SPDX-FileCopyrightText: 2014 Pierre-noel Bouteville . All rights reserved.
+ * SPDX-FileCopyrightText: 2014 Gregory Nutt. All rights reserved.
+ * SPDX-FileContributor: Pierre-noel Bouteville <pnb990@gmail.com>
+ * SPDX-FileContributor: Gregory Nutt <gnutt@nuttx.org>
 *
 * Permission is granted to anyone to use this software for any purpose,
 * including commercial applications, and to alter it and redistribute it
@ -24,11 +29,6 @@
 * incidental, or special damages, or any other relief, or for any claim by
 * any third party, arising from your use of this Software.
 *
- *   Copyright (C) 2014 Pierre-noel Bouteville . All rights reserved.
- *   Copyright (C) 2014 Gregory Nutt. All rights reserved.
- *   Authors: Pierre-noel Bouteville <pnb990@gmail.com>
- *            Gregory Nutt <gnutt@nuttx.org>
- *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
--- a/arch/arm/src/efm32/hardware/efm32_dma.h
+++ b/arch/arm/src/efm32/hardware/efm32_dma.h
@ -1,7 +1,12 @@
 /****************************************************************************
 * arch/arm/src/efm32/hardware/efm32_dma.h
 *
- *  Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ * SPDX-License-Identifier: BSD-3-Clause
+ * SPDX-FileCopyrightText: 2014 Silicon Laboratories, Inc.
+ * SPDX-FileCopyrightText: 2014 Pierre-noel Bouteville . All rights reserved.
+ * SPDX-FileCopyrightText: 2014 Gregory Nutt. All rights reserved.
+ * SPDX-FileContributor: Pierre-noel Bouteville <pnb990@gmail.com>
+ * SPDX-FileContributor: Gregory Nutt <gnutt@nuttx.org>
 *
 * Permission is granted to anyone to use this software for any purpose,
 * including commercial applications, and to alter it and redistribute it
@ -24,11 +29,6 @@
 * incidental, or special damages, or any other relief, or for any claim by
 * any third party, arising from your use of this Software.
 *
- *   Copyright (C) 2014 Pierre-noel Bouteville . All rights reserved.
- *   Copyright (C) 2014 Gregory Nutt. All rights reserved.
- *   Authors: Pierre-noel Bouteville <pnb990@gmail.com>
- *            Gregory Nutt <gnutt@nuttx.org>
- *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
--- a/arch/arm/src/efm32/hardware/efm32_emu.h
+++ b/arch/arm/src/efm32/hardware/efm32_emu.h
@ -1,7 +1,12 @@
 /****************************************************************************
 * arch/arm/src/efm32/hardware/efm32_emu.h
 *
- *  Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ * SPDX-License-Identifier: BSD-3-Clause
+ * SPDX-FileCopyrightText: 2014 Silicon Laboratories, Inc.
+ * SPDX-FileCopyrightText: 2014 Pierre-noel Bouteville . All rights reserved.
+ * SPDX-FileCopyrightText: 2014 Gregory Nutt. All rights reserved.
+ * SPDX-FileContributor: Pierre-noel Bouteville <pnb990@gmail.com>
+ * SPDX-FileContributor: Gregory Nutt <gnutt@nuttx.org>
 *
 * Permission is granted to anyone to use this software for any purpose,
 * including commercial applications, and to alter it and redistribute it
@ -24,11 +29,6 @@
 * incidental, or special damages, or any other relief, or for any claim by
 * any third party, arising from your use of this Software.
 *
- *   Copyright (C) 2014 Pierre-noel Bouteville . All rights reserved.
- *   Copyright (C) 2014 Gregory Nutt. All rights reserved.
- *   Authors: Pierre-noel Bouteville <pnb990@gmail.com>
- *            Gregory Nutt <gnutt@nuttx.org>
- *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
--- a/arch/arm/src/efm32/hardware/efm32_flash.h
+++ b/arch/arm/src/efm32/hardware/efm32_flash.h
@ -1,6 +1,8 @@
 /****************************************************************************
 * arch/arm/src/efm32/hardware/efm32_flash.h
 *
+ * SPDX-License-Identifier: Apache-2.0
+ *
 * Licensed to the Apache Software Foundation (ASF) under one or more
 * contributor license agreements.  See the NOTICE file distributed with
 * this work for additional information regarding copyright ownership.  The
--- a/arch/arm/src/efm32/hardware/efm32_gpio.h
+++ b/arch/arm/src/efm32/hardware/efm32_gpio.h
@ -1,7 +1,12 @@
 /****************************************************************************
 * arch/arm/src/efm32/hardware/efm32_gpio.h
 *
- *    (C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ * SPDX-License-Identifier: BSD-3-Clause
+ * SPDX-FileCopyrightText: 2014 Silicon Laboratories, Inc.
+ * SPDX-FileCopyrightText: 2014 Pierre-noel Bouteville . All rights reserved.
+ * SPDX-FileCopyrightText: 2014 Gregory Nutt. All rights reserved.
+ * SPDX-FileContributor: Pierre-noel Bouteville <pnb990@gmail.com>
+ * SPDX-FileContributor: Gregory Nutt <gnutt@nuttx.org>
 *
 * Permission is granted to anyone to use this software for any purpose,
 * including commercial applications, and to alter it and redistribute it
@ -24,11 +29,6 @@
 * incidental, or special damages, or any other relief, or for any claim by
 * any third party, arising from your use of this Software.
 *
- *   Copyright (C) 2014 Pierre-noel Bouteville . All rights reserved.
- *   Copyright (C) 2014 Gregory Nutt. All rights reserved.
- *   Authors: Pierre-noel Bouteville <pnb990@gmail.com>
- *            Gregory Nutt <gnutt@nuttx.org>
- *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
--- a/arch/arm/src/efm32/hardware/efm32_i2c.h
+++ b/arch/arm/src/efm32/hardware/efm32_i2c.h
@ -1,7 +1,12 @@
 /****************************************************************************
 * arch/arm/src/efm32/hardware/efm32_i2c.h
 *
- *  Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ * SPDX-License-Identifier: BSD-3-Clause
+ * SPDX-FileCopyrightText: 2014 Silicon Laboratories, Inc.
+ * SPDX-FileCopyrightText: 2014 Pierre-noel Bouteville . All rights reserved.
+ * SPDX-FileCopyrightText: 2014 Gregory Nutt. All rights reserved.
+ * SPDX-FileContributor: Pierre-noel Bouteville <pnb990@gmail.com>
+ * SPDX-FileContributor: Gregory Nutt <gnutt@nuttx.org>
 *
 * Permission is granted to anyone to use this software for any purpose,
 * including commercial applications, and to alter it and redistribute it
@ -24,11 +29,6 @@
 * incidental, or special damages, or any other relief, or for any claim by
 * any third party, arising from your use of this Software.
 *
- *   Copyright (C) 2014 Pierre-noel Bouteville . All rights reserved.
- *   Copyright (C) 2014 Gregory Nutt. All rights reserved.
- *   Authors: Pierre-noel Bouteville <pnb990@gmail.com>
- *            Gregory Nutt <gnutt@nuttx.org>
- *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
--- a/arch/arm/src/efm32/hardware/efm32_lcd.h
+++ b/arch/arm/src/efm32/hardware/efm32_lcd.h
@ -1,7 +1,12 @@
 /****************************************************************************
 * arch/arm/src/efm32/hardware/efm32_lcd.h
 *
- *  Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ * SPDX-License-Identifier: BSD-3-Clause
+ * SPDX-FileCopyrightText: 2014 Silicon Laboratories, Inc.
+ * SPDX-FileCopyrightText: 2014 Pierre-noel Bouteville . All rights reserved.
+ * SPDX-FileCopyrightText: 2014 Gregory Nutt. All rights reserved.
+ * SPDX-FileContributor: Pierre-noel Bouteville <pnb990@gmail.com>
+ * SPDX-FileContributor: Gregory Nutt <gnutt@nuttx.org>
 *
 * Permission is granted to anyone to use this software for any purpose,
 * including commercial applications, and to alter it and redistribute it
@ -24,11 +29,6 @@
 * incidental, or special damages, or any other relief, or for any claim by
 * any third party, arising from your use of this Software.
 *
- *   Copyright (C) 2014 Pierre-noel Bouteville . All rights reserved.
- *   Copyright (C) 2014 Gregory Nutt. All rights reserved.
- *   Authors: Pierre-noel Bouteville <pnb990@gmail.com>
- *            Gregory Nutt <gnutt@nuttx.org>
- *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
--- a/arch/arm/src/efm32/hardware/efm32_lesense.h
+++ b/arch/arm/src/efm32/hardware/efm32_lesense.h
@ -1,7 +1,12 @@
 /****************************************************************************
 * arch/arm/src/efm32/hardware/efm32_lesense.h
 *
- *  Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ * SPDX-License-Identifier: BSD-3-Clause
+ * SPDX-FileCopyrightText: 2014 Silicon Laboratories, Inc.
+ * SPDX-FileCopyrightText: 2014 Pierre-noel Bouteville . All rights reserved.
+ * SPDX-FileCopyrightText: 2014 Gregory Nutt. All rights reserved.
+ * SPDX-FileContributor: Pierre-noel Bouteville <pnb990@gmail.com>
+ * SPDX-FileContributor: Gregory Nutt <gnutt@nuttx.org>
 *
 * Permission is granted to anyone to use this software for any purpose,
 * including commercial applications, and to alter it and redistribute it
@ -24,11 +29,6 @@
 * incidental, or special damages, or any other relief, or for any claim by
 * any third party, arising from your use of this Software.
 *
- *   Copyright (C) 2014 Pierre-noel Bouteville . All rights reserved.
- *   Copyright (C) 2014 Gregory Nutt. All rights reserved.
- *   Authors: Pierre-noel Bouteville <pnb990@gmail.com>
- *            Gregory Nutt <gnutt@nuttx.org>
- *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
--- a/arch/arm/src/efm32/hardware/efm32_letimer.h
+++ b/arch/arm/src/efm32/hardware/efm32_letimer.h
@ -1,7 +1,12 @@
 /****************************************************************************
 * arch/arm/src/efm32/hardware/efm32_letimer.h
 *
- *  Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ * SPDX-License-Identifier: BSD-3-Clause
+ * SPDX-FileCopyrightText: 2014 Silicon Laboratories, Inc.
+ * SPDX-FileCopyrightText: 2014 Pierre-noel Bouteville . All rights reserved.
+ * SPDX-FileCopyrightText: 2014 Gregory Nutt. All rights reserved.
+ * SPDX-FileContributor: Pierre-noel Bouteville <pnb990@gmail.com>
+ * SPDX-FileContributor: Gregory Nutt <gnutt@nuttx.org>
 *
 * Permission is granted to anyone to use this software for any purpose,
 * including commercial applications, and to alter it and redistribute it
@ -24,11 +29,6 @@
 * incidental, or special damages, or any other relief, or for any claim by
 * any third party, arising from your use of this Software.
 *
- *   Copyright (C) 2014 Pierre-noel Bouteville . All rights reserved.
- *   Copyright (C) 2014 Gregory Nutt. All rights reserved.
- *   Authors: Pierre-noel Bouteville <pnb990@gmail.com>
- *            Gregory Nutt <gnutt@nuttx.org>
- *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
--- a/arch/arm/src/efm32/hardware/efm32_leuart.h
+++ b/arch/arm/src/efm32/hardware/efm32_leuart.h
@ -1,7 +1,12 @@
 /****************************************************************************
 * arch/arm/src/efm32/hardware/efm32_leuart.h
 *
- *  Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ * SPDX-License-Identifier: BSD-3-Clause
+ * SPDX-FileCopyrightText: 2014 Silicon Laboratories, Inc.
+ * SPDX-FileCopyrightText: 2014 Pierre-noel Bouteville . All rights reserved.
+ * SPDX-FileCopyrightText: 2014 Gregory Nutt. All rights reserved.
+ * SPDX-FileContributor: Pierre-noel Bouteville <pnb990@gmail.com>
+ * SPDX-FileContributor: Gregory Nutt <gnutt@nuttx.org>
 *
 * Permission is granted to anyone to use this software for any purpose,
 * including commercial applications, and to alter it and redistribute it
@ -24,11 +29,6 @@
 * incidental, or special damages, or any other relief, or for any claim by
 * any third party, arising from your use of this Software.
 *
- *   Copyright (C) 2014 Pierre-noel Bouteville . All rights reserved.
- *   Copyright (C) 2014 Gregory Nutt. All rights reserved.
- *   Authors: Pierre-noel Bouteville <pnb990@gmail.com>
- *            Gregory Nutt <gnutt@nuttx.org>
- *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
--- a/arch/arm/src/efm32/hardware/efm32_memorymap.h
+++ b/arch/arm/src/efm32/hardware/efm32_memorymap.h
@ -1,6 +1,8 @@
 /****************************************************************************
 * arch/arm/src/efm32/hardware/efm32_memorymap.h
 *
+ * SPDX-License-Identifier: Apache-2.0
+ *
 * Licensed to the Apache Software Foundation (ASF) under one or more
 * contributor license agreements.  See the NOTICE file distributed with
 * this work for additional information regarding copyright ownership.  The
--- a/arch/arm/src/efm32/hardware/efm32_msc.h
+++ b/arch/arm/src/efm32/hardware/efm32_msc.h
@ -1,7 +1,12 @@
 /****************************************************************************
 * arch/arm/src/efm32/hardware/efm32_msc.h
 *
- *  Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ * SPDX-License-Identifier: BSD-3-Clause
+ * SPDX-FileCopyrightText: 2014 Silicon Laboratories, Inc.
+ * SPDX-FileCopyrightText: 2014 Pierre-noel Bouteville . All rights reserved.
+ * SPDX-FileCopyrightText: 2014 Gregory Nutt. All rights reserved.
+ * SPDX-FileContributor: Pierre-noel Bouteville <pnb990@gmail.com>
+ * SPDX-FileContributor: Gregory Nutt <gnutt@nuttx.org>
 *
 * Permission is granted to anyone to use this software for any purpose,
 * including commercial applications, and to alter it and redistribute it
@ -24,11 +29,6 @@
 * incidental, or special damages, or any other relief, or for any claim by
 * any third party, arising from your use of this Software.
 *
- *   Copyright (C) 2014 Pierre-noel Bouteville . All rights reserved.
- *   Copyright (C) 2014 Gregory Nutt. All rights reserved.
- *   Authors: Pierre-noel Bouteville <pnb990@gmail.com>
- *            Gregory Nutt <gnutt@nuttx.org>
- *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
--- a/arch/arm/src/efm32/hardware/efm32_pcnt.h
+++ b/arch/arm/src/efm32/hardware/efm32_pcnt.h
@ -1,7 +1,12 @@
 /****************************************************************************
 * arch/arm/src/efm32/hardware/efm32_pcnt.h
 *
- *  Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ * SPDX-License-Identifier: BSD-3-Clause
+ * SPDX-FileCopyrightText: 2014 Silicon Laboratories, Inc.
+ * SPDX-FileCopyrightText: 2014 Pierre-noel Bouteville . All rights reserved.
+ * SPDX-FileCopyrightText: 2014 Gregory Nutt. All rights reserved.
+ * SPDX-FileContributor: Pierre-noel Bouteville <pnb990@gmail.com>
+ * SPDX-FileContributor: Gregory Nutt <gnutt@nuttx.org>
 *
 * Permission is granted to anyone to use this software for any purpose,
 * including commercial applications, and to alter it and redistribute it
@ -24,11 +29,6 @@
 * incidental, or special damages, or any other relief, or for any claim by
 * any third party, arising from your use of this Software.
 *
- *   Copyright (C) 2014 Pierre-noel Bouteville . All rights reserved.
- *   Copyright (C) 2014 Gregory Nutt. All rights reserved.
- *   Authors: Pierre-noel Bouteville <pnb990@gmail.com>
- *            Gregory Nutt <gnutt@nuttx.org>
- *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
--- a/arch/arm/src/efm32/hardware/efm32_prs.h
+++ b/arch/arm/src/efm32/hardware/efm32_prs.h
@ -1,7 +1,12 @@
 /****************************************************************************
 * arch/arm/src/efm32/hardware/efm32_prs.h
 *
- *  Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ * SPDX-License-Identifier: BSD-3-Clause
+ * SPDX-FileCopyrightText: 2014 Silicon Laboratories, Inc.
+ * SPDX-FileCopyrightText: 2014 Pierre-noel Bouteville . All rights reserved.
+ * SPDX-FileCopyrightText: 2014 Gregory Nutt. All rights reserved.
+ * SPDX-FileContributor: Pierre-noel Bouteville <pnb990@gmail.com>
+ * SPDX-FileContributor: Gregory Nutt <gnutt@nuttx.org>
 *
 * Permission is granted to anyone to use this software for any purpose,
 * including commercial applications, and to alter it and redistribute it
@ -24,11 +29,6 @@
 * incidental, or special damages, or any other relief, or for any claim by
 * any third party, arising from your use of this Software.
 *
- *   Copyright (C) 2014 Pierre-noel Bouteville . All rights reserved.
- *   Copyright (C) 2014 Gregory Nutt. All rights reserved.
- *   Authors: Pierre-noel Bouteville <pnb990@gmail.com>
- *            Gregory Nutt <gnutt@nuttx.org>
- *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
--- a/arch/arm/src/efm32/hardware/efm32_rmu.h
+++ b/arch/arm/src/efm32/hardware/efm32_rmu.h
@ -1,7 +1,12 @@
 /****************************************************************************
 * arch/arm/src/efm32/hardware/efm32_rmu.h
 *
- *  Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ * SPDX-License-Identifier: BSD-3-Clause
+ * SPDX-FileCopyrightText: 2014 Silicon Laboratories, Inc.
+ * SPDX-FileCopyrightText: 2014 Pierre-noel Bouteville . All rights reserved.
+ * SPDX-FileCopyrightText: 2014 Gregory Nutt. All rights reserved.
+ * SPDX-FileContributor: Pierre-noel Bouteville <pnb990@gmail.com>
+ * SPDX-FileContributor: Gregory Nutt <gnutt@nuttx.org>
 *
 * Permission is granted to anyone to use this software for any purpose,
 * including commercial applications, and to alter it and redistribute it
@ -24,11 +29,6 @@
 * incidental, or special damages, or any other relief, or for any claim by
 * any third party, arising from your use of this Software.
 *
- *   Copyright (C) 2014 Pierre-noel Bouteville . All rights reserved.
- *   Copyright (C) 2014 Gregory Nutt. All rights reserved.
- *   Authors: Pierre-noel Bouteville <pnb990@gmail.com>
- *            Gregory Nutt <gnutt@nuttx.org>
- *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
--- a/arch/arm/src/efm32/hardware/efm32_romtable.h
+++ b/arch/arm/src/efm32/hardware/efm32_romtable.h
@ -1,7 +1,12 @@
 /****************************************************************************
 * arch/arm/src/efm32/hardware/efm32_romtable.h
 *
- *  Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ * SPDX-License-Identifier: BSD-3-Clause
+ * SPDX-FileCopyrightText: 2014 Silicon Laboratories, Inc.
+ * SPDX-FileCopyrightText: 2014 Pierre-noel Bouteville . All rights reserved.
+ * SPDX-FileCopyrightText: 2014 Gregory Nutt. All rights reserved.
+ * SPDX-FileContributor: Pierre-noel Bouteville <pnb990@gmail.com>
+ * SPDX-FileContributor: Gregory Nutt <gnutt@nuttx.org>
 *
 * Permission is granted to anyone to use this software for any purpose,
 * including commercial applications, and to alter it and redistribute it
@ -24,11 +29,6 @@
 * incidental, or special damages, or any other relief, or for any claim by
 * any third party, arising from your use of this Software.
 *
- *   Copyright (C) 2014 Pierre-noel Bouteville . All rights reserved.
- *   Copyright (C) 2014 Gregory Nutt. All rights reserved.
- *   Authors: Pierre-noel Bouteville <pnb990@gmail.com>
- *            Gregory Nutt <gnutt@nuttx.org>
- *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
--- a/arch/arm/src/efm32/hardware/efm32_rtc.h
+++ b/arch/arm/src/efm32/hardware/efm32_rtc.h
@ -1,7 +1,12 @@
 /****************************************************************************
 * arch/arm/src/efm32/hardware/efm32_rtc.h
 *
- *  Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ * SPDX-License-Identifier: BSD-3-Clause
+ * SPDX-FileCopyrightText: 2014 Silicon Laboratories, Inc.
+ * SPDX-FileCopyrightText: 2014 Pierre-noel Bouteville . All rights reserved.
+ * SPDX-FileCopyrightText: 2014 Gregory Nutt. All rights reserved.
+ * SPDX-FileContributor: Pierre-noel Bouteville <pnb990@gmail.com>
+ * SPDX-FileContributor: Gregory Nutt <gnutt@nuttx.org>
 *
 * Permission is granted to anyone to use this software for any purpose,
 * including commercial applications, and to alter it and redistribute it
@ -24,11 +29,6 @@
 * incidental, or special damages, or any other relief, or for any claim by
 * any third party, arising from your use of this Software.
 *
- *   Copyright (C) 2014 Pierre-noel Bouteville . All rights reserved.
- *   Copyright (C) 2014 Gregory Nutt. All rights reserved.
- *   Authors: Pierre-noel Bouteville <pnb990@gmail.com>
- *            Gregory Nutt <gnutt@nuttx.org>
- *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
--- a/arch/arm/src/efm32/hardware/efm32_timer.h
+++ b/arch/arm/src/efm32/hardware/efm32_timer.h
@ -1,7 +1,12 @@
 /****************************************************************************
 * arch/arm/src/efm32/hardware/efm32_timer.h
 *
- *  Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ * SPDX-License-Identifier: BSD-3-Clause
+ * SPDX-FileCopyrightText: 2014 Silicon Laboratories, Inc.
+ * SPDX-FileCopyrightText: 2014 Pierre-noel Bouteville . All rights reserved.
+ * SPDX-FileCopyrightText: 2014 Gregory Nutt. All rights reserved.
+ * SPDX-FileContributor: Pierre-noel Bouteville <pnb990@gmail.com>
+ * SPDX-FileContributor: Gregory Nutt <gnutt@nuttx.org>
 *
 * Permission is granted to anyone to use this software for any purpose,
 * including commercial applications, and to alter it and redistribute it
@ -24,11 +29,6 @@
 * incidental, or special damages, or any other relief, or for any claim by
 * any third party, arising from your use of this Software.
 *
- *   Copyright (C) 2014 Pierre-noel Bouteville . All rights reserved.
- *   Copyright (C) 2014 Gregory Nutt. All rights reserved.
- *   Authors: Pierre-noel Bouteville <pnb990@gmail.com>
- *            Gregory Nutt <gnutt@nuttx.org>
- *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
--- a/arch/arm/src/efm32/hardware/efm32_usart.h
+++ b/arch/arm/src/efm32/hardware/efm32_usart.h
@ -1,7 +1,12 @@
 /****************************************************************************
 * arch/arm/src/efm32/hardware/efm32_usart.h
 *
- *    (C) Copyright 2014 Silicon Labs, http://www.silabs.com
+ * SPDX-License-Identifier: BSD-3-Clause
+ * SPDX-FileCopyrightText: 2014 Silicon Laboratories, Inc.
+ * SPDX-FileCopyrightText: 2014 Pierre-noel Bouteville . All rights reserved.
+ * SPDX-FileCopyrightText: 2014 Gregory Nutt. All rights reserved.
+ * SPDX-FileContributor: Pierre-noel Bouteville <pnb990@gmail.com>
+ * SPDX-FileContributor: Gregory Nutt <gnutt@nuttx.org>
 *
 * Permission is granted to anyone to use this software for any purpose,
 * including commercial applications, and to alter it and redistribute it
@ -24,11 +29,6 @@
 * special damages, or any other relief, or for any claim by any third party,
 * arising from your use of this Software.
 *
- *   Copyright (C) 2014 Pierre-noel Bouteville . All rights reserved.
- *   Copyright (C) 2014 Gregory Nutt. All rights reserved.
- *   Authors: Pierre-noel Bouteville <pnb990@gmail.com>
- *            Gregory Nutt <gnutt@nuttx.org>
- *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
--- a/arch/arm/src/efm32/hardware/efm32_usb.h
+++ b/arch/arm/src/efm32/hardware/efm32_usb.h
@ -1,7 +1,12 @@
 /****************************************************************************
 * arch/arm/src/efm32/hardware/efm32_usb.h
 *
- *  Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ * SPDX-License-Identifier: BSD-3-Clause
+ * SPDX-FileCopyrightText: 2014 Silicon Laboratories, Inc.
+ * SPDX-FileCopyrightText: 2014 Pierre-noel Bouteville . All rights reserved.
+ * SPDX-FileCopyrightText: 2014 Gregory Nutt. All rights reserved.
+ * SPDX-FileContributor: Pierre-noel Bouteville <pnb990@gmail.com>
+ * SPDX-FileContributor: Gregory Nutt <gnutt@nuttx.org>
 *
 * Permission is granted to anyone to use this software for any purpose,
 * including commercial applications, and to alter it and redistribute it
@ -24,11 +29,6 @@
 * incidental, or special damages, or any other relief, or for any claim by
 * any third party, arising from your use of this Software.
 *
- *   Copyright (C) 2014 Pierre-noel Bouteville . All rights reserved.
- *   Copyright (C) 2014 Gregory Nutt. All rights reserved.
- *   Authors: Pierre-noel Bouteville <pnb990@gmail.com>
- *            Gregory Nutt <gnutt@nuttx.org>
- *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
--- a/arch/arm/src/efm32/hardware/efm32_vcmp.h
+++ b/arch/arm/src/efm32/hardware/efm32_vcmp.h
@ -1,7 +1,12 @@
 /****************************************************************************
 * arch/arm/src/efm32/hardware/efm32_vcmp.h
 *
- *  Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ * SPDX-License-Identifier: BSD-3-Clause
+ * SPDX-FileCopyrightText: 2014 Silicon Laboratories, Inc.
+ * SPDX-FileCopyrightText: 2014 Pierre-noel Bouteville . All rights reserved.
+ * SPDX-FileCopyrightText: 2014 Gregory Nutt. All rights reserved.
+ * SPDX-FileContributor: Pierre-noel Bouteville <pnb990@gmail.com>
+ * SPDX-FileContributor: Gregory Nutt <gnutt@nuttx.org>
 *
 * Permission is granted to anyone to use this software for any purpose,
 * including commercial applications, and to alter it and redistribute it
@ -24,11 +29,6 @@
 * incidental, or special damages, or any other relief, or for any claim by
 * any third party, arising from your use of this Software.
 *
- *   Copyright (C) 2014 Pierre-noel Bouteville . All rights reserved.
- *   Copyright (C) 2014 Gregory Nutt. All rights reserved.
- *   Authors: Pierre-noel Bouteville <pnb990@gmail.com>
- *            Gregory Nutt <gnutt@nuttx.org>
- *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
--- a/arch/arm/src/efm32/hardware/efm32_wdog.h
+++ b/arch/arm/src/efm32/hardware/efm32_wdog.h
@ -1,7 +1,12 @@
 /****************************************************************************
 * arch/arm/src/efm32/hardware/efm32_wdog.h
 *
- *  Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ * SPDX-License-Identifier: BSD-3-Clause
+ * SPDX-FileCopyrightText: 2014 Silicon Laboratories, Inc.
+ * SPDX-FileCopyrightText: 2014 Pierre-noel Bouteville . All rights reserved.
+ * SPDX-FileCopyrightText: 2014 Gregory Nutt. All rights reserved.
+ * SPDX-FileContributor: Pierre-noel Bouteville <pnb990@gmail.com>
+ * SPDX-FileContributor: Gregory Nutt <gnutt@nuttx.org>
 *
 * Permission is granted to anyone to use this software for any purpose,
 * including commercial applications, and to alter it and redistribute it
@ -24,11 +29,6 @@
 * incidental, or special damages, or any other relief, or for any claim by
 * any third party, arising from your use of this Software.
 *
- *   Copyright (C) 2014 Pierre-noel Bouteville . All rights reserved.
- *   Copyright (C) 2014 Gregory Nutt. All rights reserved.
- *   Authors: Pierre-noel Bouteville <pnb990@gmail.com>
- *            Gregory Nutt <gnutt@nuttx.org>
- *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
--- a/arch/arm/src/efm32/hardware/efm32g_memorymap.h
+++ b/arch/arm/src/efm32/hardware/efm32g_memorymap.h
@ -1,6 +1,8 @@
 /****************************************************************************
 * arch/arm/src/efm32/hardware/efm32g_memorymap.h
 *
+ * SPDX-License-Identifier: Apache-2.0
+ *
 * Licensed to the Apache Software Foundation (ASF) under one or more
 * contributor license agreements.  See the NOTICE file distributed with
 * this work for additional information regarding copyright ownership.  The
--- a/arch/arm/src/efm32/hardware/efm32gg_memorymap.h
+++ b/arch/arm/src/efm32/hardware/efm32gg_memorymap.h
@ -1,7 +1,10 @@
 /****************************************************************************
 * arch/arm/src/efm32/hardware/efm32gg_memorymap.h
 *
- *  Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ * SPDX-License-Identifier: BSD-3-Clause
+ * SPDX-FileCopyrightText: 2014 Silicon Laboratories, Inc.
+ * SPDX-FileCopyrightText: 2014 Pierre-noel Bouteville . All rights reserved.
+ * SPDX-FileContributor: Pierre-noel Bouteville <pnb990@gmail.com>
 *
 * Permission is granted to anyone to use this software for any purpose,
 * including commercial applications, and to alter it and redistribute it
@ -24,9 +27,6 @@
 * incidental, or special damages, or any other relief, or for any claim by
 * any third party, arising from your use of this Software.
 *
- *   Copyright (C) 2014 Pierre-noel Bouteville . All rights reserved.
- *   Author: Pierre-noel Bouteville <pnb990@gmail.com>
- *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
--- a/arch/arm/src/efm32/hardware/efm32tg_memorymap.h
+++ b/arch/arm/src/efm32/hardware/efm32tg_memorymap.h
@ -1,7 +1,10 @@
 /****************************************************************************
 * arch/arm/src/efm32/hardware/efm32tg_memorymap.h
 *
- *  Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ * SPDX-License-Identifier: BSD-3-Clause
+ * SPDX-FileCopyrightText: 2014 Silicon Laboratories, Inc.
+ * SPDX-FileCopyrightText: 2014 Pierre-noel Bouteville . All rights reserved.
+ * SPDX-FileContributor: Pierre-noel Bouteville <pnb990@gmail.com>
 *
 * Permission is granted to anyone to use this software for any purpose,
 * including commercial applications, and to alter it and redistribute it
@ -24,9 +27,6 @@
 * incidental, or special damages, or any other relief, or for any claim by
 * any third party, arising from your use of this Software.
 *
- *   Copyright (C) 2014 Pierre-noel Bouteville . All rights reserved.
- *   Author: Pierre-noel Bouteville <pnb990@gmail.com>
- *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
--- a/arch/arm/src/eoss3/eoss3_irq.c
+++ b/arch/arm/src/eoss3/eoss3_irq.c
@ -159,7 +159,6 @@ static int eoss3_reserved(int irq, void *context, void *arg)
 *
 ****************************************************************************/

-#ifdef CONFIG_ARMV7M_USEBASEPRI
 static inline void eoss3_prioritize_syscall(int priority)
 {
  uint32_t regval;
@ -171,7 +170,6 @@ static inline void eoss3_prioritize_syscall(int priority)
  regval |= (priority << NVIC_SYSH_PRIORITY_PR11_SHIFT);
  putreg32(regval, NVIC_SYSH8_11_PRIORITY);
 }
-#endif

 /****************************************************************************
 * Name: eoss3_irqinfo
@ -309,11 +307,9 @@ void up_irqinitialize(void)
  irq_attach(EOSS3_IRQ_SVCALL, arm_svcall, NULL);
  irq_attach(EOSS3_IRQ_HARDFAULT, arm_hardfault, NULL);

-#ifdef CONFIG_ARMV7M_USEBASEPRI
  /* Set the priority of the SVCall interrupt */

  eoss3_prioritize_syscall(NVIC_SYSH_SVCALL_PRIORITY);
-#endif

  /* If the MPU is enabled, then attach and enable the Memory Management
   * Fault handler.
--- a/arch/arm/src/gd32f4/gd32f4xx_irq.c
+++ b/arch/arm/src/gd32f4/gd32f4xx_irq.c
@ -184,7 +184,6 @@ static int gd32_reserved(int irq, void *context, void *arg)
 *
 ****************************************************************************/

-#ifdef CONFIG_ARMV7M_USEBASEPRI
 static inline void gd32_prioritize_syscall(int priority)
 {
  uint32_t regval;
@ -196,7 +195,6 @@ static inline void gd32_prioritize_syscall(int priority)
  regval |= (priority << NVIC_SYSH_PRIORITY_PR11_SHIFT);
  putreg32(regval, NVIC_SYSH8_11_PRIORITY);
 }
-#endif

 /****************************************************************************
 * Name: gd32_irqinfo
@ -332,9 +330,8 @@ void up_irqinitialize(void)
 #ifdef CONFIG_ARCH_IRQPRIO
  /* up_prioritize_irq(GD32_IRQ_PENDSV, NVIC_SYSH_PRIORITY_MIN); */
 #endif
-#ifdef CONFIG_ARMV7M_USEBASEPRI
+
  gd32_prioritize_syscall(NVIC_SYSH_SVCALL_PRIORITY);
-#endif

  /* If the MPU is enabled, then attach and enable the Memory Management
   * Fault handler.
--- a/arch/arm/src/gd32f4/gd32f4xx_progmem.c
+++ b/arch/arm/src/gd32f4/gd32f4xx_progmem.c
@ -74,12 +74,12 @@
 #    define FMC_PROGMEM_SECTOR_EADDR     (0x0810FFFF)

 #  elif defined(CONFIG_GD32F4_FLASH_CONFIG_K)
-#if defined(CONFIG_GD32F4_GD32F450) 
+#if defined(CONFIG_GD32F4_GD32F450)
 #    define FMC_PROGMEM_SECTOR_SIZES     {_K(16), _K(16), _K(16), _K(16)}
 #    define FMC_PROGMEM_SECTOR_NUM       (4)
 #    define FMC_PROGMEM_SECTOR_SADDR     (0x08100000)
 #    define FMC_PROGMEM_SECTOR_EADDR     (0x0810FFFF)
-#elif defined(CONFIG_GD32F4_GD32F470) 
+#elif defined(CONFIG_GD32F4_GD32F470)
 #    define FMC_PROGMEM_SECTOR_SIZES     {_K(256), _K(256), _K(256), _K(256)}
 #    define FMC_PROGMEM_SECTOR_NUM       (256)
 #    define FMC_PROGMEM_SECTOR_SADDR     (0x08200000)
--- a/arch/arm/src/imx6/imx_gpio.c
+++ b/arch/arm/src/imx6/imx_gpio.c
@ -48,6 +48,8 @@
 * Private Data
 ****************************************************************************/

+static spinlock_t g_imx_gpio_lock = SP_UNLOCKED;
+
 static const uint8_t g_gpio1_padmux[IMX_GPIO_NPINS] =
 {
  IMX_PADMUX_GPIO00_INDEX,           /* GPIO1 Pin 0 */
@ -515,7 +517,7 @@ int imx_config_gpio(gpio_pinset_t pinset)

  /* Configure the pin as an input initially to avoid any spurious outputs */

-  flags = spin_lock_irqsave(NULL);
+  flags = spin_lock_irqsave(&g_imx_gpio_lock);

  /* Configure based upon the pin mode */

@ -558,7 +560,7 @@ int imx_config_gpio(gpio_pinset_t pinset)
        break;
    }

-  spin_unlock_irqrestore(NULL, flags);
+  spin_unlock_irqrestore(&g_imx_gpio_lock, flags);
  return ret;
 }

@ -576,9 +578,9 @@ void imx_gpio_write(gpio_pinset_t pinset, bool value)
  int port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT;
  int pin  = (pinset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT;

-  flags = enter_critical_section();
+  flags = spin_lock_irqsave(&g_imx_gpio_lock);
  imx_gpio_setoutput(port, pin, value);
-  leave_critical_section(flags);
+  spin_unlock_irqrestore(&g_imx_gpio_lock, flags);
 }

 /****************************************************************************
@ -596,8 +598,8 @@ bool imx_gpio_read(gpio_pinset_t pinset)
  int pin  = (pinset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT;
  bool value;

-  flags = enter_critical_section();
+  flags = spin_lock_irqsave(&g_imx_gpio_lock);
  value = imx_gpio_getinput(port, pin);
-  leave_critical_section(flags);
+  spin_unlock_irqrestore(&g_imx_gpio_lock, flags);
  return value;
 }
--- a/arch/arm/src/imxrt/hardware/imxrt_flexio.h
+++ b/arch/arm/src/imxrt/hardware/imxrt_flexio.h
@ -41,7 +41,7 @@
 #define IMXRT_FLEXIO_SHIFTSTAT_OFFSET     0x0010 /* Shifter Status Register, offset: 0x10 */
 #define IMXRT_FLEXIO_SHIFTERR_OFFSET      0x0014 /* Shifter Error Register, offset: 0x14 */
 #define IMXRT_FLEXIO_TIMSTAT_OFFSET       0x0018 /* Timer Status Register, offset: 0x18 */
-#define IMXRT_FLEXIO_SHIFTSIEN_OFFSET     0x0020 /* Shift Enable, offset: 0x20 */ 
+#define IMXRT_FLEXIO_SHIFTSIEN_OFFSET     0x0020 /* Shift Enable, offset: 0x20 */
 #define IMXRT_FLEXIO_SHIFTEIEN_OFFSET     0x0024 /* Shifter Error Interrupt Enable, offset: 0x24 */
 #define IMXRT_FLEXIO_TIMIEN_OFFSET        0x0028 /* Timer Interrupt Enable Register, offset: 0x28 */
 #define IMXRT_FLEXIO_SHIFTSDEN_OFFSET     0x0030 /* Shifter Status DMA Enable, offset: 0x30 */
--- a/Show more
+++ b/Show more