484 lines
13 KiB
C
484 lines
13 KiB
C
/****************************************************************************
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* arch/xtensa/include/irq.h
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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/* This file should never be included directly but, rather, only indirectly
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* through nuttx/irq.h
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*/
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#ifndef __ARCH_XTENSA_INCLUDE_IRQ_H
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#define __ARCH_XTENSA_INCLUDE_IRQ_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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/* Include NuttX-specific IRQ definitions */
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#include <nuttx/config.h>
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#include <nuttx/irq.h>
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#include <sys/types.h>
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#ifndef __ASSEMBLY__
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# include <stdbool.h>
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# include <arch/syscall.h>
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#endif
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#include <arch/types.h>
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#include <arch/chip/tie.h>
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#include <arch/chip/core-isa.h>
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#include <arch/xtensa/core.h>
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#include <arch/xtensa/xtensa_specregs.h>
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#include <arch/xtensa/xtensa_corebits.h>
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#include <arch/xtensa/xtensa_coproc.h>
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/* Include chip-specific IRQ definitions (including IRQ numbers) */
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#include <arch/chip/irq.h>
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/* Include architecture-specific IRQ definitions */
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#ifdef CONFIG_ARCH_FAMILY_LX6
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# include <arch/lx6/irq.h>
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#elif CONFIG_ARCH_FAMILY_LX7
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# include <arch/lx7/irq.h>
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#else
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# error Unknown XTENSA architecture
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#endif
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* IRQ Stack Frame Format. Each value is a uint32_t register index */
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#define REG_PC (0) /* Return PC */
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#define REG_PS (1) /* Return PS */
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#define REG_A0 (2)
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#define REG_A1 (3) /* Stack pointer before interrupt */
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#define REG_A2 (4)
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#define REG_A3 (5)
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#define REG_A4 (6)
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#define REG_A5 (7)
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#define REG_A6 (8)
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#define REG_A7 (9)
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#define REG_A8 (10)
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#define REG_A9 (11)
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#define REG_A10 (12)
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#define REG_A11 (13)
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#define REG_A12 (14)
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#define REG_A13 (15)
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#define REG_A14 (16)
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#define REG_A15 (17)
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#define REG_SAR (18)
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#define REG_EXCCAUSE (19)
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#define REG_EXCVADDR (20)
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#define REG_THREADPTR (21)
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#define _REG_EXTRA_START (22)
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#if XCHAL_HAVE_S32C1I != 0
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# define REG_SCOMPARE1 (_REG_EXTRA_START + 0)
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# define _REG_LOOPS_START (_REG_EXTRA_START + 1)
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#else
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# define _REG_LOOPS_START _REG_EXTRA_START
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#endif
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#if XCHAL_HAVE_LOOPS != 0
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# define REG_LBEG (_REG_LOOPS_START + 0)
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# define REG_LEND (_REG_LOOPS_START + 1)
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# define REG_LCOUNT (_REG_LOOPS_START + 2)
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# define _REG_WINDOW_TMPS (_REG_LOOPS_START + 3)
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#else
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# define _REG_WINDOW_TMPS _REG_LOOPS_START
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#endif
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#ifndef __XTENSA_CALL0_ABI__
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/* Temporary space for saving stuff during window spill. */
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# define REG_TMP0 (_REG_WINDOW_TMPS + 0)
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# define _REG_INT_CTX_START (_REG_WINDOW_TMPS + 1)
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#else
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# define _REG_INT_CTX_START _REG_WINDOW_TMPS
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#endif
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#ifndef CONFIG_BUILD_FLAT
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/* Temporary space for saving Interrupt Context information */
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# define REG_INT_CTX (_REG_INT_CTX_START + 0)
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# define _REG_OVLY_START (_REG_INT_CTX_START + 1)
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#else
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# define _REG_OVLY_START _REG_INT_CTX_START
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#endif
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#ifdef CONFIG_XTENSA_USE_OVLY
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/* Storage for overlay state */
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# error Overlays not supported
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# define _REG_CP_START _REG_OVLY_START
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#else
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# define _REG_CP_START _REG_OVLY_START
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#endif
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#if XCHAL_CP_NUM > 0
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/* FPU first address must align to CP align size.
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* ESP32 3rd party redefine the ALIGN_UP, so define a new macro XALIGN_UP()
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* instead use ALGIN_UP() in nuttx/nuttx.h
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*/
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# define XALIGN_UP(x,a) (((x) + ((a) - 1)) & ~((a) - 1))
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# define COMMON_CTX_REGS XALIGN_UP(_REG_CP_START, XCHAL_TOTAL_SA_ALIGN / 4)
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# define COPROC_CTX_REGS (XTENSA_CP_SA_SIZE / 4)
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# define RESERVE_REGS 8
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# define XCPTCONTEXT_REGS (COMMON_CTX_REGS + COPROC_CTX_REGS + RESERVE_REGS)
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#else
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# define COMMON_CTX_REGS _REG_CP_START
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# define RESERVE_REGS 8
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# define XCPTCONTEXT_REGS (COMMON_CTX_REGS + RESERVE_REGS)
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#endif
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#define XCPTCONTEXT_SIZE (4 * XCPTCONTEXT_REGS)
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/****************************************************************************
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* Public Types
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****************************************************************************/
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#ifndef __ASSEMBLY__
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#ifdef CONFIG_LIB_SYSCALL
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/* This structure represents the return state from a system call */
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struct xcpt_syscall_s
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{
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uintptr_t sysreturn; /* The return PC */
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#ifndef CONFIG_BUILD_FLAT
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uintptr_t int_ctx; /* Interrupt context */
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#endif
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};
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#endif
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/* This struct defines the way the registers are stored. */
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struct xcptcontext
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{
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/* These are saved copies of registers used during signal processing.
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*
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* REVISIT: Because there is only one copy of these save areas,
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* only a single signal handler can be active. This precludes
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* queuing of signal actions. As a result, signals received while
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* another signal handler is executing will be ignored!
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*/
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uint32_t *saved_regs;
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/* Register save area */
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uint32_t *regs;
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#ifndef CONFIG_BUILD_FLAT
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/* This is the saved address to use when returning from a user-space
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* signal handler.
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*/
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uintptr_t sigreturn;
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#endif
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#ifdef CONFIG_LIB_SYSCALL
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/* The following array holds the return address and the exc_return value
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* needed to return from each nested system call.
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*/
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uint8_t nsyscalls;
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struct xcpt_syscall_s syscall[CONFIG_SYS_NNEST];
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#endif
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};
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/****************************************************************************
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* Inline functions
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****************************************************************************/
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/* Return the current value of the PS register */
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static inline_function uint32_t xtensa_getps(void)
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{
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uint32_t ps;
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__asm__ __volatile__
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(
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"rsr %0, PS" : "=r"(ps)
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);
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return ps;
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}
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/* Set the value of the PS register */
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noinstrument_function static inline_function
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void xtensa_setps(uint32_t ps)
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{
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__asm__ __volatile__
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(
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"wsr %0, PS \n"
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"rsync \n"
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:
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: "r"(ps)
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: "memory"
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);
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}
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/* Return the current value of the stack pointer */
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static inline_function uint32_t up_getsp(void)
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{
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register uint32_t sp;
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__asm__ __volatile__
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(
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"mov %0, sp\n"
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: "=r" (sp)
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);
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return sp;
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}
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/* Restore the value of the PS register */
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noinstrument_function static inline_function
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void up_irq_restore(uint32_t ps)
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{
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__asm__ __volatile__
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(
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"wsr %0, PS\n"
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"rsync \n"
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:
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: "r"(ps)
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: "memory"
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);
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}
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/* Disable interrupts and return the previous value of the PS register */
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noinstrument_function static inline_function uint32_t up_irq_save(void)
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{
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uint32_t ps;
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/* Disable all low- and medium-priority interrupts. High priority
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* interrupts should not interfere with ongoing RTOS operations and
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* are not disabled.
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*/
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__asm__ __volatile__
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(
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"rsil %0, %1" : "=r"(ps) : "i"(XCHAL_IRQ_LEVEL)
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);
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/* Return the previous PS value so that it can be restored with
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* up_irq_restore().
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*/
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return ps;
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}
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/* Enable interrupts at all levels */
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static inline_function void up_irq_enable(void)
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{
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#ifdef __XTENSA_CALL0_ABI__
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xtensa_setps(PS_INTLEVEL(0) | PS_UM);
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#else
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xtensa_setps(PS_INTLEVEL(0) | PS_UM | PS_WOE);
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#endif
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}
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/* Disable low- and medium- priority interrupts */
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noinstrument_function static inline_function void up_irq_disable(void)
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{
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#ifdef __XTENSA_CALL0_ABI__
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xtensa_setps(PS_INTLEVEL(XCHAL_EXCM_LEVEL) | PS_UM);
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#else
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xtensa_setps(PS_INTLEVEL(XCHAL_EXCM_LEVEL) | PS_UM | PS_WOE);
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#endif
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}
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/****************************************************************************
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* Name: xtensa_disable_all
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****************************************************************************/
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static inline_function void xtensa_disable_all(void)
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{
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__asm__ __volatile__
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(
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"movi a2, 0\n"
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"xsr a2, INTENABLE\n"
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"rsync\n"
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: : : "a2"
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);
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}
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/****************************************************************************
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* Name: xtensa_intclear
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****************************************************************************/
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static inline_function void xtensa_intclear(uint32_t mask)
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{
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__asm__ __volatile__
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(
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"wsr %0, INTCLEAR\n"
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"rsync\n"
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:
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: "r"(mask)
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:
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);
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}
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#ifdef __cplusplus
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#define EXTERN extern "C"
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extern "C"
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{
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#else
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#define EXTERN extern
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#endif
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/****************************************************************************
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* Public Data
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****************************************************************************/
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#ifndef __ASSEMBLY__
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/* g_interrupt_context store irq status */
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extern volatile bool g_interrupt_context[CONFIG_SMP_NCPUS];
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#endif
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/****************************************************************************
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* Public Function Prototypes
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****************************************************************************/
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/****************************************************************************
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* Name: xtensa_enable_interrupts
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*
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* Description:
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* Enables a set of interrupts. Does not simply set INTENABLE directly,
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* but computes it as a function of the current virtual priority.
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* Can be called from interrupt handlers.
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*
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****************************************************************************/
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irqstate_t xtensa_enable_interrupts(irqstate_t mask);
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/****************************************************************************
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* Name: xtensa_disable_interrupts
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*
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* Description:
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* Disables a set of interrupts. Does not simply clear INTENABLE directly,
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* but computes it as a function of the current virtual priority.
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* Can be called from interrupt handlers.
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*
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****************************************************************************/
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irqstate_t xtensa_disable_interrupts(irqstate_t mask);
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/****************************************************************************
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* Name: up_cpu_index
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*
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* Description:
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* Return the real core number regardless CONFIG_SMP setting
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*
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****************************************************************************/
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#ifdef CONFIG_ARCH_HAVE_MULTICPU
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int up_cpu_index(void) noinstrument_function;
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#endif /* CONFIG_ARCH_HAVE_MULTICPU */
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/****************************************************************************
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* Name: up_set_interrupt_context
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*
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* Description:
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* Set the interrupt handler context.
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*
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****************************************************************************/
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noinstrument_function
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static inline_function void up_set_interrupt_context(bool flag)
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{
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#ifdef CONFIG_SMP
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g_interrupt_context[up_cpu_index()] = flag;
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#else
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g_interrupt_context[0] = flag;
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#endif
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}
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/****************************************************************************
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* Name: up_interrupt_context
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*
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* Description:
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* Return true is we are currently executing in the interrupt
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* handler context.
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*
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****************************************************************************/
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#ifndef __ASSEMBLY__
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noinstrument_function static inline_function bool up_interrupt_context(void)
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{
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#ifdef CONFIG_SMP
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irqstate_t flags = up_irq_save();
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bool ret = g_interrupt_context[up_cpu_index()];
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up_irq_restore(flags);
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return ret;
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#else
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return g_interrupt_context[0];
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#endif
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}
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#endif
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#define up_switch_context(tcb, rtcb) \
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do { \
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if (!up_interrupt_context()) \
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{ \
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sys_call0(SYS_switch_context); \
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} \
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UNUSED(rtcb); \
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} while (0)
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/****************************************************************************
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* Name: up_getusrpc
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****************************************************************************/
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#define up_getusrpc(regs) \
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(((uint32_t *)((regs) ? (regs) : running_regs()))[REG_PC])
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/****************************************************************************
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* Name: up_getusrsp
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****************************************************************************/
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#define up_getusrsp(regs) \
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(((uintptr_t*)(regs))[REG_A1])
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#undef EXTERN
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#ifdef __cplusplus
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}
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#endif
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#endif /* __ASSEMBLY__ */
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#endif /* __ARCH_XTENSA_INCLUDE_IRQ_H */
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