Ville Juven 737dc4fcdd arch/riscv: Implement cpuid mapping ... Implement hartid<->cpuid mapping for RISC-V. This is necessary for some platforms which cannot use 1:1 mapping between logical and physical CPU / core IDs. One example is MPFS where hart0 cannot be used for NuttX SMP as it is a less capable "monitor" core (E51) compared to the application cores hart1...3 (E54). Why not just use a generic offset then? We also need the physical hart ID for many things: - Communication between harts (IPI) - External interrupt acknowledgment (interrupt claim for specific CPU) - Communication to SBI Thus, create procedures that can do this translation: - The default mapping is still logical=physical. - Another flavor is to use the existing CONFIG_ARCH_RV_HARTID_BASE config variable, which is just a simple offset - The final flavor is to overload hartid<->cpuid on a per chip basis (no example for this is provided yet)		2024-10-17 13:43:06 +08:00
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include	arch/riscv: Implement cpuid mapping	2024-10-17 13:43:06 +08:00
src	arch/riscv: Implement cpuid mapping	2024-10-17 13:43:06 +08:00
CMakeLists.txt	cmake:init RISC-V cmake qemu-rv build	2023-10-26 21:01:46 +08:00
Kconfig	risc-v: Add a new option to control exception reason	2024-09-17 15:26:06 -03:00