nuttx-update/arch/risc-v
Huang Qi 74e59feaaa rv32m1: Fix compile error
Follow other risc-v based chips, and fix:
```
chip/rv32m1_irq.c: In function 'up_irqinitialize':
Error: chip/rv32m1_irq.c:98:3: error: array subscript -2048 is outside array bounds of 'uint8_t[2147483647]' {aka 'unsigned char[2147483647]'} [-Werror=array-bounds]
   98 |   riscv_stack_color(g_intstacktop - intstack_size, intstack_size);
      |   ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
In file included from /github/workspace/sources/nuttx/arch/risc-v/src/common/riscv_internal.h:40,
                 from chip/rv32m1_irq.c:36:
/github/workspace/sources/nuttx/arch/risc-v/src/common/riscv_common_memorymap.h:72:16: note: at offset -2048 into object 'g_intstacktop' of size [0, 2147483647]
   72 | EXTERN uint8_t g_intstacktop[];   /* Initial top of interrupt stack */
      |                ^~~~~~~~~~~~~
cc1: all warnings being treated as errors
```

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2023-09-20 17:04:56 +08:00
..
include arch/risc-v: Add support for StarFive JH7110 SoC 2023-08-03 22:55:55 -07:00
src rv32m1: Fix compile error 2023-09-20 17:04:56 +08:00
Kconfig risc-v/litex: Add system reset and access to core control registers. 2023-08-25 17:16:28 +08:00