forked from nuttx/nuttx-update
follow upstream change & fix minor things
Signed-off-by: Peter Bee <pbjd97@gmail.com>
This commit is contained in:
Peter Bee
Alan C. Assis
parent
48ded21e30
commit
c0f776dbc3
44 changed files with 468 additions and 690 deletions
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@ -1,11 +1,11 @@
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README
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======
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This directory contains the port of NuttX to the Raspberry Pi Pico.
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This directory contains the porting of NuttX to the Raspberry Pi Pico 2.
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See https://www.raspberrypi.org/products/raspberry-pi-pico-2/ for information
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about Raspberry Pi Pico 2.
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NuttX supports the following RP2530 capabilities:
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NuttX supports the following RP2350 capabilities:
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- UART (console port)
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- GPIO 0 (UART0 TX) and GPIO 1 (UART0 RX) are used for the console.
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- ADC
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@ -24,18 +24,18 @@ Installation
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$ cd nuttx
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$ make distclean
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$ ./tools/configure.sh raspberrypi-pico-2:nsh
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$ make V=1
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$ make -j
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4. Connect Raspberry Pi Pico 2 board to USB port while pressing BOOTSEL.
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4. Connect Raspberry Pi Pico 2 board to the USB port while pressing BOOTSEL.
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The board will be detected as USB Mass Storage Device.
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Then copy "nuttx.uf2" into the device.
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(Same manner as the standard Pico SDK applications installation.)
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5. To access the console, GPIO 0 and 1 pins must be connected to the
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device such as USB-serial converter.
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device such as a USB-serial converter.
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`usbnsh` configuration provides the console access by USB CDC/ACM serial
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devcice. The console is available by using a terminal software on the USB
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device. The console is available by using a terminal software on the USB
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host.
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Defconfigs
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@ -46,18 +46,3 @@ Defconfigs
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- usbnsh
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USB CDC/ACM serial console with NuttShell
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License exceptions
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==================
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The following files are originated from the files in Pico SDK.
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So, the files are licensed under 3-Clause BSD same as Pico SDK.
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- arch/arm/src/rp23xx/rp23xx_clock.c
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- arch/arm/src/rp23xx/rp23xx_pll.c
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- arch/arm/src/rp23xx/rp23xx_xosc.c
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- These are created by referring the Pico SDK clock initialization.
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- arch/arm/src/rp23xx/hardware/*.h
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- arch/arm/src/rp23xx/pico/*.h
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- These are originally provided in Pico SDK.
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@ -1,5 +1,5 @@
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===============================
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Raspberry Pi Pico
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Raspberry Pi Pico 2
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===============================
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The `Raspberry Pi Pico 2 <https://www.raspberrypi.com/products/raspberry-pi-pico-2/>`_ is a general purpose board supplied by
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@ -23,7 +23,7 @@ Features
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* Accurate clock and timer on-chip
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* Temperature sensor
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* Accelerated floating point libraries on-chip
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* 8 × Programmable IO (PIO) state machines for custom peripheral support
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* 12 × Programmable IO (PIO) state machines for custom peripheral support
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Serial Console
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==============
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@ -41,9 +41,9 @@ User LED controlled by GPIO25 and is configured as autoled by default.
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A BOOTSEL button, which if held down when power is first
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applied to the board, will cause the RP2350 to boot into programming
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mode and appear as a storage device to a computer connected via USB .
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mode and appear as a storage device to the computer connected via USB.
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Saving a .UF2 file to this device will replace the Flash ROM contents
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on the RP2040.
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on the RP2350.
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Pin Mapping
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===========
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@ -16,18 +16,18 @@ Most drivers were copied from the rp2040 port with some modifications.
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The following list indicates peripherals currently supported in NuttX:
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============== ====== =====
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============== ============ =====
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Peripheral Status Notes
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============== ====== =====
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============== ============ =====
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GPIO Working See Supported Boards documentation for available pins.
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UART Working GPIO 0 (UART0 TX) and GPIO 1 (UART0 RX) are used for the console.
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I2C Untested
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SPI Master Untested
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SPI Slave Not working
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SPI Master Working
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SPI Slave Untested
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DMAC Untested
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PWM Untested
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USB Experimental usbnsh configuration is somewhat working with some data corruption
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PIO Untested
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PIO Working
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IRQs Working
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DMA Untested
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Clock Output Untested
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@ -35,7 +35,7 @@ Flash ROM Boot Working Does not require boot2 from pico-sdk
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If picotool is available a nuttx.uf2 file will be created
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SRAM Boot Working Requires external SWD debugger
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PSRAM Working Three modes of heap allocation described below
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============== ====== =====
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============== ============ =====
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Installation
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============
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@ -94,14 +94,14 @@ the flash on startup).
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It is also possible to execute from SRAM, which reduces the
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available SRAM to the OS and applications, however it is very
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useful when debugging as erasings and rewriting the flash on
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useful when debugging as erasing and rewriting the flash on
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every build is tedious and slow. This option is enabled with
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`BOOT_RUNFROMISRAM` and requires `openocd`` and/or `gdb`.
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There is a third option which is to write the firmware on the
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flash and it gets copied to the SRAM. This is enabled with
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`CONFIG_BOOT_COPYTORAM` and might be useful for time critical
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applications, on the expense of reduced useable interna SRAM
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applications, on the expense of reduced usable internal SRAM
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memory.
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PSRAM
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@ -195,7 +195,7 @@ Most builds provide access to the console via UART0. To access this
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GPIO 0 and 1 pins must be connected to the device such as USB-serial converter.
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The `usbnsh` configuration provides the console access by USB CDC/ACM serial
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devcice. The console is available by using a terminal software on the USB host.
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device. The console is available by using a terminal software on the USB host.
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Supported Boards
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================
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@ -55,7 +55,7 @@ extern "C"
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* to the instance of struct i2c_slave_s. This function should only be
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* called once of a give controller.
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*
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* Note: the same port cannot be initalized as both master and slave.
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* Note: the same port cannot be initialized as both master and slave.
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*
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* Input Parameters:
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* rx_buffer - Buffer for data transmitted to us by an I2C master.
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@ -84,7 +84,7 @@ struct i2c_slave_s *rp2040_i2c0_slave_initialize
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* to the instance of struct i2c_slave_s. This function should only be
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* called once of a give controller.
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*
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* Note: the same port cannot be initalized as both master and slave.
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* Note: the same port cannot be initialized as both master and slave.
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*
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* Input Parameters:
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* rx_buffer - Buffer for data transmitted to us by an I2C master.
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@ -55,7 +55,7 @@ extern "C"
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* to the instance of struct i2c_slave_s. This function should only be
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* called once of a give controller.
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*
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* Note: the same port cannot be initalized as both master and slave.
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* Note: the same port cannot be initialized as both master and slave.
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*
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* Input Parameters:
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* rx_buffer - Buffer for data transmitted to us by an I2C master.
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@ -84,7 +84,7 @@ struct i2c_slave_s *rp23xx_i2c0_slave_initialize
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* to the instance of struct i2c_slave_s. This function should only be
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* called once of a give controller.
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*
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* Note: the same port cannot be initalized as both master and slave.
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* Note: the same port cannot be initialized as both master and slave.
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*
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* Input Parameters:
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* rx_buffer - Buffer for data transmitted to us by an I2C master.
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@ -35,14 +35,17 @@ CHIP_CSRCS += rp23xx_xosc.c
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CHIP_CSRCS += rp23xx_pll.c
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ifeq ($(CONFIG_SMP),y)
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CHIP_CSRCS += rp23xx_cpuindex.c
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CHIP_CSRCS += rp23xx_cpustart.c
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CHIP_CSRCS += rp23xx_cpupause.c
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CHIP_CSRCS += rp23xx_smpcall.c
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CHIP_CSRCS += rp23xx_cpuidlestack.c
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CHIP_CSRCS += rp23xx_testset.c
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CMN_ASRCS := $(filter-out arm_testset.S,$(CMN_ASRCS))
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endif
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ifeq ($(CONFIG_ARCH_HAVE_MULTICPU),y)
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CHIP_CSRCS += rp23xx_cpuindex.c
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endif
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ifeq ($(CONFIG_RP23XX_DMAC),y)
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CHIP_CSRCS += rp23xx_dmac.c
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endif
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@ -33,7 +33,6 @@
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/* Register offsets *********************************************************/
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#define RP23XX_DMA_READ_ADDR_OFFSET 0x000000 /* DMA Read Address pointer */
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#define RP23XX_DMA_WRITE_ADDR_OFFSET 0x000004 /* DMA Write Address pointer */
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#define RP23XX_DMA_TRANS_COUNT_OFFSET 0x000008 /* DMA Transfer Count */
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@ -240,4 +239,4 @@
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#define RP23XX_DMA_SECCFG_MISC_TIMER3_S (1 << 9)
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#define RP23XX_DMA_DBG_CTDREQ_MASK (0x3f)
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#endif /*__ARCH_ARM_SRC_RP23XX_HARDWARE_RP23XX_DMA_H*/
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#endif /* __ARCH_ARM_SRC_RP23XX_HARDWARE_RP23XX_DMA_H */
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@ -55,5 +55,4 @@
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#define RP23XX_SHA256_WDATA_MASK (0xffffffff)
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#define RP23XX_SHA256_SUM_MASK (0xffffffff)
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#endif /* __ARCH_ARM_SRC_RP23XX_HARDWARE_RP23XX_SHA256_H */
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@ -1,38 +0,0 @@
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/*
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* Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef _PICO_H
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#define _PICO_H
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/** \file pico.h
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* \defgroup pico_base pico_base
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*
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* \brief Core types and macros for the Raspberry Pi Pico SDK.
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*
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* This header is intended to be included by all source code
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* as it includes configuration headers and overrides in the correct order
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*
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* This header may be included by assembly code
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*/
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// We may be included by assembly which can't include <cdefs.h>
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#define __PICO_STRING(x) #x
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#define __PICO_XSTRING(x) __PICO_STRING(x)
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#define __PICO_CONCAT1(x, y) x ## y
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#include "pico/types.h"
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#include "pico/version.h"
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// PICO_CONFIG: PICO_CONFIG_HEADER, Unquoted path to header include in place of the default pico/config.h which may be desirable for build systems which can't easily generate the config_autogen header, group=pico_base
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#ifdef PICO_CONFIG_HEADER
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#include __PICO_XSTRING(PICO_CONFIG_HEADER)
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#else
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#include "pico/config.h"
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#endif
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#include "pico/platform.h"
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#include "pico/error.h"
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#endif
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@ -29,7 +29,7 @@
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#include "arm_internal.h"
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#include "hardware/rp23xx_sio.h"
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#ifdef CONFIG_SMP
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#ifdef CONFIG_ARCH_HAVE_MULTICPU
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/****************************************************************************
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* Public Functions
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@ -1,498 +0,0 @@
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/****************************************************************************
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* arch/arm/src/rp23xx/rp23xx_cpupause.c
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
|
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
|
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
|
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
|
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* License for the specific language governing permissions and limitations
|
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* under the License.
|
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*
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****************************************************************************/
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include <stdint.h>
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#include <assert.h>
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#include <debug.h>
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#include <string.h>
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#include <stdio.h>
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#include <nuttx/arch.h>
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#include <nuttx/spinlock.h>
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#include <nuttx/sched_note.h>
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#include "sched/sched.h"
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#include "arm_internal.h"
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#include "hardware/rp23xx_sio.h"
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#ifdef CONFIG_SMP
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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#if 0
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#define DPRINTF(fmt, args...) llinfo(fmt, ##args)
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#else
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#define DPRINTF(fmt, args...) do {} while (0)
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#endif
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/****************************************************************************
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* Private Data
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****************************************************************************/
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/* These spinlocks are used in the SMP configuration in order to implement
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* up_cpu_pause(). The protocol for CPUn to pause CPUm is as follows
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*
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* 1. The up_cpu_pause() implementation on CPUn locks both g_cpu_wait[m]
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* and g_cpu_paused[m]. CPUn then waits spinning on g_cpu_paused[m].
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* 2. CPUm receives the interrupt it (1) unlocks g_cpu_paused[m] and
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* (2) locks g_cpu_wait[m]. The first unblocks CPUn and the second
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* blocks CPUm in the interrupt handler.
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*
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* When CPUm resumes, CPUn unlocks g_cpu_wait[m] and the interrupt handler
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* on CPUm continues. CPUm must, of course, also then unlock g_cpu_wait[m]
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* so that it will be ready for the next pause operation.
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*/
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static volatile spinlock_t g_cpu_wait[CONFIG_SMP_NCPUS];
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static volatile spinlock_t g_cpu_paused[CONFIG_SMP_NCPUS];
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static volatile spinlock_t g_cpu_resumed[CONFIG_SMP_NCPUS];
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/****************************************************************************
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* Name: rp23xx_handle_irqreq
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*
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* Description:
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* If an irq handling request is found on cpu, call up_enable_irq() or
|
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* up_disable_irq().
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*
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* Input Parameters:
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* irqreq - The IRQ number to be handled (>0 : enable / <0 : disable)
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*
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****************************************************************************/
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static void rp23xx_handle_irqreq(int irqreq)
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{
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DEBUGASSERT(up_cpu_index() == 0);
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/* Unlock the spinlock first */
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||||
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spin_unlock(&g_cpu_paused[0]);
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/* Then wait for the spinlock to be released */
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spin_lock(&g_cpu_wait[0]);
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if (irqreq > 0)
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{
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up_enable_irq(irqreq);
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}
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else
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{
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up_disable_irq(-irqreq);
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}
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||||
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||||
/* Finally unlock the spinlock */
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||||
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||||
spin_unlock(&g_cpu_wait[0]);
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||||
}
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||||
|
||||
/****************************************************************************
|
||||
* Public Functions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: up_cpu_pausereq
|
||||
*
|
||||
* Description:
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||||
* Return true if a pause request is pending for this CPU.
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||||
*
|
||||
* Input Parameters:
|
||||
* cpu - The index of the CPU to be queried
|
||||
*
|
||||
* Returned Value:
|
||||
* true = a pause request is pending.
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||||
* false = no pasue request is pending.
|
||||
*
|
||||
****************************************************************************/
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||||
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||||
bool up_cpu_pausereq(int cpu)
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||||
{
|
||||
return spin_is_locked(&g_cpu_paused[cpu]);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: up_cpu_paused_save
|
||||
*
|
||||
* Description:
|
||||
* Handle a pause request from another CPU. Normally, this logic is
|
||||
* executed from interrupt handling logic within the architecture-specific
|
||||
* However, it is sometimes necessary to perform the pending
|
||||
* pause operation in other contexts where the interrupt cannot be taken
|
||||
* in order to avoid deadlocks.
|
||||
*
|
||||
* Input Parameters:
|
||||
* None
|
||||
*
|
||||
* Returned Value:
|
||||
* On success, OK is returned. Otherwise, a negated errno value indicating
|
||||
* the nature of the failure is returned.
|
||||
*
|
||||
****************************************************************************/
|
||||
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||||
int up_cpu_paused_save(void)
|
||||
{
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||||
struct tcb_s *tcb = this_task();
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||||
|
||||
/* Update scheduler parameters */
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||||
|
||||
nxsched_suspend_scheduler(tcb);
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||||
|
||||
#ifdef CONFIG_SCHED_INSTRUMENTATION
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||||
/* Notify that we are paused */
|
||||
|
||||
sched_note_cpu_paused(tcb);
|
||||
#endif
|
||||
|
||||
/* Save the current context at CURRENT_REGS into the TCB at the head
|
||||
* of the assigned task list for this CPU.
|
||||
*/
|
||||
|
||||
arm_savestate(tcb->xcp.regs);
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||||
|
||||
return OK;
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: up_cpu_paused
|
||||
*
|
||||
* Description:
|
||||
* Handle a pause request from another CPU. Normally, this logic is
|
||||
* executed from interrupt handling logic within the architecture-specific
|
||||
* However, it is sometimes necessary to perform the pending
|
||||
* pause operation in other contexts where the interrupt cannot be taken
|
||||
* in order to avoid deadlocks.
|
||||
*
|
||||
* This function performs the following operations:
|
||||
*
|
||||
* 1. It saves the current task state at the head of the current assigned
|
||||
* task list.
|
||||
* 2. It waits on a spinlock, then
|
||||
* 3. Returns from interrupt, restoring the state of the new task at the
|
||||
* head of the ready to run list.
|
||||
*
|
||||
* Input Parameters:
|
||||
* cpu - The index of the CPU to be paused
|
||||
*
|
||||
* Returned Value:
|
||||
* On success, OK is returned. Otherwise, a negated errno value indicating
|
||||
* the nature of the failure is returned.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
int up_cpu_paused(int cpu)
|
||||
{
|
||||
/* Wait for the spinlock to be released */
|
||||
|
||||
spin_unlock(&g_cpu_paused[cpu]);
|
||||
|
||||
/* Ensure the CPU has been resumed to avoid causing a deadlock */
|
||||
|
||||
spin_lock(&g_cpu_resumed[cpu]);
|
||||
|
||||
spin_lock(&g_cpu_wait[cpu]);
|
||||
|
||||
spin_unlock(&g_cpu_wait[cpu]);
|
||||
spin_unlock(&g_cpu_resumed[cpu]);
|
||||
|
||||
return OK;
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: up_cpu_paused_restore
|
||||
*
|
||||
* Description:
|
||||
* Restore the state of the CPU after it was paused via up_cpu_pause(),
|
||||
* and resume normal tasking.
|
||||
*
|
||||
* Input Parameters:
|
||||
* None
|
||||
*
|
||||
* Returned Value:
|
||||
* On success, OK is returned. Otherwise, a negated errno value indicating
|
||||
* the nature of the failure is returned.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
int up_cpu_paused_restore(void)
|
||||
{
|
||||
struct tcb_s *tcb = this_task();
|
||||
|
||||
#ifdef CONFIG_SCHED_INSTRUMENTATION
|
||||
/* Notify that we have resumed */
|
||||
|
||||
sched_note_cpu_resumed(tcb);
|
||||
#endif
|
||||
|
||||
/* Reset scheduler parameters */
|
||||
|
||||
nxsched_resume_scheduler(tcb);
|
||||
|
||||
/* Then switch contexts. Any necessary address environment changes
|
||||
* will be made when the interrupt returns.
|
||||
*/
|
||||
|
||||
arm_restorestate(tcb->xcp.regs);
|
||||
|
||||
return OK;
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: arm_pause_handler
|
||||
*
|
||||
* Description:
|
||||
* Inter-CPU interrupt handler
|
||||
*
|
||||
* Input Parameters:
|
||||
* Standard interrupt handler inputs
|
||||
*
|
||||
* Returned Value:
|
||||
* Should always return OK
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
int arm_pause_handler(int irq, void *c, void *arg)
|
||||
{
|
||||
int cpu = up_cpu_index();
|
||||
int irqreq;
|
||||
uint32_t stat;
|
||||
|
||||
stat = getreg32(RP23XX_SIO_FIFO_ST);
|
||||
if (stat & (RP23XX_SIO_FIFO_ST_ROE | RP23XX_SIO_FIFO_ST_WOF))
|
||||
{
|
||||
/* Clear sticky flag */
|
||||
|
||||
putreg32(0, RP23XX_SIO_FIFO_ST);
|
||||
}
|
||||
|
||||
if (!(stat & RP23XX_SIO_FIFO_ST_VLD))
|
||||
{
|
||||
/* No data received */
|
||||
|
||||
return OK;
|
||||
}
|
||||
|
||||
irqreq = getreg32(RP23XX_SIO_FIFO_RD);
|
||||
|
||||
if (irqreq != 0)
|
||||
{
|
||||
/* Handle IRQ enable/disable request */
|
||||
|
||||
rp23xx_handle_irqreq(irqreq);
|
||||
return OK;
|
||||
}
|
||||
|
||||
DPRINTF("cpu%d will be paused\n", cpu);
|
||||
|
||||
/* Check for false alarms. Such false could occur as a consequence of
|
||||
* some deadlock breaking logic that might have already serviced the SG2
|
||||
* interrupt by calling up_cpu_paused.
|
||||
*/
|
||||
|
||||
if (up_cpu_pausereq(cpu))
|
||||
{
|
||||
/* NOTE: The following enter_critical_section() will call
|
||||
* up_cpu_paused() to process a pause request to break a deadlock
|
||||
* because the caller held a critical section. Once up_cpu_paused()
|
||||
* finished, the caller will proceed and release the g_cpu_irqlock.
|
||||
* Then this CPU will acquire g_cpu_irqlock in the function.
|
||||
*/
|
||||
|
||||
irqstate_t flags = enter_critical_section();
|
||||
|
||||
/* NOTE: the pause request should not exist here */
|
||||
|
||||
DEBUGVERIFY(!up_cpu_pausereq(cpu));
|
||||
|
||||
leave_critical_section(flags);
|
||||
}
|
||||
|
||||
return OK;
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: up_cpu_pause
|
||||
*
|
||||
* Description:
|
||||
* Save the state of the current task at the head of the
|
||||
* g_assignedtasks[cpu] task list and then pause task execution on the
|
||||
* CPU.
|
||||
*
|
||||
* This function is called by the OS when the logic executing on one CPU
|
||||
* needs to modify the state of the g_assignedtasks[cpu] list for another
|
||||
* CPU.
|
||||
*
|
||||
* Input Parameters:
|
||||
* cpu - The index of the CPU to be stopped/
|
||||
*
|
||||
* Returned Value:
|
||||
* Zero on success; a negated errno value on failure.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
int up_cpu_pause(int cpu)
|
||||
{
|
||||
DPRINTF("cpu=%d\n", cpu);
|
||||
|
||||
DEBUGASSERT(cpu >= 0 && cpu < CONFIG_SMP_NCPUS && cpu != this_cpu());
|
||||
|
||||
#ifdef CONFIG_SCHED_INSTRUMENTATION
|
||||
/* Notify of the pause event */
|
||||
|
||||
sched_note_cpu_pause(this_task(), cpu);
|
||||
#endif
|
||||
|
||||
/* Take the both spinlocks. The g_cpu_wait spinlock will prevent the SGI2
|
||||
* handler from returning until up_cpu_resume() is called; g_cpu_paused
|
||||
* is a handshake that will prefent this function from returning until
|
||||
* the CPU is actually paused.
|
||||
* Note that we might spin before getting g_cpu_wait, this just means that
|
||||
* the other CPU still hasn't finished responding to the previous resume
|
||||
* request.
|
||||
*/
|
||||
|
||||
DEBUGASSERT(!spin_is_locked(&g_cpu_paused[cpu]));
|
||||
|
||||
spin_lock(&g_cpu_wait[cpu]);
|
||||
spin_lock(&g_cpu_paused[cpu]);
|
||||
|
||||
DEBUGASSERT(cpu != up_cpu_index());
|
||||
|
||||
/* Generate IRQ for CPU(cpu) */
|
||||
|
||||
while (!(getreg32(RP23XX_SIO_FIFO_ST) & RP23XX_SIO_FIFO_ST_RDY))
|
||||
;
|
||||
putreg32(0, RP23XX_SIO_FIFO_WR);
|
||||
|
||||
/* Wait for the other CPU to unlock g_cpu_paused meaning that
|
||||
* it is fully paused and ready for up_cpu_resume();
|
||||
*/
|
||||
|
||||
spin_lock(&g_cpu_paused[cpu]);
|
||||
spin_unlock(&g_cpu_paused[cpu]);
|
||||
|
||||
/* On successful return g_cpu_wait will be locked, the other CPU will be
|
||||
* spinning on g_cpu_wait and will not continue until g_cpu_resume() is
|
||||
* called. g_cpu_paused will be unlocked in any case.
|
||||
*/
|
||||
|
||||
return OK;
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: up_cpu_resume
|
||||
*
|
||||
* Description:
|
||||
* Restart the cpu after it was paused via up_cpu_pause(), restoring the
|
||||
* state of the task at the head of the g_assignedtasks[cpu] list, and
|
||||
* resume normal tasking.
|
||||
*
|
||||
* This function is called after up_cpu_pause in order resume operation of
|
||||
* the CPU after modifying its g_assignedtasks[cpu] list.
|
||||
*
|
||||
* Input Parameters:
|
||||
* cpu - The index of the CPU being re-started.
|
||||
*
|
||||
* Returned Value:
|
||||
* Zero on success; a negated errno value on failure.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
int up_cpu_resume(int cpu)
|
||||
{
|
||||
DPRINTF("cpu=%d\n", cpu);
|
||||
|
||||
DEBUGASSERT(cpu >= 0 && cpu < CONFIG_SMP_NCPUS && cpu != this_cpu());
|
||||
|
||||
#ifdef CONFIG_SCHED_INSTRUMENTATION
|
||||
/* Notify of the resume event */
|
||||
|
||||
sched_note_cpu_resume(this_task(), cpu);
|
||||
#endif
|
||||
|
||||
/* Release the spinlock. Releasing the spinlock will cause the SGI2
|
||||
* handler on 'cpu' to continue and return from interrupt to the newly
|
||||
* established thread.
|
||||
*/
|
||||
|
||||
DEBUGASSERT(spin_is_locked(&g_cpu_wait[cpu]) &&
|
||||
!spin_is_locked(&g_cpu_paused[cpu]));
|
||||
|
||||
spin_unlock(&g_cpu_wait[cpu]);
|
||||
|
||||
/* Ensure the CPU has been resumed to avoid causing a deadlock */
|
||||
|
||||
spin_lock(&g_cpu_resumed[cpu]);
|
||||
|
||||
spin_unlock(&g_cpu_resumed[cpu]);
|
||||
return OK;
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: rp23xx_send_irqreq()
|
||||
*
|
||||
* Description:
|
||||
* Send up_enable_irq() / up_disable_irq() request to the Core #0
|
||||
*
|
||||
* This function is called from up_enable_irq() or up_disable_irq()
|
||||
* to be handled on specified CPU. Locking protocol in the sequence is
|
||||
* the same as up_pause_cpu() plus up_resume_cpu().
|
||||
*
|
||||
* Input Parameters:
|
||||
* irqreq - The IRQ number to be handled (>0 : enable / <0 : disable)
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void rp23xx_send_irqreq(int irqreq)
|
||||
{
|
||||
/* Wait for the spinlocks to be released */
|
||||
|
||||
spin_lock(&g_cpu_wait[0]);
|
||||
spin_lock(&g_cpu_paused[0]);
|
||||
|
||||
/* Send IRQ number to Core #0 */
|
||||
|
||||
while (!(getreg32(RP23XX_SIO_FIFO_ST) & RP23XX_SIO_FIFO_ST_RDY))
|
||||
;
|
||||
putreg32(irqreq, RP23XX_SIO_FIFO_WR);
|
||||
|
||||
/* Wait for the handler is executed on cpu */
|
||||
|
||||
spin_lock(&g_cpu_paused[0]);
|
||||
spin_unlock(&g_cpu_paused[0]);
|
||||
|
||||
/* Finally unlock the spinlock to proceed the handler */
|
||||
|
||||
spin_unlock(&g_cpu_wait[0]);
|
||||
|
||||
/* Ensure the CPU has been resumed to avoid causing a deadlock */
|
||||
|
||||
spin_lock(&g_cpu_resumed[0]);
|
||||
|
||||
spin_unlock(&g_cpu_resumed[0]);
|
||||
}
|
||||
|
||||
#endif /* CONFIG_SMP */
|
||||
|
|
@ -67,7 +67,7 @@
|
|||
|
||||
volatile static spinlock_t g_core1_boot;
|
||||
|
||||
extern int arm_pause_handler(int irq, void *c, void *arg);
|
||||
extern int rp23xx_smp_call_handler(int irq, void *c, void *arg);
|
||||
|
||||
/****************************************************************************
|
||||
* Private Functions
|
||||
|
|
@ -151,8 +151,8 @@ static void core1_boot(void)
|
|||
|
||||
/* Enable inter-processor FIFO interrupt */
|
||||
|
||||
irq_attach(RP23XX_SIO_IRQ_PROC1, arm_pause_handler, NULL);
|
||||
up_enable_irq(RP23XX_SIO_IRQ_PROC1);
|
||||
irq_attach(RP23XX_SIO_IRQ_FIFO, rp23xx_smp_call_handler, NULL);
|
||||
up_enable_irq(RP23XX_SIO_IRQ_FIFO);
|
||||
|
||||
spin_unlock(&g_core1_boot);
|
||||
|
||||
|
|
@ -225,7 +225,7 @@ int up_cpu_start(int cpu)
|
|||
|
||||
core1_boot_msg[0] = 0;
|
||||
core1_boot_msg[1] = 1;
|
||||
core1_boot_msg[2] = getreg32(ARMV6M_SYSCON_VECTAB);
|
||||
core1_boot_msg[2] = getreg32(NVIC_VECTAB);
|
||||
core1_boot_msg[3] = (uint32_t)tcb->stack_base_ptr +
|
||||
tcb->adj_stack_size;
|
||||
core1_boot_msg[4] = (uint32_t)core1_boot;
|
||||
|
|
@ -247,8 +247,8 @@ int up_cpu_start(int cpu)
|
|||
|
||||
/* Enable inter-processor FIFO interrupt */
|
||||
|
||||
irq_attach(RP23XX_SIO_IRQ_PROC0, arm_pause_handler, NULL);
|
||||
up_enable_irq(RP23XX_SIO_IRQ_PROC0);
|
||||
irq_attach(RP23XX_SIO_IRQ_FIFO, rp23xx_smp_call_handler, NULL);
|
||||
up_enable_irq(RP23XX_SIO_IRQ_FIFO);
|
||||
|
||||
spin_lock(&g_core1_boot);
|
||||
|
||||
|
|
|
|||
|
|
@ -107,7 +107,7 @@ static const int g_gpio_function_mapping_i2c[2][9] =
|
|||
{
|
||||
0, 4, 8, 12, 16, 20, 24, 28,
|
||||
#ifdef CONFIG_RP23XX_RP2350B
|
||||
32, 36, 40, 44,
|
||||
32, 36, 40, 44,
|
||||
#endif
|
||||
-1
|
||||
}, /* pin numbers assignable to I2C0 */
|
||||
|
|
|
|||
|
|
@ -36,7 +36,7 @@
|
|||
****************************************************************************/
|
||||
|
||||
static void * const psram_start = (void *)0x11000000ul;
|
||||
static const size_t psram_size = 8*1024*1024;
|
||||
static const size_t psram_size = 8 * 1024 * 1024;
|
||||
|
||||
/****************************************************************************
|
||||
* Public Functions
|
||||
|
|
@ -68,7 +68,8 @@ void arm_addregion(void)
|
|||
|
||||
/* Use the internal SRAM as the kernel heap */
|
||||
|
||||
void up_allocate_kheap(void **heap_start, size_t *heap_size) {
|
||||
void up_allocate_kheap(void **heap_start, size_t *heap_size)
|
||||
{
|
||||
*heap_start = (void *)g_idle_topstack;
|
||||
|
||||
#ifdef CONFIG_ARCH_PGPOOL_PBASE
|
||||
|
|
@ -78,9 +79,10 @@ void up_allocate_kheap(void **heap_start, size_t *heap_size) {
|
|||
#endif
|
||||
}
|
||||
|
||||
/* Use the external PSRAM as the default user heap*/
|
||||
/* Use the external PSRAM as the default user heap */
|
||||
|
||||
void up_allocate_heap(void **heap_start, size_t *heap_size) {
|
||||
void up_allocate_heap(void **heap_start, size_t *heap_size)
|
||||
{
|
||||
*heap_start = psram_start;
|
||||
*heap_size = psram_size;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -108,14 +108,20 @@ static void rp23xx_dumpnvic(const char *msg, int irq)
|
|||
getreg32(NVIC_IRQ0_3_PRIORITY), getreg32(NVIC_IRQ4_7_PRIORITY),
|
||||
getreg32(NVIC_IRQ8_11_PRIORITY), getreg32(NVIC_IRQ12_15_PRIORITY));
|
||||
irqinfo(" %08x %08x %08x %08x\n",
|
||||
getreg32(NVIC_IRQ16_19_PRIORITY), getreg32(NVIC_IRQ20_23_PRIORITY),
|
||||
getreg32(NVIC_IRQ24_27_PRIORITY), getreg32(NVIC_IRQ28_31_PRIORITY));
|
||||
getreg32(NVIC_IRQ16_19_PRIORITY),
|
||||
getreg32(NVIC_IRQ20_23_PRIORITY),
|
||||
getreg32(NVIC_IRQ24_27_PRIORITY),
|
||||
getreg32(NVIC_IRQ28_31_PRIORITY));
|
||||
irqinfo(" %08x %08x %08x %08x\n",
|
||||
getreg32(NVIC_IRQ32_35_PRIORITY), getreg32(NVIC_IRQ36_39_PRIORITY),
|
||||
getreg32(NVIC_IRQ40_43_PRIORITY), getreg32(NVIC_IRQ44_47_PRIORITY));
|
||||
getreg32(NVIC_IRQ32_35_PRIORITY),
|
||||
getreg32(NVIC_IRQ36_39_PRIORITY),
|
||||
getreg32(NVIC_IRQ40_43_PRIORITY),
|
||||
getreg32(NVIC_IRQ44_47_PRIORITY));
|
||||
irqinfo(" %08x %08x %08x %08x\n",
|
||||
getreg32(NVIC_IRQ48_51_PRIORITY), getreg32(NVIC_IRQ52_55_PRIORITY),
|
||||
getreg32(NVIC_IRQ56_59_PRIORITY), getreg32(NVIC_IRQ60_63_PRIORITY));
|
||||
getreg32(NVIC_IRQ48_51_PRIORITY),
|
||||
getreg32(NVIC_IRQ52_55_PRIORITY),
|
||||
getreg32(NVIC_IRQ56_59_PRIORITY),
|
||||
getreg32(NVIC_IRQ60_63_PRIORITY));
|
||||
|
||||
irqinfo("SYSCON:\n");
|
||||
irqinfo(" CPUID: %08x\n",
|
||||
|
|
@ -203,7 +209,8 @@ static inline void rp23xx_clrpend(int irq)
|
|||
}
|
||||
else
|
||||
{
|
||||
putreg32((1 << (irq - RP23XX_IRQ_EXTINT - 32)), NVIC_IRQ32_63_CLRPEND);
|
||||
putreg32((1 << (irq - RP23XX_IRQ_EXTINT - 32)),
|
||||
NVIC_IRQ32_63_CLRPEND);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
@ -321,7 +328,8 @@ void up_disable_irq(int irq)
|
|||
}
|
||||
else
|
||||
{
|
||||
putreg32((1 << (irq - RP23XX_IRQ_EXTINT - 32)), NVIC_IRQ32_63_CLEAR);
|
||||
putreg32((1 << (irq - RP23XX_IRQ_EXTINT - 32)),
|
||||
NVIC_IRQ32_63_CLEAR);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -376,7 +384,8 @@ void up_enable_irq(int irq)
|
|||
}
|
||||
else
|
||||
{
|
||||
putreg32((1 << (irq - RP23XX_IRQ_EXTINT - 32)), NVIC_IRQ32_63_ENABLE);
|
||||
putreg32((1 << (irq - RP23XX_IRQ_EXTINT - 32)),
|
||||
NVIC_IRQ32_63_ENABLE);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -294,7 +294,8 @@ inline static uint32_t pio_encode_irq_set(bool relative, uint32_t irq)
|
|||
_pio_encode_irq(relative, irq));
|
||||
}
|
||||
|
||||
inline static uint32_t pio_encode_irq_wait(bool relative, uint32_t irq) {
|
||||
inline static uint32_t pio_encode_irq_wait(bool relative, uint32_t irq)
|
||||
{
|
||||
return _pio_encode_instr_and_args(pio_instr_bits_irq, 1,
|
||||
_pio_encode_irq(relative, irq));
|
||||
}
|
||||
|
|
|
|||
|
|
@ -29,9 +29,9 @@
|
|||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
// ROM FUNCTIONS
|
||||
/* ROM FUNCTIONS */
|
||||
|
||||
// RP2040 & RP2350
|
||||
/* RP2040 & RP2350 */
|
||||
#define ROM_DATA_SOFTWARE_GIT_REVISION ROM_TABLE_CODE('G', 'R')
|
||||
#define ROM_FUNC_FLASH_ENTER_CMD_XIP ROM_TABLE_CODE('C', 'X')
|
||||
#define ROM_FUNC_FLASH_EXIT_XIP ROM_TABLE_CODE('E', 'X')
|
||||
|
|
@ -40,7 +40,7 @@
|
|||
#define ROM_FUNC_FLASH_RANGE_ERASE ROM_TABLE_CODE('R', 'E')
|
||||
#define ROM_FUNC_FLASH_RANGE_PROGRAM ROM_TABLE_CODE('R', 'P')
|
||||
|
||||
// RP2350 only
|
||||
/* RP2350 only */
|
||||
#define ROM_FUNC_PICK_AB_PARTITION ROM_TABLE_CODE('A', 'B')
|
||||
#define ROM_FUNC_CHAIN_IMAGE ROM_TABLE_CODE('C', 'I')
|
||||
#define ROM_FUNC_EXPLICIT_BUY ROM_TABLE_CODE('E', 'B')
|
||||
|
|
@ -65,15 +65,15 @@
|
|||
#define ROM_FUNC_FLASH_SELECT_XIP_READ_MODE ROM_TABLE_CODE('X', 'M')
|
||||
#define ROM_FUNC_VALIDATE_NS_BUFFER ROM_TABLE_CODE('V', 'B')
|
||||
|
||||
// these form a bit set
|
||||
/* these form a bit set */
|
||||
#define BOOTROM_STATE_RESET_CURRENT_CORE 0x01
|
||||
#define BOOTROM_STATE_RESET_OTHER_CORE 0x02
|
||||
#define BOOTROM_STATE_RESET_GLOBAL_STATE 0x04 // reset any global state (e.g. permissions)
|
||||
#define BOOTROM_STATE_RESET_GLOBAL_STATE 0x04 /* reset any global state (e.g. permissions) */
|
||||
|
||||
#define RT_FLAG_FUNC_RISCV 0x0001
|
||||
#define RT_FLAG_FUNC_RISCV_FAR 0x0003
|
||||
#define RT_FLAG_FUNC_ARM_SEC 0x0004
|
||||
// reserved for 32-bit pointer: 0x0008
|
||||
/* reserved for 32-bit pointer: 0x0008 */
|
||||
#define RT_FLAG_FUNC_ARM_NONSEC 0x0010
|
||||
|
||||
#define BOOTROM_FUNC_TABLE_OFFSET 0x14
|
||||
|
|
@ -90,15 +90,6 @@
|
|||
#define BOOTROM_TABLE_LOOKUP_OFFSET (BOOTROM_FUNC_TABLE_OFFSET + BOOTROM_WELL_KNOWN_PTR_SIZE)
|
||||
#endif
|
||||
|
||||
/*! \brief Return a bootrom lookup code based on two ASCII characters
|
||||
* \ingroup pico_bootrom
|
||||
*
|
||||
* These codes are uses to lookup data or function addresses in the bootrom
|
||||
*
|
||||
* \param c1 the first character
|
||||
* \param c2 the second character
|
||||
* \return the 'code' to use in rom_func_lookup() or rom_data_lookup()
|
||||
*/
|
||||
#define ROM_TABLE_CODE(c1, c2) ((c1) | ((c2) << 8))
|
||||
|
||||
/****************************************************************************
|
||||
|
|
@ -107,19 +98,30 @@
|
|||
|
||||
typedef void *(*rom_table_lookup_fn)(uint32_t code, uint32_t mask);
|
||||
|
||||
static __inline void *rom_func_lookup(uint32_t code) {
|
||||
static __inline void *rom_func_lookup(uint32_t code)
|
||||
{
|
||||
#ifdef __riscv
|
||||
uint32_t rom_offset_adjust = rom_size_is_64k() ? 32 * 1024 : 0;
|
||||
// on RISC-V the code (a jmp) is actually embedded in the table
|
||||
rom_table_lookup_fn rom_table_lookup = (rom_table_lookup_fn) (uintptr_t)*(uint16_t*)(BOOTROM_TABLE_LOOKUP_ENTRY_OFFSET + rom_offset_adjust);
|
||||
|
||||
/* on RISC-V the code (a jmp) is actually embedded in the table */
|
||||
|
||||
rom_table_lookup_fn rom_table_lookup = (rom_table_lookup_fn) (uintptr_t)
|
||||
*(uint16_t *)(BOOTROM_TABLE_LOOKUP_ENTRY_OFFSET + rom_offset_adjust);
|
||||
|
||||
return rom_table_lookup(code, RT_FLAG_FUNC_RISCV);
|
||||
#else
|
||||
// on ARM the function pointer is stored in the table, so we dereference it
|
||||
// via lookup() rather than lookup_entry()
|
||||
rom_table_lookup_fn rom_table_lookup = (rom_table_lookup_fn) (uintptr_t)*(uint16_t*)(BOOTROM_TABLE_LOOKUP_OFFSET);
|
||||
if (pico_processor_state_is_nonsecure()) {
|
||||
/* on ARM the function pointer is stored in the table, so we dereference
|
||||
* it via lookup() rather than lookup_entry()
|
||||
*/
|
||||
|
||||
rom_table_lookup_fn rom_table_lookup = (rom_table_lookup_fn) (uintptr_t)
|
||||
*(uint16_t *)(BOOTROM_TABLE_LOOKUP_OFFSET);
|
||||
if (pico_processor_state_is_nonsecure())
|
||||
{
|
||||
return rom_table_lookup(code, RT_FLAG_FUNC_ARM_NONSEC);
|
||||
} else {
|
||||
}
|
||||
else
|
||||
{
|
||||
return rom_table_lookup(code, RT_FLAG_FUNC_ARM_SEC);
|
||||
}
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -1015,7 +1015,7 @@ void arm_serialinit(void)
|
|||
*
|
||||
****************************************************************************/
|
||||
|
||||
int up_putc(int ch)
|
||||
void up_putc(int ch)
|
||||
{
|
||||
#ifdef HAVE_CONSOLE
|
||||
struct up_dev_s *priv = (struct up_dev_s *)CONSOLE_DEV.priv;
|
||||
|
|
@ -1036,8 +1036,6 @@ int up_putc(int ch)
|
|||
#ifdef HAVE_CONSOLE
|
||||
up_restoreuartint(priv, ier);
|
||||
#endif
|
||||
|
||||
return ch;
|
||||
}
|
||||
|
||||
#else /* USE_SERIALDRIVER */
|
||||
|
|
@ -1050,7 +1048,7 @@ int up_putc(int ch)
|
|||
*
|
||||
****************************************************************************/
|
||||
|
||||
int up_putc(int ch)
|
||||
void up_putc(int ch)
|
||||
{
|
||||
#ifdef HAVE_UART
|
||||
/* Check for LF */
|
||||
|
|
@ -1064,7 +1062,6 @@ int up_putc(int ch)
|
|||
|
||||
arm_lowputc(ch);
|
||||
#endif
|
||||
return ch;
|
||||
}
|
||||
|
||||
#endif /* USE_SERIALDRIVER */
|
||||
|
|
|
|||
213
arch/arm/src/rp23xx/rp23xx_smpcall.c
Normal file
213
arch/arm/src/rp23xx/rp23xx_smpcall.c
Normal file
|
|
@ -0,0 +1,213 @@
|
|||
/****************************************************************************
|
||||
* arch/arm/src/rp23xx/rp23xx_smpcall.c
|
||||
*
|
||||
* Licensed to the Apache Software Foundation (ASF) under one or more
|
||||
* contributor license agreements. See the NOTICE file distributed with
|
||||
* this work for additional information regarding copyright ownership. The
|
||||
* ASF licenses this file to you under the Apache License, Version 2.0 (the
|
||||
* "License"); you may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
|
||||
* License for the specific language governing permissions and limitations
|
||||
* under the License.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include <stdint.h>
|
||||
#include <assert.h>
|
||||
#include <debug.h>
|
||||
#include <string.h>
|
||||
#include <stdio.h>
|
||||
|
||||
#include <nuttx/arch.h>
|
||||
#include <nuttx/spinlock.h>
|
||||
#include <nuttx/sched_note.h>
|
||||
|
||||
#include "sched/sched.h"
|
||||
#include "arm_internal.h"
|
||||
#include "hardware/rp23xx_sio.h"
|
||||
|
||||
#ifdef CONFIG_SMP
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
#if 0
|
||||
#define DPRINTF(fmt, args...) llinfo(fmt, ##args)
|
||||
#else
|
||||
#define DPRINTF(fmt, args...) do {} while (0)
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Name: rp23xx_handle_irqreq
|
||||
*
|
||||
* Description:
|
||||
* If an irq handling request is found on cpu, call up_enable_irq() or
|
||||
* up_disable_irq().
|
||||
*
|
||||
* Input Parameters:
|
||||
* irqreq - The IRQ number to be handled (>0 : enable / <0 : disable)
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
static void rp23xx_handle_irqreq(int irqreq)
|
||||
{
|
||||
DEBUGASSERT(this_cpu() == 0);
|
||||
|
||||
if (irqreq > 0)
|
||||
{
|
||||
up_enable_irq(irqreq);
|
||||
}
|
||||
else
|
||||
{
|
||||
up_disable_irq(-irqreq);
|
||||
}
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Public Functions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: rp23xx_smp_call_handler
|
||||
*
|
||||
* Description:
|
||||
* This is the handler for SMP_CALL.
|
||||
*
|
||||
* Returned Value:
|
||||
* Should always return OK
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
int rp23xx_smp_call_handler(int irq, void *c, void *arg)
|
||||
{
|
||||
int cpu = this_cpu();
|
||||
int irqreq;
|
||||
uint32_t stat;
|
||||
|
||||
nxsched_smp_call_handler(irq, c, arg);
|
||||
|
||||
stat = getreg32(RP23XX_SIO_FIFO_ST);
|
||||
if (stat & (RP23XX_SIO_FIFO_ST_ROE | RP23XX_SIO_FIFO_ST_WOF))
|
||||
{
|
||||
/* Clear sticky flag */
|
||||
|
||||
putreg32(0, RP23XX_SIO_FIFO_ST);
|
||||
}
|
||||
|
||||
if (!(stat & RP23XX_SIO_FIFO_ST_VLD))
|
||||
{
|
||||
/* No data received */
|
||||
|
||||
return OK;
|
||||
}
|
||||
|
||||
irqreq = getreg32(RP23XX_SIO_FIFO_RD);
|
||||
|
||||
if (irqreq != 0)
|
||||
{
|
||||
/* Handle IRQ enable/disable request */
|
||||
|
||||
rp23xx_handle_irqreq(irqreq);
|
||||
return OK;
|
||||
}
|
||||
|
||||
DPRINTF("cpu%d will be paused\n", cpu);
|
||||
|
||||
nxsched_process_delivered(cpu);
|
||||
|
||||
return OK;
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: up_send_smp_sched
|
||||
*
|
||||
* Description:
|
||||
* pause task execution on the CPU
|
||||
* check whether there are tasks delivered to specified cpu
|
||||
* and try to run them.
|
||||
*
|
||||
* Input Parameters:
|
||||
* cpu - The index of the CPU to be paused.
|
||||
*
|
||||
* Returned Value:
|
||||
* Zero on success; a negated errno value on failure.
|
||||
*
|
||||
* Assumptions:
|
||||
* Called from within a critical section;
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
int up_send_smp_sched(int cpu)
|
||||
{
|
||||
/* Generate IRQ for CPU(cpu) */
|
||||
|
||||
while (!(getreg32(RP23XX_SIO_FIFO_ST) & RP23XX_SIO_FIFO_ST_RDY))
|
||||
;
|
||||
putreg32(0, RP23XX_SIO_FIFO_WR);
|
||||
|
||||
return OK;
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: up_send_smp_call
|
||||
*
|
||||
* Description:
|
||||
* Send smp call to target cpu.
|
||||
*
|
||||
* Input Parameters:
|
||||
* cpuset - The set of CPUs to receive the SGI.
|
||||
*
|
||||
* Returned Value:
|
||||
* None.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void up_send_smp_call(cpu_set_t cpuset)
|
||||
{
|
||||
int cpu;
|
||||
|
||||
for (; cpuset != 0; cpuset &= ~(1 << cpu))
|
||||
{
|
||||
cpu = ffs(cpuset) - 1;
|
||||
up_send_smp_sched(cpu);
|
||||
}
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: rp23xx_send_irqreq()
|
||||
*
|
||||
* Description:
|
||||
* Send up_enable_irq() / up_disable_irq() request to the Core #0
|
||||
*
|
||||
* This function is called from up_enable_irq() or up_disable_irq()
|
||||
* to be handled on specified CPU. Locking protocol in the sequence is
|
||||
* the same as up_pause_cpu() plus up_resume_cpu().
|
||||
*
|
||||
* Input Parameters:
|
||||
* irqreq - The IRQ number to be handled (>0 : enable / <0 : disable)
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void rp23xx_send_irqreq(int irqreq)
|
||||
{
|
||||
/* Send IRQ number to Core #0 */
|
||||
|
||||
while (!(getreg32(RP23XX_SIO_FIFO_ST) & RP23XX_SIO_FIFO_ST_RDY))
|
||||
;
|
||||
putreg32(irqreq, RP23XX_SIO_FIFO_WR);
|
||||
}
|
||||
|
||||
#endif /* CONFIG_SMP */
|
||||
|
|
@ -91,7 +91,7 @@ void __start(void)
|
|||
|
||||
__asm__ __volatile__ ("\tmsr msp, %0\n" :: "r" (g_idle_topstack));
|
||||
|
||||
if (up_cpu_index() != 0)
|
||||
if (this_cpu() != 0)
|
||||
{
|
||||
while (1)
|
||||
{
|
||||
|
|
@ -108,6 +108,11 @@ void __start(void)
|
|||
*dest++ = 0;
|
||||
}
|
||||
|
||||
/* Set up clock */
|
||||
|
||||
rp23xx_clockconfig();
|
||||
rp23xx_boardearlyinitialize();
|
||||
|
||||
/* Initialize all spinlock states */
|
||||
|
||||
for (i = 0; i < 32; i++)
|
||||
|
|
@ -115,6 +120,11 @@ void __start(void)
|
|||
putreg32(0, RP23XX_SIO_SPINLOCK(i));
|
||||
}
|
||||
|
||||
/* Configure the uart so that we can get debug output as soon as possible */
|
||||
|
||||
rp23xx_lowsetup();
|
||||
showprogress('A');
|
||||
|
||||
/* Move the initialized data section from its temporary holding spot in
|
||||
* FLASH into the correct place in SRAM. The correct place in SRAM is
|
||||
* give by _sdata and _edata. The temporary location is in FLASH at the
|
||||
|
|
@ -130,16 +140,6 @@ void __start(void)
|
|||
}
|
||||
#endif
|
||||
|
||||
/* Set up clock */
|
||||
|
||||
rp23xx_clockconfig();
|
||||
rp23xx_boardearlyinitialize();
|
||||
|
||||
/* Configure the uart so that we can get debug output as soon as possible */
|
||||
|
||||
rp23xx_lowsetup();
|
||||
showprogress('A');
|
||||
|
||||
showprogress('B');
|
||||
|
||||
/* Perform early serial initialization */
|
||||
|
|
|
|||
1
boards/arm/rp23xx/common/.gitignore
vendored
Normal file
1
boards/arm/rp23xx/common/.gitignore
vendored
Normal file
|
|
@ -0,0 +1 @@
|
|||
etctmp*
|
||||
|
|
@ -74,10 +74,6 @@ int rp23xx_common_bringup(void)
|
|||
{
|
||||
int ret = 0;
|
||||
|
||||
#ifdef CONFIG_RP23XX_FLASH_FILE_SYSTEM
|
||||
struct mtd_dev_s *mtd_dev;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_RP23XX_I2C_DRIVER
|
||||
#ifdef CONFIG_RP23XX_I2C0
|
||||
ret = board_i2cdev_initialize(0);
|
||||
|
|
|
|||
|
|
@ -33,8 +33,6 @@
|
|||
#include "rp23xx_uniqueid.h"
|
||||
#include "rp23xx_rom.h"
|
||||
|
||||
// #include "pico/bootrom_constants.h"
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
|
@ -45,6 +43,9 @@
|
|||
* Private Types
|
||||
****************************************************************************/
|
||||
|
||||
typedef int (*rom_get_sys_info_fn)
|
||||
(uint32_t *out_buffer, uint32_t out_buffer_word_size, uint32_t flags);
|
||||
|
||||
/****************************************************************************
|
||||
* Private Function Prototypes
|
||||
****************************************************************************/
|
||||
|
|
@ -85,9 +86,8 @@ void rp23xx_uniqueid_initialize(void)
|
|||
{
|
||||
uint64_t x;
|
||||
|
||||
typedef int (*rom_get_sys_info_fn)(uint32_t *out_buffer, uint32_t out_buffer_word_size, uint32_t flags);
|
||||
|
||||
rom_get_sys_info_fn func = (rom_get_sys_info_fn) rom_func_lookup(ROM_FUNC_GET_SYS_INFO);
|
||||
rom_get_sys_info_fn func = (rom_get_sys_info_fn)
|
||||
rom_func_lookup(ROM_FUNC_GET_SYS_INFO);
|
||||
|
||||
union
|
||||
{
|
||||
|
|
@ -95,7 +95,7 @@ void rp23xx_uniqueid_initialize(void)
|
|||
uint8_t bytes[9 * 4];
|
||||
} out;
|
||||
|
||||
memset(out.bytes, 0x00, 9*4);
|
||||
memset(out.bytes, 0x00, 9 * 4);
|
||||
|
||||
int rc = func(out.words, 9, SYS_INFO_CHIP_INFO);
|
||||
|
||||
|
|
|
|||
|
|
@ -11,7 +11,6 @@
|
|||
# CONFIG_NSH_CMDOPT_HEXDUMP is not set
|
||||
# CONFIG_NSH_DISABLE_DATE is not set
|
||||
# CONFIG_NSH_DISABLE_LOSMART is not set
|
||||
# CONFIG_RP23XX_FLASH_BOOT is not set
|
||||
# CONFIG_STANDARD_SERIAL is not set
|
||||
CONFIG_ARCH="arm"
|
||||
CONFIG_ARCH_BOARD="raspberrypi-pico-2"
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/****************************************************************************
|
||||
* boards/arm/rp23xx/raspberrypi-pico-2/include/board.h
|
||||
* boards/arm/rp23xx/pimoroni-pico-2-plus/include/board.h
|
||||
*
|
||||
* Licensed to the Apache Software Foundation (ASF) under one or more
|
||||
* contributor license agreements. See the NOTICE file distributed with
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/****************************************************************************
|
||||
* boards/arm/rp23xx/raspberrypi-pico-2/include/rp23xx_i2cdev.h
|
||||
* boards/arm/rp23xx/pimoroni-pico-2-plus/include/rp23xx_i2cdev.h
|
||||
*
|
||||
* Licensed to the Apache Software Foundation (ASF) under one or more
|
||||
* contributor license agreements. See the NOTICE file distributed with
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/****************************************************************************
|
||||
* boards/arm/rp23xx/raspberrypi-pico-2/include/rp23xx_i2sdev.h
|
||||
* boards/arm/rp23xx/pimoroni-pico-2-plus/include/rp23xx_i2sdev.h
|
||||
*
|
||||
* Licensed to the Apache Software Foundation (ASF) under one or more
|
||||
* contributor license agreements. See the NOTICE file distributed with
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/****************************************************************************
|
||||
* boards/arm/rp23xx/raspberrypi-pico-2/include/rp23xx_spidev.h
|
||||
* boards/arm/rp23xx/pimoroni-pico-2-plus/include/rp23xx_spidev.h
|
||||
*
|
||||
* Licensed to the Apache Software Foundation (ASF) under one or more
|
||||
* contributor license agreements. See the NOTICE file distributed with
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
############################################################################
|
||||
# boards/arm/rp23xx/raspberrypi-pico-2/scripts/Make.defs
|
||||
# boards/arm/rp23xx/pimoroni-pico-2-plus/scripts/Make.defs
|
||||
#
|
||||
# Licensed to the Apache Software Foundation (ASF) under one or more
|
||||
# contributor license agreements. See the NOTICE file distributed with
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
############################################################################
|
||||
# boards/arm/rp23xx/raspberrypi-pico-2/src/Make.defs
|
||||
# boards/arm/rp23xx/pimoroni-pico-2-plus/src/Make.defs
|
||||
#
|
||||
# Licensed to the Apache Software Foundation (ASF) under one or more
|
||||
# contributor license agreements. See the NOTICE file distributed with
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/****************************************************************************
|
||||
* boards/arm/rp23xx/raspberrypi-pico-2/src/rp23xx_appinit.c
|
||||
* boards/arm/rp23xx/pimoroni-pico-2-plus/src/rp23xx_appinit.c
|
||||
*
|
||||
* Licensed to the Apache Software Foundation (ASF) under one or more
|
||||
* contributor license agreements. See the NOTICE file distributed with
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/****************************************************************************
|
||||
* boards/arm/rp23xx/raspberrypi-pico-2/src/rp23xx_autoleds.c
|
||||
* boards/arm/rp23xx/pimoroni-pico-2-plus/src/rp23xx_autoleds.c
|
||||
*
|
||||
* Licensed to the Apache Software Foundation (ASF) under one or more
|
||||
* contributor license agreements. See the NOTICE file distributed with
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/****************************************************************************
|
||||
* boards/arm/rp23xx/raspberrypi-pico-2/src/rp23xx_boardinitialize.c
|
||||
* boards/arm/rp23xx/pimoroni-pico-2-plus/src/rp23xx_boardinitialize.c
|
||||
*
|
||||
* Licensed to the Apache Software Foundation (ASF) under one or more
|
||||
* contributor license agreements. See the NOTICE file distributed with
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/****************************************************************************
|
||||
* boards/arm/rp23xx/raspberrypi-pico-2/src/rp23xx_bringup.c
|
||||
* boards/arm/rp23xx/pimoroni-pico-2-plus/src/rp23xx_bringup.c
|
||||
*
|
||||
* Licensed to the Apache Software Foundation (ASF) under one or more
|
||||
* contributor license agreements. See the NOTICE file distributed with
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/****************************************************************************
|
||||
* boards/arm/rp23xx/raspberrypi-pico-2/src/rp23xx_buttons.c
|
||||
* boards/arm/rp23xx/pimoroni-pico-2-plus/src/rp23xx_buttons.c
|
||||
*
|
||||
* Licensed to the Apache Software Foundation (ASF) under one or more
|
||||
* contributor license agreements. See the NOTICE file distributed with
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/****************************************************************************
|
||||
* boards/arm/rp23xx/raspberrypi-pico-2/src/rp23xx_gpio.c
|
||||
* boards/arm/rp23xx/pimoroni-pico-2-plus/src/rp23xx_gpio.c
|
||||
*
|
||||
* Licensed to the Apache Software Foundation (ASF) under one or more
|
||||
* contributor license agreements. See the NOTICE file distributed with
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/****************************************************************************
|
||||
* boards/arm/rp23xx/raspberrypi-pico-2/src/rp23xx_pico.h
|
||||
* boards/arm/rp23xx/pimoroni-pico-2-plus/src/rp23xx_pico.h
|
||||
*
|
||||
* Licensed to the Apache Software Foundation (ASF) under one or more
|
||||
* contributor license agreements. See the NOTICE file distributed with
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/****************************************************************************
|
||||
* boards/arm/rp23xx/raspberrypi-pico-2/src/rp23xx_userleds.c
|
||||
* boards/arm/rp23xx/pimoroni-pico-2-plus/src/rp23xx_userleds.c
|
||||
*
|
||||
* Licensed to the Apache Software Foundation (ASF) under one or more
|
||||
* contributor license agreements. See the NOTICE file distributed with
|
||||
|
|
|
|||
|
|
@ -9,24 +9,43 @@
|
|||
# CONFIG_NSH_ARGCAT is not set
|
||||
# CONFIG_NSH_CMDOPT_HEXDUMP is not set
|
||||
# CONFIG_NSH_DISABLE_DATE is not set
|
||||
# CONFIG_NSH_DISABLE_LOSMART is not set
|
||||
# CONFIG_SPI_CALLBACK is not set
|
||||
# CONFIG_STANDARD_SERIAL is not set
|
||||
CONFIG_ARCH="arm"
|
||||
CONFIG_ARCH_BOARD="raspberrypi-pico-2"
|
||||
CONFIG_ARCH_BOARD_RASPBERRYPI_PICO_2=y
|
||||
CONFIG_ARCH_CHIP="rp23xx"
|
||||
CONFIG_ARCH_CHIP_RP23XX=y
|
||||
CONFIG_ARCH_INTERRUPTSTACK=2048
|
||||
CONFIG_ARCH_RAMVECTORS=y
|
||||
CONFIG_ARCH_STACKDUMP=y
|
||||
CONFIG_AUDIO=y
|
||||
CONFIG_AUDIO_I2S=y
|
||||
CONFIG_BOARDCTL_RESET=y
|
||||
CONFIG_BOARD_LOOPSPERMSEC=10450
|
||||
CONFIG_BUILTIN=y
|
||||
CONFIG_DEBUG_FULLOPT=y
|
||||
CONFIG_DEBUG_SYMBOLS=y
|
||||
CONFIG_DISABLE_POSIX_TIMERS=y
|
||||
CONFIG_DRIVERS_AUDIO=y
|
||||
CONFIG_ETC_ROMFS=y
|
||||
CONFIG_EXAMPLES_HELLO=y
|
||||
CONFIG_EXAMPLES_WS2812=y
|
||||
CONFIG_FAT_LFN=y
|
||||
CONFIG_FSUTILS_MKGPT=y
|
||||
CONFIG_FSUTILS_MKMBR=y
|
||||
CONFIG_FS_FAT=y
|
||||
CONFIG_FS_FATTIME=y
|
||||
CONFIG_FS_PROCFS=y
|
||||
CONFIG_FS_PROCFS_REGISTER=y
|
||||
CONFIG_FS_ROMFS=y
|
||||
CONFIG_FS_TMPFS=y
|
||||
CONFIG_INIT_ENTRYPOINT="nsh_main"
|
||||
CONFIG_LIBC_LZF=y
|
||||
CONFIG_LIBC_MEMFD_ERROR=y
|
||||
CONFIG_MMCSD=y
|
||||
CONFIG_MMCSD_PROCFS=y
|
||||
CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6
|
||||
CONFIG_NSH_ARCHINIT=y
|
||||
CONFIG_NSH_BUILTIN_APPS=y
|
||||
|
|
@ -34,16 +53,31 @@ CONFIG_NSH_READLINE=y
|
|||
CONFIG_RAM_SIZE=532480
|
||||
CONFIG_RAM_START=0x20000000
|
||||
CONFIG_READLINE_CMD_HISTORY=y
|
||||
CONFIG_RP23XX_FLASH_FILE_SYSTEM=y
|
||||
CONFIG_RP23XX_BOARD_HAS_WS2812=y
|
||||
CONFIG_RP23XX_I2S=y
|
||||
CONFIG_RP23XX_SPI0=y
|
||||
CONFIG_RP23XX_SPI0_CS_GPIO=5
|
||||
CONFIG_RP23XX_SPI0_RX_GPIO=4
|
||||
CONFIG_RP23XX_SPI0_SCK_GPIO=2
|
||||
CONFIG_RP23XX_SPI0_TX_GPIO=3
|
||||
CONFIG_RP23XX_SPI=y
|
||||
CONFIG_RP23XX_SPISD=y
|
||||
CONFIG_RP23XX_WS2812_GPIO_PIN=6
|
||||
CONFIG_RR_INTERVAL=200
|
||||
CONFIG_SCHED_HPWORK=y
|
||||
CONFIG_SCHED_LPWORK=y
|
||||
CONFIG_SCHED_WAITPID=y
|
||||
CONFIG_SMARTFS_ALIGNED_ACCESS=y
|
||||
CONFIG_SMP=y
|
||||
CONFIG_SMP_NCPUS=2
|
||||
CONFIG_START_DAY=9
|
||||
CONFIG_START_MONTH=2
|
||||
CONFIG_START_YEAR=2021
|
||||
CONFIG_SYSLOG_CONSOLE=y
|
||||
CONFIG_SYSTEM_NSH=y
|
||||
CONFIG_SYSTEM_NXLOOPER=y
|
||||
CONFIG_SYSTEM_NXPLAYER=y
|
||||
CONFIG_SYSTEM_NXRECORDER=y
|
||||
CONFIG_TESTING_GETPRIME=y
|
||||
CONFIG_TESTING_OSTEST=y
|
||||
CONFIG_TESTING_SMART_TEST=y
|
||||
CONFIG_UART0_SERIAL_CONSOLE=y
|
||||
CONFIG_WS2812=y
|
||||
|
|
@ -38,6 +38,10 @@ ifeq ($(CONFIG_ARCH_BUTTONS),y)
|
|||
CSRCS += rp23xx_buttons.c
|
||||
endif
|
||||
|
||||
ifeq ($(CONFIG_ETC_ROMFS),y)
|
||||
RCSRCS = etc/init.d/rc.sysinit etc/init.d/rcS
|
||||
endif
|
||||
|
||||
DEPPATH += --dep-path board
|
||||
VPATH += :board
|
||||
CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board
|
||||
|
|
|
|||
|
|
@ -0,0 +1,23 @@
|
|||
/****************************************************************************
|
||||
* boards/arm/rp23xx/raspberrypi-pico-2/src/etc/init.d/rc.sysinit
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed to the Apache Software Foundation (ASF) under one or more
|
||||
* contributor license agreements. See the NOTICE file distributed with
|
||||
* this work for additional information regarding copyright ownership. The
|
||||
* ASF licenses this file to you under the Apache License, Version 2.0 (the
|
||||
* "License"); you may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
|
||||
* License for the specific language governing permissions and limitations
|
||||
* under the License.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
24
boards/arm/rp23xx/raspberrypi-pico-2/src/etc/init.d/rcS
Normal file
24
boards/arm/rp23xx/raspberrypi-pico-2/src/etc/init.d/rcS
Normal file
|
|
@ -0,0 +1,24 @@
|
|||
/****************************************************************************
|
||||
* boards/arm/rp23xx/raspberrypi-pico-2/src/etc/init.d/rcS
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed to the Apache Software Foundation (ASF) under one or more
|
||||
* contributor license agreements. See the NOTICE file distributed with
|
||||
* this work for additional information regarding copyright ownership. The
|
||||
* ASF licenses this file to you under the Apache License, Version 2.0 (the
|
||||
* "License"); you may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
|
||||
* License for the specific language governing permissions and limitations
|
||||
* under the License.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
|
|
@ -24,10 +24,33 @@
|
|||
|
||||
# POSTBUILD -- Perform post build operations
|
||||
|
||||
ifeq ($(CONFIG_RP23XX_UF2_BINARY),y)
|
||||
define POSTBUILD
|
||||
PICOTOOL_BIN_PATH?=$(PICO_SDK_PATH)$(DELIM)_deps$(DELIM)picotool$(DELIM)picotool
|
||||
|
||||
define GEN_PICO_UF2
|
||||
$(Q)echo "Generating: nuttx.uf2"; \
|
||||
picotool uf2 convert nuttx -t elf nuttx.uf2
|
||||
|
||||
$(Q)$1 uf2 convert --quiet -t elf nuttx nuttx.uf2;
|
||||
$(Q)([ $$? -eq 0 ] && echo nuttx.uf2 >> nuttx.manifest && echo "Done.")
|
||||
endef
|
||||
|
||||
ifeq ($(CONFIG_RP23XX_UF2_BINARY),y)
|
||||
ifneq ($(shell which picotool),)
|
||||
define POSTBUILD
|
||||
$(call GEN_PICO_UF2, picotool)
|
||||
endef
|
||||
else ifdef PICO_SDK_PATH
|
||||
define POSTBUILD
|
||||
$(Q)(if ! $(PICOTOOL_BIN_PATH) help >&/dev/null; then \
|
||||
echo "Building: picotool"; \
|
||||
cd $(PICO_SDK_PATH); \
|
||||
cmake . >&/dev/null; \
|
||||
make picotoolBuild >&/dev/null; \
|
||||
fi;)
|
||||
$(call GEN_PICO_UF2, $(PICOTOOL_BIN_PATH))
|
||||
endef
|
||||
else
|
||||
define POSTBUILD
|
||||
$(Q) echo "PICO_SDK_PATH/picotool must be specified/installed for flash boot"
|
||||
endef
|
||||
endif
|
||||
endif
|
||||
|
|
|
|||
Loading…
Reference in a new issue