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https://github.com/lupyuen/pinephone-nuttx.git
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Adding annotations
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parent
ff7cd79e79
commit
88221bffe8
2 changed files with 103 additions and 43 deletions
139
display.zig
139
display.zig
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@ -1067,17 +1067,18 @@ pub export fn enable_dsi_block() void {
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debug("Set Pixel Format", .{});
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const DSI_PIXEL_PH_REG = DSI_BASE_ADDRESS + 0x90;
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comptime{ assert(DSI_PIXEL_PH_REG == 0x1ca0090); }
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const ECC: u32 = 19 << 24;
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const WC: u24 = 2160 << 8;
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const VC: u8 = 0 << 6;
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const DT: u6 = 0x3E << 0;
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const DSI_PIXEL_PH = ECC
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| WC
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| VC
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| DT;
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comptime{ assert(DSI_PIXEL_PH == 0x1308703e); }
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putreg32(DSI_PIXEL_PH, DSI_PIXEL_PH_REG); // TODO: DMB
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{
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const ECC: u32 = 19 << 24;
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const WC: u24 = 2160 << 8;
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const VC: u8 = 0 << 6;
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const DT: u6 = 0x3E << 0;
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const DSI_PIXEL_PH = ECC
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| WC
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| VC
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| DT;
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comptime{ assert(DSI_PIXEL_PH == 0x1308703e); }
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putreg32(DSI_PIXEL_PH, DSI_PIXEL_PH_REG); // TODO: DMB
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}
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// DSI_PIXEL_PF0_REG: DSI Offset 0x98 (A31 Page 849)
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// Set CRC_Force (Bits 0 to 15) to 0xffff (Force CRC to this value)
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@ -1123,8 +1124,6 @@ pub export fn enable_dsi_block() void {
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comptime{ assert(DSI_BASIC_CTL_REG == 0x1ca000c); }
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putreg32(0x0, DSI_BASIC_CTL_REG); // TODO: DMB
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////////////////////////////////////////////////////////////////////////////
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// DSI_SYNC_HSS_REG: DSI Offset 0xb0 (A31 Page 850)
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// Set ECC (Bits 24 to 31) to 0x12
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// Set D1 (Bits 16 to 23) to 0
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@ -1133,10 +1132,20 @@ pub export fn enable_dsi_block() void {
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// Set DT (Bits 0 to 5) to 0x21 (HSS)
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const DSI_SYNC_HSS_REG = DSI_BASE_ADDRESS + 0xb0;
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comptime{ assert(DSI_SYNC_HSS_REG == 0x1ca00b0); }
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const DSI_SYNC_HSS = 0x12000021;
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comptime{ assert(DSI_SYNC_HSS == 0x12000021); }
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putreg32(DSI_SYNC_HSS, DSI_SYNC_HSS_REG); // TODO: DMB
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{
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const ECC: u32 = 0x12 << 24;
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const D1: u24 = 0 << 16;
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const D0: u16 = 0 << 8;
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const VC: u8 = 0 << 6;
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const DT: u6 = 0x21 << 0;
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const DSI_SYNC_HSS = ECC
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| D1
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| D0
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| VC
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| DT;
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comptime{ assert(DSI_SYNC_HSS == 0x12000021); }
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putreg32(DSI_SYNC_HSS, DSI_SYNC_HSS_REG); // TODO: DMB
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}
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// DSI_SYNC_HSE_REG: DSI Offset 0xb4 (A31 Page 850)
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// Set ECC (Bits 24 to 31) to 1
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@ -1146,10 +1155,20 @@ pub export fn enable_dsi_block() void {
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// Set DT (Bits 0 to 5) to 0x31 (HSE)
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const DSI_SYNC_HSE_REG = DSI_BASE_ADDRESS + 0xb4;
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comptime{ assert(DSI_SYNC_HSE_REG == 0x1ca00b4); }
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const DSI_SYNC_HSE = 0x1000031;
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comptime{ assert(DSI_SYNC_HSE == 0x1000031); }
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putreg32(DSI_SYNC_HSE, DSI_SYNC_HSE_REG); // TODO: DMB
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{
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const ECC: u32 = 1 << 24;
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const D1: u24 = 0 << 16;
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const D0: u16 = 0 << 8;
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const VC: u8 = 0 << 6;
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const DT: u6 = 0x31 << 0;
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const DSI_SYNC_HSE = ECC
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| D1
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| D0
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| VC
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| DT;
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comptime{ assert(DSI_SYNC_HSE == 0x1000031); }
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putreg32(DSI_SYNC_HSE, DSI_SYNC_HSE_REG); // TODO: DMB
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}
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// DSI_SYNC_VSS_REG: DSI Offset 0xb8 (A31 Page 851)
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// Set ECC (Bits 24 to 31) to 7
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@ -1159,10 +1178,20 @@ pub export fn enable_dsi_block() void {
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// Set DT (Bits 0 to 5) to 1 (VSS)
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const DSI_SYNC_VSS_REG = DSI_BASE_ADDRESS + 0xb8;
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comptime{ assert(DSI_SYNC_VSS_REG == 0x1ca00b8); }
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const DSI_SYNC_VSS = 0x7000001;
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comptime{ assert(DSI_SYNC_VSS == 0x7000001); }
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putreg32(DSI_SYNC_VSS, DSI_SYNC_VSS_REG); // TODO: DMB
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{
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const ECC: u32 = 7 << 24;
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const D1: u24 = 0 << 16;
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const D0: u16 = 0 << 8;
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const VC: u8 = 0 << 6;
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const DT: u6 = 1 << 0;
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const DSI_SYNC_VSS = ECC
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| D1
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| D0
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| VC
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| DT;
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comptime{ assert(DSI_SYNC_VSS == 0x7000001); }
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putreg32(DSI_SYNC_VSS, DSI_SYNC_VSS_REG); // TODO: DMB
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}
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// DSI_SYNC_VSE_REG: DSI Offset 0xbc (A31 Page 851)
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// Set ECC (Bits 24 to 31) to 0x14
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@ -1172,10 +1201,20 @@ pub export fn enable_dsi_block() void {
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// Set DT (Bits 0 to 5) to 0x11 (VSE)
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const DSI_SYNC_VSE_REG = DSI_BASE_ADDRESS + 0xbc;
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comptime{ assert(DSI_SYNC_VSE_REG == 0x1ca00bc); }
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const DSI_SYNC_VSE = 0x14000011;
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comptime{ assert(DSI_SYNC_VSE == 0x14000011); }
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putreg32(DSI_SYNC_VSE, DSI_SYNC_VSE_REG); // TODO: DMB
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{
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const ECC: u32 = 0x14 << 24;
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const D1: u24 = 0 << 16;
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const D0: u16 = 0 << 8;
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const VC: u8 = 0 << 6;
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const DT: u6 = 0x11 << 0;
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const DSI_SYNC_VSE = ECC
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| D1
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| D0
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| VC
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| DT;
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comptime{ assert(DSI_SYNC_VSE == 0x14000011); }
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putreg32(DSI_SYNC_VSE, DSI_SYNC_VSE_REG); // TODO: DMB
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}
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// Set Basic Size (Undocumented)
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// DSI_BASIC_SIZE0_REG: DSI Offset 0x18
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@ -1185,7 +1224,10 @@ pub export fn enable_dsi_block() void {
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const DSI_BASIC_SIZE0_REG = DSI_BASE_ADDRESS + 0x18;
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comptime{ assert(DSI_BASIC_SIZE0_REG == 0x1ca0018); }
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const DSI_BASIC_SIZE0 = 0x11000a;
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const Video_VBP: u28 = 17 << 16;
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const Video_VSA: u12 = 10 << 0;
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const DSI_BASIC_SIZE0 = Video_VBP
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| Video_VSA;
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comptime{ assert(DSI_BASIC_SIZE0 == 0x11000a); }
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putreg32(DSI_BASIC_SIZE0, DSI_BASIC_SIZE0_REG); // TODO: DMB
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@ -1195,7 +1237,10 @@ pub export fn enable_dsi_block() void {
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const DSI_BASIC_SIZE1_REG = DSI_BASE_ADDRESS + 0x1c;
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comptime{ assert(DSI_BASIC_SIZE1_REG == 0x1ca001c); }
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const DSI_BASIC_SIZE1 = 0x5cd05a0;
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const Video_VT: u28 = 1485 << 16;
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const Video_VACT: u12 = 1440 << 0;
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const DSI_BASIC_SIZE1 = Video_VT
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| Video_VACT;
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comptime{ assert(DSI_BASIC_SIZE1 == 0x5cd05a0); }
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putreg32(DSI_BASIC_SIZE1, DSI_BASIC_SIZE1_REG); // TODO: DMB
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@ -1205,9 +1250,7 @@ pub export fn enable_dsi_block() void {
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debug("Set Horizontal Blanking", .{});
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const DSI_BLK_HSA0_REG = DSI_BASE_ADDRESS + 0xc0;
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comptime{ assert(DSI_BLK_HSA0_REG == 0x1ca00c0); }
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const DSI_BLK_HSA0 = 0x9004a19;
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comptime{ assert(DSI_BLK_HSA0 == 0x9004a19); }
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putreg32(DSI_BLK_HSA0, DSI_BLK_HSA0_REG); // TODO: DMB
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// DSI_BLK_HSA1_REG: DSI Offset 0xc4 (A31 Page 852)
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@ -1216,7 +1259,10 @@ pub export fn enable_dsi_block() void {
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const DSI_BLK_HSA1_REG = DSI_BASE_ADDRESS + 0xc4;
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comptime{ assert(DSI_BLK_HSA1_REG == 0x1ca00c4); }
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const DSI_BLK_HSA1 = 0x50b40000;
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const HSA_PF: u32 = 0x50b4 << 16;
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const HSA_PD: u8 = 0 << 0;
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const DSI_BLK_HSA1 = HSA_PF
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| HSA_PD;
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comptime{ assert(DSI_BLK_HSA1 == 0x50b40000); }
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putreg32(DSI_BLK_HSA1, DSI_BLK_HSA1_REG); // TODO: DMB
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@ -1224,10 +1270,7 @@ pub export fn enable_dsi_block() void {
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// Set HBP_PH (Bits 0 to 31) to 0x3500 5419
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const DSI_BLK_HBP0_REG = DSI_BASE_ADDRESS + 0xc8;
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comptime{ assert(DSI_BLK_HBP0_REG == 0x1ca00c8); }
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const DSI_BLK_HBP0 = 0x35005419;
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comptime{ assert(DSI_BLK_HBP0 == 0x35005419); }
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putreg32(DSI_BLK_HBP0, DSI_BLK_HBP0_REG); // TODO: DMB
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putreg32(0x35005419, DSI_BLK_HBP0_REG); // TODO: DMB
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// DSI_BLK_HBP1_REG: DSI Offset 0xcc (A31 Page 852)
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// Set HBP_PF (Bits 16 to 31) to 0x757a
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@ -1235,7 +1278,10 @@ pub export fn enable_dsi_block() void {
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const DSI_BLK_HBP1_REG = DSI_BASE_ADDRESS + 0xcc;
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comptime{ assert(DSI_BLK_HBP1_REG == 0x1ca00cc); }
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const DSI_BLK_HBP1 = 0x757a0000;
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const HBP_PF: u32 = 0x757a << 16;
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const HBP_PD: u8 = 0 << 0;
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const DSI_BLK_HBP1 = HBP_PF
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| HBP_PD;
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comptime{ assert(DSI_BLK_HBP1 == 0x757a0000); }
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putreg32(DSI_BLK_HBP1, DSI_BLK_HBP1_REG); // TODO: DMB
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@ -1251,7 +1297,10 @@ pub export fn enable_dsi_block() void {
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const DSI_BLK_HFP1_REG = DSI_BASE_ADDRESS + 0xd4;
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comptime{ assert(DSI_BLK_HFP1_REG == 0x1ca00d4); }
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const DSI_BLK_HFP1 = 0x50b40000;
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const HFP_PF: u32 = 0x50b4 << 16;
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const HFP_PD: u8 = 0 << 0;
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const DSI_BLK_HFP1 = HFP_PF
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| HFP_PD;
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comptime{ assert(DSI_BLK_HFP1 == 0x50b40000); }
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putreg32(DSI_BLK_HFP1, DSI_BLK_HFP1_REG); // TODO: DMB
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@ -1267,7 +1316,10 @@ pub export fn enable_dsi_block() void {
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const DSI_BLK_HBLK1_REG = DSI_BASE_ADDRESS + 0xe4;
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comptime{ assert(DSI_BLK_HBLK1_REG == 0x1ca00e4); }
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const DSI_BLK_HBLK1 = 0x72bd0000;
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const HBLK_PF: u32 = 0x72bd << 16;
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const HBLK_PD: u8 = 0 << 0;
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const DSI_BLK_HBLK1 = HBLK_PF
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| HBLK_PD;
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comptime{ assert(DSI_BLK_HBLK1 == 0x72bd0000); }
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putreg32(DSI_BLK_HBLK1, DSI_BLK_HBLK1_REG); // TODO: DMB
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@ -1285,7 +1337,10 @@ pub export fn enable_dsi_block() void {
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const DSI_BLK_VBLK1_REG = DSI_BASE_ADDRESS + 0xec;
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comptime{ assert(DSI_BLK_VBLK1_REG == 0x1ca00ec); }
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const DSI_BLK_VBLK1 = 0xffff0000;
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const VBLK_PF: u32 = 0xffff << 16;
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const VBLK_PD: u8 = 0 << 0;
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const DSI_BLK_VBLK1 = VBLK_PF
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| VBLK_PD;
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comptime{ assert(DSI_BLK_VBLK1 == 0xffff0000); }
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putreg32(DSI_BLK_VBLK1, DSI_BLK_VBLK1_REG); // TODO: DMB
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}
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7
dphy.zig
7
dphy.zig
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@ -62,7 +62,12 @@ pub export fn dphy_enable() void {
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const MIPI_DSI_CLK_REG = CCU_BASE_ADDRESS + 0x168;
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comptime{ assert(MIPI_DSI_CLK_REG == 0x1c20168); }
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const MIPI_DSI_CLK = 0x8203;
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const DSI_DPHY_GATING: u16 = 1 << 15;
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const DSI_DPHY_SRC_SEL: u10 = 0b10 << 8;
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const DPHY_CLK_DIV_M: u4 = 3 << 0;
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const MIPI_DSI_CLK = DSI_DPHY_GATING
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| DSI_DPHY_SRC_SEL
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| DPHY_CLK_DIV_M;
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comptime{ assert(MIPI_DSI_CLK == 0x8203); }
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putreg32(MIPI_DSI_CLK, MIPI_DSI_CLK_REG); // TODO: DMB
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