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Add device tree
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307
README.md
307
README.md
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@ -22,7 +22,17 @@ PinePhone is based on [Allwinner A64 SoC](https://linux-sunxi.org/A64) with 4 Co
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- [PinePhone Wiki](https://wiki.pine64.org/index.php/PinePhone)
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Will NuttX run on PinePhone? Let's find out!
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_Will NuttX run on PinePhone?_
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Yep it does! PinePhone (with a Serial Debug Cable) boots to the NuttX Shell...
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- [Watch the Demo on YouTube](https://youtube.com/shorts/WmRzfCiWV6o?feature=share)
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Here's the NuttX Source Code for PinePhone...
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- NuttX OS: [lupyuen/incubator-nuttx/tree/pinephone](https://github.com/lupyuen/incubator-nuttx/tree/pinephone)
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- NuttX Apps: [lupyuen/incubator-nuttx-apps/tree/pinephone](https://github.com/lupyuen/incubator-nuttx-apps/tree/pinephone)
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_Why NuttX?_
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@ -32,8 +42,12 @@ Someday we might have a cheap, fast, responsive and tweakable phone running on N
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Many thanks to [qinwei2004](https://github.com/qinwei2004) and the NuttX Team for implementing [Cortex-A53 support](https://github.com/apache/incubator-nuttx/pull/6478)!
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The following is a journal that documents the porting of NuttX to PinePhone. It looks super messy and unstructured, please read the articles (at the top of this page) instead.
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# Download NuttX
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We start with NuttX Mainline, run it on QEMU, then mod it for PinePhone.
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Download the Source Code for NuttX Mainline, which supports Arm Cortex-A53...
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```bash
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@ -2274,7 +2288,7 @@ Previously we noticed that NuttX Shell wasn't generating output on the Serial Co
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We discovered that `sinfo` (`syslog`) works, but `printf` (`puts`) doesn't!
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https://github.com/lupyuen/incubator-nuttx-apps/blob/pinephone/system/nsh/nsh_main.c#L88-L102
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Here's what we tested with NuttX Shell: [system/nsh/nsh_main.c](https://github.com/lupyuen/incubator-nuttx-apps/blob/pinephone/system/nsh/nsh_main.c#L88-L102)
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```c
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/****************************************************************************
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@ -2326,285 +2340,26 @@ We need to implement UART Transmit and Receive Interrupts to support NuttX Shell
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Here's our implementation...
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TODO: Constants
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- ["NuttX RTOS on PinePhone: UART Driver"](https://lupyuen.github.io/articles/serial)
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https://github.com/lupyuen/incubator-nuttx/blob/pinephone/arch/arm64/src/qemu/qemu_serial.c#L60-L64
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# PinePhone Device Tree
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```c
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// UART0 IRQ Number for PinePhone Allwinner A64 UART
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#define UART_IRQ 32
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Below is the Device Tree for PinePhone's Linux Kernel. We'll use this to figure out how Allwinner A64's Display Timing Controller (TCON0) talks to PinePhone's MIPI DSI Display...
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// UART0 Base Address for PinePhone Allwinner A64 UART
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#define UART_BASE_ADDRESS 0x01C28000
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- [PinePhone Device Tree: sun50i-a64-pinephone-1.2.dts](sun50i-a64-pinephone-1.2.dts)
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We converted the Device Tree with this command...
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```
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## Convert Device Tree to text format
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dtc \
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-o sun50i-a64-pinephone-1.2.dts \
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-O dts \
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-I dtb \
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sun50i-a64-pinephone-1.2.dtb
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```
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TODO: `qemu_pl011_txready`
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https://github.com/lupyuen/incubator-nuttx/blob/pinephone/arch/arm64/src/qemu/qemu_serial.c#L405-L414
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```c
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// Return true if PinePhone Allwinner A64 UART Transmit FIFO is not full
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static bool qemu_pl011_txready(struct uart_dev_s *dev)
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{
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//up_putc('C');////
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// LSR is at Offset 0x14
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const uint8_t *uart_lsr = (const uint8_t *) (UART_BASE_ADDRESS + 0x14);
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// Transmit FIFO is ready if THRE=1 (bit 5 of LSR)
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return (*uart_lsr & 0x20) != 0;
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}
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```
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TODO: `qemu_pl011_txempty`
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https://github.com/lupyuen/incubator-nuttx/blob/pinephone/arch/arm64/src/qemu/qemu_serial.c#L434-L439
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```c
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// Return true if PinePhone Allwinner A64 UART Transmit FIFO is empty
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static bool qemu_pl011_txempty(struct uart_dev_s *dev)
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{
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//up_putc('D');////
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return qemu_pl011_txready(dev);
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}
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```
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TODO: `qemu_pl011_send`
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https://github.com/lupyuen/incubator-nuttx/blob/pinephone/arch/arm64/src/qemu/qemu_serial.c#L460-L466
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```c
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// Send one byte to PinePhone Allwinner A64 UART
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static void qemu_pl011_send(struct uart_dev_s *dev, int ch)
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{
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//up_putc('E');////
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uint8_t *uart0_base_address = (uint8_t *) UART_BASE_ADDRESS;
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*uart0_base_address = ch;
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}
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```
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TODO: `qemu_pl011_rxavailable`
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https://github.com/lupyuen/incubator-nuttx/blob/pinephone/arch/arm64/src/qemu/qemu_serial.c#L495-L512
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```c
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// TODO: Return true if PinePhone Allwinner A64 UART Receive FIFO is not empty
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static bool qemu_pl011_rxavailable(struct uart_dev_s *dev)
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{
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//up_putc('F');////
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// UART Line Status Register (UART_LSR)
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// Offset: 0x0014
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const uint8_t *uart_lsr = (const uint8_t *) (UART_BASE_ADDRESS + 0x14);
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// Bit 0: Data Ready (DR)
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// This is used to indicate that the receiver contains at least one character in
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// the RBR or the receiver FIFO.
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// 0: no data ready
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// 1: data ready
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// This bit is cleared when the RBR is read in non-FIFO mode, or when the
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// receiver FIFO is empty, in FIFO mode.
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return (*uart_lsr) & 1; // DR=1 if data is ready
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}
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```
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TODO: `qemu_pl011_rxint`
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https://github.com/lupyuen/incubator-nuttx/blob/pinephone/arch/arm64/src/qemu/qemu_serial.c#L539-L554
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```c
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// TODO: Enable or disable PinePhone Allwinner A64 UART interrupts
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static void qemu_pl011_rxint(struct uart_dev_s *dev, bool enable)
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{
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//up_putc('G');////
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// Write to UART Interrupt Enable Register (UART_IER)
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// Offset: 0x0004
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uint8_t *uart_ier = (uint8_t *) (UART_BASE_ADDRESS + 0x04);
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// Bit 0: Enable Received Data Available Interrupt (ERBFI)
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// This is used to enable/disable the generation of Received Data Available Interrupt and the Character Timeout Interrupt (if in FIFO mode and FIFOs enabled). These are the second highest priority interrupts.
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// 0: Disable
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// 1: Enable
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if (enable) { *uart_ier |= 0b00000001; }
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else { *uart_ier &= 0b11111110; }
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}
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```
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TODO: `qemu_pl011_txint`
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https://github.com/lupyuen/incubator-nuttx/blob/pinephone/arch/arm64/src/qemu/qemu_serial.c#L581-L596
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```c
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// TODO: Enable or disable PinePhone Allwinner A64 UART TX interrupts
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static void qemu_pl011_txint(struct uart_dev_s *dev, bool enable)
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{
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//up_putc('H');////
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// Write to UART Interrupt Enable Register (UART_IER)
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// Offset: 0x0004
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uint8_t *uart_ier = (uint8_t *) (UART_BASE_ADDRESS + 0x04);
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// Bit 1: Enable Transmit Holding Register Empty Interrupt (ETBEI)
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// This is used to enable/disable the generation of Transmitter Holding Register Empty Interrupt. This is the third highest priority interrupt.
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// 0: Disable
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// 1: Enable
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if (enable) { *uart_ier |= 0b00000010; }
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else { *uart_ier &= 0b11111101; }
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}
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```
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TODO: `qemu_pl011_receive`
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https://github.com/lupyuen/incubator-nuttx/blob/pinephone/arch/arm64/src/qemu/qemu_serial.c#L624-L643
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```c
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// TODO: Receive data from PinePhone Allwinner A64 UART
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static int qemu_pl011_receive(struct uart_dev_s *dev, unsigned int *status)
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{
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//up_putc('I');////
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// Read UART Receiver Buffer Register (UART_RBR)
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// Offset: 0x0000
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const uint8_t *uart_rbr = (const uint8_t *) (UART_BASE_ADDRESS + 0x00);
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// Data byte received on the serial input port . The data in this register is
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// valid only if the Data Ready (DR) bit in the UART Line Status Register
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// (UART_LCR) is set.
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//
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// If in FIFO mode and FIFOs are enabled (UART_FCR[0] set to one), this
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// register accesses the head of the receive FIFO. If the receive FIFO is full
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// and this register is not read before the next data character arrives, then
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// the data already in the FIFO is preserved, but any incoming data are lost
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// and an overrun error occurs.
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return *uart_rbr;
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}
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```
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TODO: `qemu_pl011_irq_handler`
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https://github.com/lupyuen/incubator-nuttx/blob/pinephone/arch/arm64/src/qemu/qemu_serial.c#L710-L747
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```c
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// Interrupt Handler for PinePhone Allwinner A64 UART
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static int qemu_pl011_irq_handler(int irq, void *context, void *arg)
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{
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//up_putc('M');////
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struct uart_dev_s *dev = (struct uart_dev_s *)arg;
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UNUSED(irq);
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UNUSED(context);
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DEBUGASSERT(dev != NULL && dev->priv != NULL);
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// Read UART Interrupt Identity Register (UART_IIR)
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// Offset: 0x0008
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const uint8_t *uart_iir = (const uint8_t *) (UART_BASE_ADDRESS + 0x08);
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// Bits 3:0: Interrupt ID
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// This indicates the highest priority pending interrupt which can be one of the following types:
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// 0000: modem status
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// 0001: no interrupt pending
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// 0010: THR empty
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// 0100: received data available
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// 0110: receiver line status
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// 0111: busy detect
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// 1100: character timeout
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// Bit 3 indicates an interrupt can only occur when the FIFOs are enabled and used to distinguish a Character Timeout condition interrupt.
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uint8_t int_id = (*uart_iir) & 0b1111;
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// 0100: If received data is available...
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if (int_id == 0b0100) {
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// Receive the data
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uart_recvchars(dev);
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// 0010: If THR is empty (Transmit Holding Register)...
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} else if (int_id == 0b0010) {
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// Transmit the data
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uart_xmitchars(dev);
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}
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return OK;
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}
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```
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TODO: `qemu_pl011_detach`
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https://github.com/lupyuen/incubator-nuttx/blob/pinephone/arch/arm64/src/qemu/qemu_serial.c#L770-L776
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```c
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// TODO: Detach PinePhone Allwinner A64 UART
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static void qemu_pl011_detach(struct uart_dev_s *dev)
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{
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//up_putc('J');////
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up_disable_irq(UART_IRQ);
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irq_detach(UART_IRQ);
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}
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```
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TODO: `qemu_pl011_attach`
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https://github.com/lupyuen/incubator-nuttx/blob/pinephone/arch/arm64/src/qemu/qemu_serial.c#L827-L852
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```c
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// TODO: Attach PinePhone Allwinner A64 UART
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static int qemu_pl011_attach(struct uart_dev_s *dev)
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{
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//up_putc('K');////
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int ret;
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ret = irq_attach(UART_IRQ, qemu_pl011_irq_handler, dev);
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arm64_gic_irq_set_priority(UART_IRQ, IRQ_TYPE_LEVEL, 0);
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if (ret == OK)
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{
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up_enable_irq(UART_IRQ);
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}
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else
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{
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sinfo("error ret=%d\n", ret);
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}
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#ifdef TODO
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if (!data->sbsa)
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{
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pl011_enable(sport);
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}
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#endif // TODO
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return ret;
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}
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```
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TODO: Interrupt Priority:
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```text
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Interrupt ID
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Priority Level
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Interrupt Type
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Interrupt Source
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Interrupt Reset
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0110 Highest
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Receiver line status
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Overrun/parity/framing errors or break interrupt
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Reading UART Line Status Register
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0100 Second
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Received data available
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Receiver data available (non-FIFO mode or FIFOs disabled) or RCVR FIFO trigger level reached (FIFO mode and FIFOs enabled)
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Reading UART Receiver Buffer Register (non-FIFO mode or FIFOs disabled) or the FIFO drops below the trigger level (FIFO mode and FIFOs enabled)
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1100 Second
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Character timeout indication
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No characters in or out of the RCVR FIFO during the last 4 character times and there is at least 1character in it during This time
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Reading UART Receiver Buffer Register
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0010 Third
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Transmit holding register empty
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Transmitter holding register empty (Program THRE Mode disabled) or XMIT FIFO at or below threshold (Program THRE Mode enabled)
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Reading UART Interrupt Identity Register (if source of interrupt); or, writing into THR (FIFOs or THRE Mode not selected or disabled) or XMIT FIFO above threshold (FIFOs and THRE Mode selected and enabled).
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```
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We got `sun50i-a64-pinephone-1.2.dtb` from the [Jumpdrive microSD](https://lupyuen.github.io/articles/uboot#pinephone-jumpdrive).
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# GIC Register Dump
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2053
sun50i-a64-pinephone-1.2.dts
Normal file
2053
sun50i-a64-pinephone-1.2.dts
Normal file
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