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arch/: Unify the cache interface for all architectures

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This commit is contained in:
Xiang Xiao 2019-03-19 10:37:13 -06:00 committed by Gregory Nutt
parent 2f208fdde8
commit 64252a298f
103 changed files with 2198 additions and 2935 deletions
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8
arch/Kconfig
View file

@ -171,11 +171,15 @@ config ARCH_HAVE_IRQPRIO
bool
default n
config ARCH_L2CACHE
config ARCH_ICACHE
bool
default n
config ARCH_HAVE_COHERENT_DCACHE
config ARCH_DCACHE
bool
default n
config ARCH_L2CACHE
bool
default n

31
arch/arm/Kconfig
View file

@ -405,6 +405,8 @@ endchoice
config ARCH_ARM7TDMI
bool
default n
select ARCH_DCACHE
select ARCH_ICACHE
---help---
The Arm7TDMI-S is an excellent workhorse processor capable of a wide
array of applications. Traditionally used in mobile handsets, the
@ -413,6 +415,8 @@ config ARCH_ARM7TDMI
config ARCH_ARM920T
bool
default n
select ARCH_DCACHE
select ARCH_ICACHE
select ARCH_HAVE_MMU
select ARCH_USE_MMU
---help---
@ -428,6 +432,8 @@ config ARCH_ARM920T
config ARCH_ARM926EJS
bool
default n
select ARCH_DCACHE
select ARCH_ICACHE
select ARCH_HAVE_MMU
select ARCH_USE_MMU
---help---
@ -449,6 +455,8 @@ config ARCH_ARM926EJS
config ARCH_ARM1136J
bool
default n
select ARCH_DCACHE
select ARCH_ICACHE
select ARCH_HAVE_MMU
select ARCH_USE_MMU
---help---
@ -459,6 +467,8 @@ config ARCH_ARM1136J
config ARCH_ARM1156T2
bool
default n
select ARCH_DCACHE
select ARCH_ICACHE
select ARCH_HAVE_MMU
select ARCH_USE_MMU
---help---
@ -468,6 +478,8 @@ config ARCH_ARM1156T2
config ARCH_ARM1176JZ
bool
default n
select ARCH_DCACHE
select ARCH_ICACHE
select ARCH_HAVE_MMU
select ARCH_USE_MMU
---help---
@ -527,54 +539,59 @@ config ARCH_CORTEXM7
select ARCH_HAVE_HIPRI_INTERRUPT
select ARCH_HAVE_RESET
select ARCH_HAVE_TESTSET
select ARCH_HAVE_COHERENT_DCACHE if ELF || MODULE
select ARCH_HAVE_HARDFAULT_DEBUG
select ARCH_HAVE_MEMFAULT_DEBUG
config ARCH_CORTEXA5
bool
default n
select ARCH_DCACHE
select ARCH_ICACHE
select ARCH_HAVE_MMU
select ARCH_USE_MMU
select ARCH_HAVE_TESTSET
select ARCH_HAVE_COHERENT_DCACHE if ELF || MODULE
config ARCH_CORTEXA8
bool
default n
select ARCH_DCACHE
select ARCH_ICACHE
select ARCH_HAVE_MMU
select ARCH_USE_MMU
select ARCH_HAVE_TESTSET
select ARCH_HAVE_COHERENT_DCACHE if ELF || MODULE
config ARCH_CORTEXA9
bool
default n
select ARCH_DCACHE
select ARCH_ICACHE
select ARCH_HAVE_MMU
select ARCH_USE_MMU
select ARCH_HAVE_TESTSET
select ARCH_HAVE_COHERENT_DCACHE if ELF || MODULE
config ARCH_CORTEXR4
bool
default n
select ARCH_DCACHE
select ARCH_ICACHE
select ARCH_HAVE_MPU
select ARCH_HAVE_TESTSET
select ARCH_HAVE_COHERENT_DCACHE if ELF || MODULE
config ARCH_CORTEXR5
bool
default n
select ARCH_DCACHE
select ARCH_ICACHE
select ARCH_HAVE_MPU
select ARCH_HAVE_TESTSET
select ARCH_HAVE_COHERENT_DCACHE if ELF || MODULE
config ARCH_CORTEXR7
bool
default n
select ARCH_DCACHE
select ARCH_ICACHE
select ARCH_HAVE_MPU
select ARCH_HAVE_TESTSET
select ARCH_HAVE_COHERENT_DCACHE if ELF || MODULE
config ARCH_FAMILY
string

6
arch/arm/src/a1x/Make.defs
View file

@ -111,11 +111,7 @@ CMN_CSRCS += arm_virtpgaddr.c
endif
endif
ifeq ($(CONFIG_ELF),y)
CMN_CSRCS += arm_coherent_dcache.c
else ifeq ($(CONFIG_MODULE),y)
CMN_CSRCS += arm_coherent_dcache.c
endif
CMN_CSRCS += arm_cache.c
ifeq ($(CONFIG_ARCH_FPU),y)
CMN_ASRCS += arm_savefpu.S arm_restorefpu.S

6
arch/arm/src/am335x/Make.defs
View file

@ -107,11 +107,7 @@ CMN_CSRCS += arm_virtpgaddr.c
endif
endif
ifeq ($(CONFIG_ELF),y)
CMN_CSRCS += arm_coherent_dcache.c
else ifeq ($(CONFIG_MODULE),y)
CMN_CSRCS += arm_coherent_dcache.c
endif
CMN_CSRCS += arm_cache.c
ifeq ($(CONFIG_ARCH_FPU),y)
CMN_ASRCS += arm_savefpu.S arm_restorefpu.S

4
arch/arm/src/am335x/am335x_boot.c
View file

@ -43,6 +43,7 @@
#include <assert.h>
#include <debug.h>
#include <nuttx/cache.h>
#ifdef CONFIG_PAGING
# include <nuttx/page.h>
#endif
@ -52,7 +53,6 @@
#include "chip.h"
#include "arm.h"
#include "mmu.h"
#include "cache.h"
#include "fpu.h"
#include "up_internal.h"
#include "up_arch.h"
@ -348,7 +348,7 @@ static void am335x_copyvectorblock(void)
#else
/* Flush the DCache to assure that the vector data is in physical RAM */
arch_clean_dcache((uintptr_t)AM335X_VECTOR_VSRAM,
up_clean_dcache((uintptr_t)AM335X_VECTOR_VSRAM,
(uintptr_t)AM335X_VECTOR_VSRAM + am335x_vectorsize());
#endif
}

6
arch/arm/src/arm/arm.h
View file

@ -44,12 +44,6 @@
* Pre-processor Definitions
************************************************************************************/
#undef CONFIG_ALIGNMENT_TRAP
#undef CONFIG_DCACHE_WRITETHROUGH
#undef CONFIG_CACHE_ROUND_ROBIN
#undef CONFIG_DCACHE_DISABLE
#undef CONFIG_ICACHE_DISABLE
/* ARM9EJS **************************************************************************/
/* PSR bits */

78
arch/arm/src/arm/cache.h
View file

@ -1,78 +0,0 @@
/****************************************************************************
* arch/arm/src/arm/cache.h
*
* Copyright (C) 2013 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Several of these cache operations come from Atmel sample code with
* modifications for better integration with NuttX. The Atmel sample code
* has a BSD compatibile license that requires this copyright notice:
*
* Copyright (c) 2008, Atmel Corporation
*
* [Actually, I think that all of the Atmel functions are commented out now]
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the names NuttX nor Atmel nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_ARM_CACHE_H
#define __ARCH_ARM_SRC_ARM_CACHE_H
/****************************************************************************
* Included Files
****************************************************************************/
/****************************************************************************
* Pre-processor Defintiions
****************************************************************************/
/****************************************************************************
* Public Functions
****************************************************************************/
void cp15_flush_idcache(uint32_t start, uint32_t end);
#if 0 /* Not used */
void cp15_invalidate_idcache(void);
void cp15_invalidate_icache(void);
#endif
void cp15_invalidate_dcache(uint32_t start, uint32_t end);
#if 0 /* Not used */
void cp15_invalidate_dcache_all(void);
void cp15_prefetch_icacheline(unsigned int value);
void cp15_testcleaninvalidate_dcache(void);
void cp15_drain_writebuffer(void);
unsigned int cp15_read_dcachelockdown(void);
void cp15_write_dcachelockdown(unsigned int value);
unsigned int cp15_read_icachelockdown(void);
void cp15_write_icachelockdown(unsigned int value);
#endif
#endif /* __ARCH_ARM_SRC_ARM_CACHE_H */

209
arch/arm/src/arm/up_cache.S
View file

@ -41,7 +41,7 @@
*
****************************************************************************/
.file "up_cp15.S"
.file "up_cache.S"
/****************************************************************************
* Included Files
@ -93,10 +93,10 @@
* the corresponding I-Cache lines.
*/
.globl cp15_flush_idcache
.type cp15_flush_idcache, function
.globl up_coherent_dcache
.type up_coherent_dcache, function
cp15_flush_idcache:
up_coherent_dcache:
bic r0, r0, #CACHE_DLINESIZE - 1
1: mcr p15, 0, r0, c7, c10, 1 /* Clean D entry */
mcr p15, 0, r0, c7, c5, 1 /* Invalidate I entry */
@ -105,34 +105,28 @@ cp15_flush_idcache:
blo 1b
mcr p15, 0, r0, c7, c10, 4 /* Drain WB */
mov pc, lr
.size cp15_flush_idcache, .-cp15_flush_idcache
.size up_coherent_dcache, .-up_coherent_dcache
#if 0 /* Not used */
/* Invalidate all of Icache and Dcache */
/* Invalidate ICache in the region described by r0=start and r1=end. */
.globl cp15_invalidate_idcache
.type cp15_invalidate_idcache, function
.globl up_invalidate_icache
.type up_invalidate_icache, function
cp15_invalidate_idcache:
mov r0, #0
mcr p15, 0, r0, c7, c7, 0
nop
nop
nop
nop
nop
nop
nop
nop
bx lr
.size cp15_invalidate_idcache, . - cp15_invalidate_idcache
up_invalidate_icache:
bic r0, r0, #CACHE_DLINESIZE - 1
1: mcr p15, 0, r0, c7, c5, 1 /* Invalidate I entry */
add r0, r0, #CACHE_DLINESIZE
cmp r0, r1
blo 1b
mov pc, lr
.size up_invalidate_icache, .-up_invalidate_icache
/* Invalidate all of Icache */
.globl cp15_invalidate_icache
.type cp15_invalidate_icache, function
.globl up_invalidate_icache_all
.type up_invalidate_icache_all, function
cp15_invalidate_icache:
up_invalidate_icache_all:
mov r0, #0
mcr p15, 0, r0, c7, c5, 0
nop
@ -144,30 +138,28 @@ cp15_invalidate_icache:
nop
nop
bx lr
.size cp15_invalidate_icache, . - cp15_invalidate_icache
#endif /* Not used */
.size up_invalidate_icache_all, . - up_invalidate_icache_all
/* Invalidate D-Cache in the region described by r0=start and r1=end. */
.globl cp15_invalidate_dcache
.type cp15_invalidate_dcache, function
.globl up_invalidate_dcache
.type up_invalidate_dcache, function
cp15_invalidate_dcache:
up_invalidate_dcache:
bic r0, r0, #CACHE_DLINESIZE - 1
1: mcr p15, 0, r0, c7, c6, 1 /* Invalidate D entry */
add r0, r0, #CACHE_DLINESIZE
cmp r0, r1
blo 1b
mov pc, lr
.size cp15_invalidate_dcache, .-cp15_invalidate_dcache
.size up_invalidate_dcache, .-up_invalidate_dcache
#if 0 /* Not used */
/* Invalidate Dcache */
.globl cp15_invalidate_dcache_all
.type cp15_invalidate_dcache_all, function
.globl up_invalidate_dcache_all
.type up_invalidate_dcache_all, function
cp15_invalidate_dcache_all:
up_invalidate_dcache_all:
mov r0, #0
mcr p15, 0, r0, c7, c6, 0
nop
@ -179,124 +171,59 @@ cp15_invalidate_dcache_all:
nop
nop
bx lr
.size cp15_invalidate_dcache_all, . - cp15_invalidate_dcache_all
.size up_invalidate_dcache_all, . - up_invalidate_dcache_all
/* CP15 Prefetch Icache line c7
* Performs an Icache lookup of the specified modified virtual address.
* If the cache misses, and the region is cacheable, a linefill is performed.
* Prefetch Icache line (MVA): MCR p15, 0, <Rd>, c7, c13, 1
*/
/* Clean D-Cache in the region described by r0=start and r1=end. */
.globl cp15_prefetch_icacheline
.type cp15_prefetch_icacheline, function
.globl up_clean_dcache
.type up_clean_dcache, function
cp15_prefetch_icacheline:
mcr p15, 0, r0, c7, c13, 1
up_clean_dcache:
bic r0, r0, #CACHE_DLINESIZE - 1
1: mcr p15, 0, r0, c7, c10, 1 /* Clean D entry */
add r0, r0, #CACHE_DLINESIZE
cmp r0, r1
blo 1b
mov pc, lr
.size up_clean_dcache, .-up_clean_dcache
/* Clean D-cache */
.globl up_clean_dcache_all
.type up_clean_dcache_all, function
up_clean_dcache_all:
mrc p15, 0, r0, c7, c10, 3
bne up_clean_dcache_all
bx lr
.size cp15_prefetch_icacheline, . - cp15_prefetch_icacheline
.size up_clean_dcache_all, . - up_clean_dcache_all
/* Clean & invalidate D-Cache in the region described by r0=start and r1=end. */
.globl up_flush_dcache
.type up_flush_dcache, function
up_flush_dcache:
bic r0, r0, #CACHE_DLINESIZE - 1
1: mcr p15, 0, r0, c7, c14, 1 /* Clean & invalidate D entry */
add r0, r0, #CACHE_DLINESIZE
cmp r0, r1
blo 1b
mov pc, lr
.size up_flush_dcache, .-up_flush_dcache
/* CP15 Test, clean, and invalidate Dcache c7
* As for test and clean, except that when the entire cache has
* been tested and cleaned, it is invalidated.
*/
.globl cp15_testcleaninvalidate_dcache
.type cp15_testcleaninvalidate_dcache, function
.globl up_flush_dcache_all
.type up_flush_dcache_all, function
cp15_testcleaninvalidate_dcache:
up_flush_dcache_all:
mrc p15, 0, r0, c7, c14, 3
bne cp15_testcleaninvalidate_dcache
bne up_flush_dcache_all
bx lr
.size cp15_testcleaninvalidate_dcache, . - cp15_testcleaninvalidate_dcache
.size up_flush_dcache_all, . - up_flush_dcache_all
/* CP15 Drain write buffer c7
* This instruction acts as an explicit memory barrier. It drains
* the contents of the write buffers of all memory stores
* occurring in program order before this instruction is
* completed. No instructions occurring in program order
* after this instruction are executed until it completes. This
* can be used when timing of specific stores to the level two
* memory system has to be controlled (for example, when a
* store to an interrupt acknowledge location has to complete
* before interrupts are enabled).
*/
.globl cp15_drain_writebuffer
.type cp15_drain_writebuffer, function
cp15_drain_writebuffer:
mov r0, #0
mcr p15, 0, r0, c7, c10, 4
bx lr
.size cp15_drain_writebuffer, . - cp15_drain_writebuffer
/****************************************************************************
* Cache Lockdown
****************************************************************************/
/* Cache Lockdown Register c9
* The Cache Lockdown Register uses a cache-way-based locking scheme (Format C) that
* enables you to control each cache way independently.
* These registers enable you to control which cache ways of the four-way cache are used
* for the allocation on a linefill. When the registers are defined, subsequent linefills are
* only placed in the specified target cache way. This gives you some control over the
* cache pollution caused by particular applications, and provides a traditional lockdown
* operation for locking critical code into the cache.
*
* Read Dcache Lockdown Register MRC p15,0,<Rd>,c9,c0,0
* Write Dcache Lockdown Register MCR p15,0,<Rd>,c9,c0,0
* Read Icache Lockdown Register MRC p15,0,<Rd>,c9,c0,1
* Write Icache Lockdown Register MCR p15,0,<Rd>,c9,c0,1
*/
.globl cp15_read_dcachelockdown
.type cp15_read_dcachelockdown, function
cp15_read_dcachelockdown:
mov r0, #0
mrc p15, 0, r0, c9, c0, 0
bx lr
.size cp15_read_dcachelockdown, . - cp15_read_dcachelockdown
.globl cp15_write_dcachelockdown
.type cp15_write_dcachelockdown, function
cp15_write_dcachelockdown:
mcr p15, 0, r0, c9, c0, 0
nop
nop
nop
nop
nop
nop
nop
nop
bx lr
.size cp15_write_dcachelockdown, . - cp15_write_dcachelockdown
.globl cp15_read_icachelockdown
.type cp15_read_icachelockdown, function
cp15_read_icachelockdown:
mov r0, #0
mrc p15, 0, r0, c9, c0, 1
bx lr
.size cp15_read_icachelockdown, . - cp15_read_icachelockdown
.globl cp15_write_icachelockdown
.type cp15_write_icachelockdown, function
cp15_write_icachelockdown:
mcr p15, 0, r0, c9, c0, 1
nop
nop
nop
nop
nop
nop
nop
nop
bx lr
.size cp15_write_icachelockdown, . - cp15_write_icachelockdown
#endif /* Not used */
.end

11
arch/arm/src/armv7-a/arm_addrenv.c
View file

@ -118,7 +118,6 @@
#include <nuttx/irq.h>
#include "pgalloc.h"
#include "cache.h"
#include "mmu.h"
#include "addrenv.h"
@ -181,7 +180,7 @@ static int up_addrenv_initdata(uintptr_t l2table)
/* Invalidate D-Cache so that we read from the physical memory */
arch_invalidate_dcache((uintptr_t)virtptr,
up_invalidate_dcache((uintptr_t)virtptr,
(uintptr_t)virtptr + sizeof(uint32_t));
/* Get the physical address of the first page of of .bss/.data */
@ -208,7 +207,7 @@ static int up_addrenv_initdata(uintptr_t l2table)
/* Make sure that the initialized data is flushed to physical memory. */
arch_flush_dcache((uintptr_t)virtptr,
up_flush_dcache((uintptr_t)virtptr,
(uintptr_t)virtptr + ARCH_DATA_RESERVE_SIZE);
#ifndef CONFIG_ARCH_PGPOOL_MAPPING
@ -715,17 +714,17 @@ int up_addrenv_coherent(FAR const group_addrenv_t *addrenv)
#warning REVISIT... causes crashes
#if 0
arch_clean_dcache(CONFIG_ARCH_TEXT_VBASE,
up_clean_dcache(CONFIG_ARCH_TEXT_VBASE,
CONFIG_ARCH_TEXT_VBASE +
CONFIG_ARCH_TEXT_NPAGES * MM_PGSIZE - 1);
arch_clean_dcache(CONFIG_ARCH_DATA_VBASE,
up_clean_dcache(CONFIG_ARCH_DATA_VBASE,
CONFIG_ARCH_DATA_VBASE +
CONFIG_ARCH_DATA_NPAGES * MM_PGSIZE - 1);
#endif
#ifdef CONFIG_BUILD_KERNEL
arch_clean_dcache(CONFIG_ARCH_HEAP_VBASE,
up_clean_dcache(CONFIG_ARCH_HEAP_VBASE,
CONFIG_ARCH_HEAP_VBASE + addrenv->heapsize);
#endif

5
arch/arm/src/armv7-a/arm_addrenv_shm.c
View file

@ -49,7 +49,6 @@
#include <nuttx/addrenv.h>
#include "mmu.h"
#include "cache.h"
#include "addrenv.h"
#include "pgalloc.h"
@ -195,7 +194,7 @@ int up_shmat(FAR uintptr_t *pages, unsigned int npages, uintptr_t vaddr)
* flush the entire L2 page table numerous times.
*/
arch_flush_dcache((uintptr_t)l2table,
up_flush_dcache((uintptr_t)l2table,
(uintptr_t)l2table +
ENTRIES_PER_L2TABLE * sizeof(uint32_t));
@ -313,7 +312,7 @@ int up_shmdt(uintptr_t vaddr, unsigned int npages)
* flush the entire L2 page table numerous times.
*/
arch_flush_dcache((uintptr_t)l2table,
up_flush_dcache((uintptr_t)l2table,
(uintptr_t)l2table +
ENTRIES_PER_L2TABLE * sizeof(uint32_t));

4
arch/arm/src/armv7-a/arm_addrenv_utils.c
View file

@ -43,10 +43,8 @@
#include <debug.h>
#include <nuttx/pgalloc.h>
#include <nuttx/irq.h>
#include "cache.h"
#include "mmu.h"
#include "pgalloc.h"
#include "addrenv.h"
@ -166,7 +164,7 @@ int arm_addrenv_create_region(FAR uintptr_t **list, unsigned int listlen,
* memory.
*/
arch_flush_dcache((uintptr_t)l2table,
up_flush_dcache((uintptr_t)l2table,
(uintptr_t)l2table +
ENTRIES_PER_L2TABLE * sizeof(uint32_t));

205
arch/arm/src/armv7-r/cache.h → arch/arm/src/armv7-a/arm_cache.c
View file

@ -1,7 +1,7 @@
/************************************************************************************
* arch/arm/src/armv7-r/cache.h
/****************************************************************************
* arch/arm/src/armv7-a/arm_cache.c
*
* Copyright (C) 2015 Gregory Nutt. All rights reserved.
* Copyright (C) 2014, 2019 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
@ -31,25 +31,22 @@
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_SRC_ARMV7_R_CACHE_H
#define __ARCH_ARM_SRC_ARMV7_R_CACHE_H
/************************************************************************************
/****************************************************************************
* Included Files
************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
#include <nuttx/cache.h>
#include <nuttx/irq.h>
#include "sctlr.h"
#include "cp15_cacheops.h"
#include "l2cc.h"
/************************************************************************************
/****************************************************************************
* Pre-processor Definitions
************************************************************************************/
****************************************************************************/
/* Intrinsics are used in these inline functions */
@ -61,14 +58,12 @@
#define ARM_ISB() arm_isb(15)
#define ARM_DMB() arm_dmb(15)
/************************************************************************************
* Inline Functions
************************************************************************************/
#ifndef __ASSEMBLY__
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: arch_invalidate_dcache
* Name: up_invalidate_dcache
*
* Description:
* Invalidate the data cache within the specified region; we will be
@ -89,14 +84,14 @@
*
****************************************************************************/
static inline void arch_invalidate_dcache(uintptr_t start, uintptr_t end)
void up_invalidate_dcache(uintptr_t start, uintptr_t end)
{
cp15_invalidate_dcache(start, end);
l2cc_invalidate(start, end);
}
/****************************************************************************
* Name: arch_invalidate_dcache_all
* Name: up_invalidate_dcache_all
*
* Description:
* Invalidate the entire contents of D cache.
@ -112,7 +107,7 @@ static inline void arch_invalidate_dcache(uintptr_t start, uintptr_t end)
*
****************************************************************************/
static inline void arch_invalidate_dcache_all(void)
void up_invalidate_dcache_all(void)
{
#ifdef CONFIG_ARCH_L2CACHE
irqstate_t flags = enter_critical_section();
@ -124,11 +119,12 @@ static inline void arch_invalidate_dcache_all(void)
#endif
}
/************************************************************************************
* Name: arch_invalidate_icache
/****************************************************************************
* Name: up_invalidate_icache_all
*
* Description:
* Invalidate all instruction caches to PoU, also flushes branch target cache
* Invalidate all instruction caches to PoU, also flushes branch target
* cache
*
* Input Parameters:
* None
@ -136,12 +132,15 @@ static inline void arch_invalidate_dcache_all(void)
* Returned Value:
* None
*
************************************************************************************/
****************************************************************************/
#define arch_invalidate_icache() cp15_invalidate_icache()
void up_invalidate_icache_all(void)
{
cp15_invalidate_icache();
}
/****************************************************************************
* Name: arch_clean_dcache
* Name: up_clean_dcache
*
* Description:
* Clean the data cache within the specified region by flushing the
@ -161,14 +160,14 @@ static inline void arch_invalidate_dcache_all(void)
*
****************************************************************************/
static inline void arch_clean_dcache(uintptr_t start, uintptr_t end)
void up_clean_dcache(uintptr_t start, uintptr_t end)
{
cp15_clean_dcache(start, end);
l2cc_clean(start, end);
}
/****************************************************************************
* Name: arch_flush_dcache
* Name: up_flush_dcache
*
* Description:
* Flush the data cache within the specified region by cleaning and
@ -188,14 +187,14 @@ static inline void arch_clean_dcache(uintptr_t start, uintptr_t end)
*
****************************************************************************/
static inline void arch_flush_dcache(uintptr_t start, uintptr_t end)
void up_flush_dcache(uintptr_t start, uintptr_t end)
{
cp15_flush_dcache(start, end);
l2cc_flush(start, end);
}
/****************************************************************************
* Name: arch_enable_icache
* Name: up_enable_icache
*
* Description:
* Enable the I-Cache
@ -208,76 +207,100 @@ static inline void arch_flush_dcache(uintptr_t start, uintptr_t end)
*
****************************************************************************/
static inline void arch_enable_icache(void)
void up_enable_icache(void)
{
#ifdef CONFIG_ARMV7R_ICACHE
uint32_t regval;
ARM_DSB();
ARM_ISB();
/* Enable the I-Cache */
regval = cp15_rdsctlr();
if ((regval & SCTLR_I) == 0)
{
cp15_wrsctlr(regval | SCTLR_I);
}
ARM_DSB();
ARM_ISB();
#endif
cp15_enable_icache();
}
/****************************************************************************
* Name: arch_enable_dcache
*
* Description:
* Enable the D-Cache
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
****************************************************************************/
static inline void arch_enable_dcache(void)
{
#ifdef CONFIG_ARMV7R_DCACHE
uint32_t regval;
/* Enable the D-Cache */
regval = cp15_rdsctlr();
if ((regval & SCTLR_C) == 0)
{
cp15_wrsctlr(regval | SCTLR_C);
}
#endif
}
/****************************************************************************
* Public Data
* Name: up_disable_icache
*
* Description:
* Disable the I-Cache
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
****************************************************************************/
#ifdef __cplusplus
#define EXTERN extern "C"
extern "C"
void up_disable_icache(void)
{
#else
#define EXTERN extern
#endif
cp15_disable_icache();
}
/****************************************************************************
* Public Function Prototypes
* Name: up_enable_dcache
*
* Description:
* Enable the D-Cache
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
****************************************************************************/
#undef EXTERN
#ifdef __cplusplus
void up_enable_dcache(void)
{
cp15_enable_dcache();
l2cc_enable();
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_ARM_SRC_ARMV7_R_CACHE_H */
/****************************************************************************
* Name: up_disable_dcache
*
* Description:
* Disable the D-Cache
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
****************************************************************************/
void up_disable_dcache(void)
{
cp15_disable_dcache();
l2cc_disable();
}
/****************************************************************************
* Name: up_coherent_dcache
*
* Description:
* Ensure that the I and D caches are coherent within specified region
* by cleaning the D cache (i.e., flushing the D cache contents to memory
* and invalidating the I cache. This is typically used when code has been
* written to a memory region, and will be executed.
*
* Input Parameters:
* addr - virtual start address of region
* len - Size of the address region in bytes
*
* Returned Value:
* None
*
****************************************************************************/
void up_coherent_dcache(uintptr_t addr, size_t len)
{
if (len > 0)
{
/* Perform the operation on the L1 cache */
cp15_coherent_dcache(addr, addr + len);
#ifdef CONFIG_ARCH_L2CACHE
/* If we have an L2 cache, then there more things that need to done */
# warning This is insufficient
#endif
}
}

85
arch/arm/src/armv7-a/arm_coherent_dcache.c
View file

@ -1,85 +0,0 @@
/****************************************************************************
* arch/arm/src/armv7-a/up_coherent_dcache.c
*
* Copyright (C) 2014 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <sys/types.h>
#include <stdint.h>
#include "cp15_cacheops.h"
#include <nuttx/arch.h>
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: up_coherent_dcache
*
* Description:
* Ensure that the I and D caches are coherent within specified region
* by cleaning the D cache (i.e., flushing the D cache contents to memory
* and invalidating the I cache. This is typically used when code has been
* written to a memory region, and will be executed.
*
* Input Parameters:
* addr - virtual start address of region
* len - Size of the address region in bytes
*
* Returned Value:
* None
*
****************************************************************************/
void up_coherent_dcache(uintptr_t addr, size_t len)
{
if (len > 0)
{
/* Perform the operation on the L1 cache */
cp15_coherent_dcache(addr, addr + len - 1);
#ifdef CONFIG_ARCH_L2CACHE
/* If we have an L2 cache, then there more things that need to done */
# warning This is insufficient
#endif
}
}

2
arch/arm/src/armv7-a/arm_mmu.c
View file

@ -41,7 +41,7 @@
#include <stdint.h>
#include "cache.h"
#include "cp15_cacheops.h"
#include "mmu.h"
/****************************************************************************

5
arch/arm/src/armv7-a/arm_pgalloc.c
View file

@ -48,7 +48,6 @@
#include <nuttx/arch.h>
#include <nuttx/addrenv.h>
#include "cache.h"
#include "mmu.h"
#include "pgalloc.h"
@ -105,7 +104,7 @@ static uintptr_t alloc_pgtable(void)
* memory.
*/
arch_flush_dcache((uintptr_t)l2table,
up_flush_dcache((uintptr_t)l2table,
(uintptr_t)l2table + MM_PGSIZE);
#ifndef CONFIG_ARCH_PGPOOL_MAPPING
@ -297,7 +296,7 @@ uintptr_t pgalloc(uintptr_t brkaddr, unsigned int npages)
* memory.
*/
arch_flush_dcache((uintptr_t)&l2table[index],
up_flush_dcache((uintptr_t)&l2table[index],
(uintptr_t)&l2table[index] + sizeof(uint32_t));
#ifndef CONFIG_ARCH_PGPOOL_MAPPING

3
arch/arm/src/armv7-a/arm_physpgaddr.c
View file

@ -49,7 +49,6 @@
#include "chip.h"
#include "mmu.h"
#include "cache.h"
#include "pgalloc.h"
@ -115,7 +114,7 @@ uintptr_t arm_physpgaddr(uintptr_t vaddr)
*/
index = (vaddr & SECTION_MASK) >> MM_PGSHIFT;
arch_invalidate_dcache((uintptr_t)&l2table[index],
up_invalidate_dcache((uintptr_t)&l2table[index],
(uintptr_t)&l2table[index] + sizeof(uint32_t));
/* Get the Level 2 page table entry corresponding to this virtual

1
arch/arm/src/armv7-a/arm_scu.c
View file

@ -44,7 +44,6 @@
#include "up_arch.h"
#include "cp15_cacheops.h"
#include "sctlr.h"
#include "cache.h"
#include "scu.h"
#ifdef CONFIG_SMP

110
arch/arm/src/armv7-a/cp15_cacheops.h
View file

@ -193,6 +193,26 @@
#ifdef __ASSEMBLY__
/************************************************************************************
* Name: cp15_enable_dcache
*
* Description:
* Enable L1 D Cache
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
************************************************************************************/
.macro cp15_enable_dcache, tmp
mrc p15, 0, \tmp, c1, c0, 0 /* Read SCTLR */
orr \tmp, \tmp, #(0x1 << 2) /* Enable D cache */
mcr p15, 0, \tmp, c1, c0, 0 /* Update the SCTLR */
.endm
/************************************************************************************
* Name: cp15_disable_dcache
*
@ -214,10 +234,10 @@
.endm
/************************************************************************************
* Name: cp15_disable_caches
* Name: cp15_enable_icache
*
* Description:
* Disable L1 Caches
* Enable L1 I Cache
*
* Input Parameters:
* None
@ -227,10 +247,29 @@
*
************************************************************************************/
.macro cp15_disable_caches, tmp
.macro cp15_enable_icache, tmp
mrc p15, 0, \tmp, c1, c0, 0 /* Read SCTLR */
orr \tmp, \tmp, #(0x1 << 12) /* Enable I cache */
mcr p15, 0, \tmp, c1, c0, 0 /* Update the SCTLR */
.endm
/************************************************************************************
* Name: cp15_disable_icache
*
* Description:
* Disable L1 I Cache
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
************************************************************************************/
.macro cp15_disable_icache, tmp
mrc p15, 0, \tmp, c1, c0, 0 /* Read SCTLR */
bic \tmp, \tmp, #(0x1 << 12) /* Disable I cache */
bic \tmp, \tmp, #(0x1 << 2) /* Disable D cache */
mcr p15, 0, \tmp, c1, c0, 0 /* Update the SCTLR */
.endm
@ -481,11 +520,38 @@
#ifndef __ASSEMBLY__
/************************************************************************************
* Name: cp15_enable_dcache
*
* Description:
* Enable L1 D Cache
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
************************************************************************************/
static inline void cp15_enable_dcache(void)
{
__asm__ __volatile__
(
"\tmrc p15, 0, r0, c1, c0, 0\n" /* Read SCTLR */
"\torr r0, r0, #(1 << 2)\n" /* Enable D cache */
"\tmcr p15, 0, r0, c1, c0, 0\n" /* Update the SCTLR */
:
:
: "r0", "memory"
);
}
/************************************************************************************
* Name: cp15_disable_dcache
*
* Description:
* Disable L1 Caches
* Disable L1 D Cache
*
* Input Parameters:
* None
@ -509,10 +575,10 @@ static inline void cp15_disable_dcache(void)
}
/************************************************************************************
* Name: cp15_disable_caches
* Name: cp15_enable_icache
*
* Description:
* Disable L1 Caches
* Enable L1 I Cache
*
* Input Parameters:
* None
@ -522,13 +588,39 @@ static inline void cp15_disable_dcache(void)
*
************************************************************************************/
static inline void cp15_disable_caches(void)
static inline void cp15_enable_icache(void)
{
__asm__ __volatile__
(
"\tmrc p15, 0, r0, c1, c0, 0\n" /* Read SCTLR */
"\torr r0, r0, #(1 << 12)\n" /* Enable I cache */
"\tmcr p15, 0, r0, c1, c0, 0\n" /* Update the SCTLR */
:
:
: "r0", "memory"
);
}
/************************************************************************************
* Name: cp15_disable_icache
*
* Description:
* Disable L1 I Cache
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
************************************************************************************/
static inline void cp15_disable_icache(void)
{
__asm__ __volatile__
(
"\tmrc p15, 0, r0, c1, c0, 0\n" /* Read SCTLR */
"\tbic r0, r0, #(1 << 12)\n" /* Disable I cache */
"\tbic r0, r0, #(1 << 2)\n" /* Disable D cache */
"\tmcr p15, 0, r0, c1, c0, 0\n" /* Update the SCTLR */
:
:

2
arch/arm/src/armv7-m/Kconfig
View file

@ -89,11 +89,13 @@ config ARMV7M_ICACHE
bool "Use I-Cache"
default n
depends on ARMV7M_HAVE_ICACHE
select ARCH_ICACHE
config ARMV7M_DCACHE
bool "Use D-Cache"
default n
depends on ARMV7M_HAVE_DCACHE
select ARCH_DCACHE
config ARMV7M_DCACHE_WRITETHROUGH
bool "D-Cache Write-Through"

149
arch/arm/src/armv7-m/arch_clean_dcache.c
View file

@ -1,149 +0,0 @@
/****************************************************************************
* arch/arm/src/armv7-m/arch_clean_dcache.c
*
* Copyright (C) 2015 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Some logic in this header file derives from the ARM CMSIS core_cm7.h
* header file which has a compatible 3-clause BSD license:
*
* Copyright (c) 2009 - 2014 ARM LIMITED. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name ARM, NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "cache.h"
#if defined(CONFIG_ARMV7M_DCACHE) && !defined(CONFIG_ARMV7M_DCACHE_WRITETHROUGH)
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: arch_clean_dcache
*
* Description:
* Clean the data cache within the specified region by flushing the
* contents of the data cache to memory.
*
* Input Parameters:
* start - virtual start address of region
* end - virtual end address of region + 1
*
* Returned Value:
* None
*
* Assumptions:
* This operation is not atomic. This function assumes that the caller
* has exclusive access to the address range so that no harm is done if
* the operation is pre-empted.
*
****************************************************************************/
void arch_clean_dcache(uintptr_t start, uintptr_t end)
{
uint32_t ccsidr;
uint32_t smask;
uint32_t sshift;
uint32_t ways;
uint32_t wshift;
uint32_t ssize;
uint32_t set;
uint32_t sw;
/* Get the characteristics of the D-Cache */
ccsidr = getreg32(NVIC_CCSIDR);
smask = CCSIDR_SETS(ccsidr); /* (Number of sets) - 1 */
sshift = CCSIDR_LSSHIFT(ccsidr) + 4; /* log2(cache-line-size-in-bytes) */
ways = CCSIDR_WAYS(ccsidr); /* (Number of ways) - 1 */
/* Calculate the bit offset for the way field in the DCCSW register by
* counting the number of leading zeroes. For example:
*
* Number of Value of ways Field
* Ways 'ways' Offset
* 2 1 31
* 4 3 30
* 8 7 29
* ...
*/
wshift = arm_clz(ways) & 0x1f;
/* Clean the D-Cache over the range of addresses */
ssize = (1 << sshift);
start &= ~(ssize - 1);
ARM_DSB();
do
{
int32_t tmpways = ways;
/* Isolate the cache line associated with this address. For example
* if the cache line size is 32 bytes and the cache size is 16KB, then
*
* sshift = 5 : Offset to the beginning of the set field
* smask = 0x007f : Mask of the set field
*/
set = ((uint32_t)start >> sshift) & smask;
/* Clean and invalidate each way for this cacheline */
do
{
sw = ((tmpways << wshift) | (set << sshift));
putreg32(sw, NVIC_DCCSW);
}
while (tmpways--);
/* Increment the address by the size of one cache line. */
start += ssize;
}
while (start < end);
ARM_DSB();
ARM_ISB();
}
#endif /* CONFIG_ARMV7M_DCACHE && !CONFIG_ARMV7M_DCACHE_WRITETHROUGH */

129
arch/arm/src/armv7-m/arch_clean_dcache_all.c
View file

@ -1,129 +0,0 @@
/****************************************************************************
* arch/arm/src/armv7-m/arch_clean_dcache_all.c
*
* Copyright (C) 2015 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Some logic in this header file derives from the ARM CMSIS core_cm7.h
* header file which has a compatible 3-clause BSD license:
*
* Copyright (c) 2009 - 2014 ARM LIMITED. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name ARM, NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "cache.h"
#if defined(CONFIG_ARMV7M_DCACHE) && !defined(CONFIG_ARMV7M_DCACHE_WRITETHROUGH)
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: arch_clean_dcache_all
*
* Description:
* Clean the entire data cache within the specified region by flushing the
* contents of the data cache to memory.
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
* Assumptions:
* This operation is not atomic. This function assumes that the caller
* has exclusive access to the address range so that no harm is done if
* the operation is pre-empted.
*
****************************************************************************/
void arch_clean_dcache_all(void)
{
uint32_t ccsidr;
uint32_t sshift;
uint32_t wshift;
uint32_t sw;
uint32_t sets;
uint32_t ways;
/* Get the characteristics of the D-Cache */
ccsidr = getreg32(NVIC_CCSIDR);
sets = CCSIDR_SETS(ccsidr); /* (Number of sets) - 1 */
sshift = CCSIDR_LSSHIFT(ccsidr) + 4; /* log2(cache-line-size-in-bytes) */
ways = CCSIDR_WAYS(ccsidr); /* (Number of ways) - 1 */
/* Calculate the bit offset for the way field in the DCCSW register by
* counting the number of leading zeroes. For example:
*
* Number of Value of ways Field
* Ways 'ways' Offset
* 2 1 31
* 4 3 30
* 8 7 29
* ...
*/
wshift = arm_clz(ways) & 0x1f;
ARM_DSB();
/* Clean the entire D-Cache */
do
{
int32_t tmpways = ways;
do
{
sw = ((tmpways << wshift) | (sets << sshift));
putreg32(sw, NVIC_DCCSW);
}
while (tmpways--);
}
while (sets--);
ARM_DSB();
ARM_ISB();
}
#endif /* CONFIG_ARMV7M_DCACHE && !CONFIG_ARMV7M_DCACHE_WRITETHROUGH */

130
arch/arm/src/armv7-m/arch_disable_dcache.c
View file

@ -1,130 +0,0 @@
/****************************************************************************
* arch/arm/src/armv7-m/arch_disable_dcache.c
*
* Copyright (C) 2015 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Some logic in this header file derives from the ARM CMSIS core_cm7.h
* header file which has a compatible 3-clause BSD license:
*
* Copyright (c) 2009 - 2014 ARM LIMITED. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name ARM, NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "cache.h"
#ifdef CONFIG_ARMV7M_DCACHE
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: arch_disable_dcache
*
* Description:
* Disable the D-Cache
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
****************************************************************************/
void arch_disable_dcache(void)
{
uint32_t ccsidr;
uint32_t ccr;
uint32_t sshift;
uint32_t wshift;
uint32_t sw;
uint32_t sets;
uint32_t ways;
/* Get the characteristics of the D-Cache */
ccsidr = getreg32(NVIC_CCSIDR);
sets = CCSIDR_SETS(ccsidr); /* (Number of sets) - 1 */
sshift = CCSIDR_LSSHIFT(ccsidr) + 4; /* log2(cache-line-size-in-bytes) */
ways = CCSIDR_WAYS(ccsidr); /* (Number of ways) - 1 */
/* Calculate the bit offset for the way field in the DCCISW register by
* counting the number of leading zeroes. For example:
*
* Number of Value of ways Field
* Ways 'ways' Offset
* 2 1 31
* 4 3 30
* 8 7 29
* ...
*/
wshift = arm_clz(ways) & 0x1f;
ARM_DSB();
/* Disable the D-Cache */
ccr = getreg32(NVIC_CFGCON);
ccr &= ~NVIC_CFGCON_DC;
putreg32(ccr, NVIC_CFGCON);
/* Clean and invalidate the entire D-Cache */
do
{
int32_t tmpways = ways;
do
{
sw = ((tmpways << wshift) | (sets << sshift));
putreg32(sw, NVIC_DCCISW);
}
while (tmpways--);
}
while (sets--);
ARM_DSB();
ARM_ISB();
}
#endif /* CONFIG_ARMV7M_DCACHE */

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/****************************************************************************
* arch/arm/src/armv7-m/arch_enable_dcache.c
*
* Copyright (C) 2015 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Some logic in this header file derives from the ARM CMSIS core_cm7.h
* header file which has a compatible 3-clause BSD license:
*
* Copyright (c) 2009 - 2014 ARM LIMITED. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name ARM, NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "cache.h"
#ifdef CONFIG_ARMV7M_DCACHE
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: arch_enable_dcache
*
* Description:
* Enable the D-Cache
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
****************************************************************************/
void arch_enable_dcache(void)
{
uint32_t ccsidr;
uint32_t ccr;
uint32_t sshift;
uint32_t wshift;
uint32_t sw;
uint32_t sets;
uint32_t ways;
/* Get the characteristics of the D-Cache */
ccsidr = getreg32(NVIC_CCSIDR);
sets = CCSIDR_SETS(ccsidr); /* (Number of sets) - 1 */
sshift = CCSIDR_LSSHIFT(ccsidr) + 4; /* log2(cache-line-size-in-bytes) */
ways = CCSIDR_WAYS(ccsidr); /* (Number of ways) - 1 */
/* Calculate the bit offset for the way field in the DCISW register by
* counting the number of leading zeroes. For example:
*
* Number of Value of ways Field
* Ways 'ways' Offset
* 2 1 31
* 4 3 30
* 8 7 29
* ...
*/
wshift = arm_clz(ways) & 0x1f;
/* Invalidate the entire D-Cache */
ARM_DSB();
do
{
int32_t tmpways = ways;
do
{
sw = ((tmpways << wshift) | (sets << sshift));
putreg32(sw, NVIC_DCISW);
}
while (tmpways--);
}
while (sets--);
ARM_DSB();
/* Enable the D-Cache */
ccr = getreg32(NVIC_CFGCON);
ccr |= NVIC_CFGCON_DC;
putreg32(ccr, NVIC_CFGCON);
ARM_DSB();
ARM_ISB();
}
#endif /* CONFIG_ARMV7M_DCACHE */

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/****************************************************************************
* arch/arm/src/armv7-m/arch_flush_dcache.c
*
* Copyright (C) 2015 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Some logic in this header file derives from the ARM CMSIS core_cm7.h
* header file which has a compatible 3-clause BSD license:
*
* Copyright (c) 2009 - 2014 ARM LIMITED. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name ARM, NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "cache.h"
#if defined(CONFIG_ARMV7M_DCACHE) && !defined(CONFIG_ARMV7M_DCACHE_WRITETHROUGH)
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: arch_flush_dcache
*
* Description:
* Flush the data cache within the specified region by cleaning and
* invalidating the D cache.
*
* Input Parameters:
* start - virtual start address of region
* end - virtual end address of region + 1
*
* Returned Value:
* None
*
* Assumptions:
* This operation is not atomic. This function assumes that the caller
* has exclusive access to the address range so that no harm is done if
* the operation is pre-empted.
*
****************************************************************************/
void arch_flush_dcache(uintptr_t start, uintptr_t end)
{
uint32_t ccsidr;
uint32_t smask;
uint32_t sshift;
uint32_t ways;
uint32_t wshift;
uint32_t ssize;
uint32_t set;
uint32_t sw;
/* Get the characteristics of the D-Cache */
ccsidr = getreg32(NVIC_CCSIDR);
smask = CCSIDR_SETS(ccsidr); /* (Number of sets) - 1 */
sshift = CCSIDR_LSSHIFT(ccsidr) + 4; /* log2(cache-line-size-in-bytes) */
ways = CCSIDR_WAYS(ccsidr); /* (Number of ways) - 1 */
/* Calculate the bit offset for the way field in the DCCISW register by
* counting the number of leading zeroes. For example:
*
* Number of Value of ways Field
* Ways 'ways' Offset
* 2 1 31
* 4 3 30
* 8 7 29
* ...
*/
wshift = arm_clz(ways) & 0x1f;
/* Clean and invalidate the D-Cache over the range of addresses */
ssize = (1 << sshift);
start &= ~(ssize - 1);
ARM_DSB();
do
{
int32_t tmpways = ways;
/* Isolate the cache line associated with this address. For example
* if the cache line size is 32 bytes and the cache size is 16KB, then
*
* sshift = 5 : Offset to the beginning of the set field
* smask = 0x007f : Mask of the set field
*/
set = ((uint32_t)start >> sshift) & smask;
/* Clean and invalidate each way for this cacheline */
do
{
sw = ((tmpways << wshift) | (set << sshift));
putreg32(sw, NVIC_DCCISW);
}
while (tmpways--);
/* Increment the address by the size of one cache line. */
start += ssize;
}
while (start < end);
ARM_DSB();
ARM_ISB();
}
#endif /* CONFIG_ARMV7M_DCACHE && !CONFIG_ARMV7M_DCACHE_WRITETHROUGH */

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/****************************************************************************
* arch/arm/src/armv7-m/arch_flush_dcache_all.c
*
* Copyright (C) 2015 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Some logic in this header file derives from the ARM CMSIS core_cm7.h
* header file which has a compatible 3-clause BSD license:
*
* Copyright (c) 2009 - 2014 ARM LIMITED. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name ARM, NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "cache.h"
#if defined(CONFIG_ARMV7M_DCACHE) && !defined(CONFIG_ARMV7M_DCACHE_WRITETHROUGH)
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: arch_flush_dcache_all
*
* Description:
* Flush the entire data cache by cleaning and invalidating the D cache.
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
* Assumptions:
* This operation is not atomic. This function assumes that the caller
* has exclusive access to the address range so that no harm is done if
* the operation is pre-empted.
*
****************************************************************************/
void arch_flush_dcache_all(void)
{
uint32_t ccsidr;
uint32_t sshift;
uint32_t wshift;
uint32_t sw;
uint32_t sets;
uint32_t ways;
/* Get the characteristics of the D-Cache */
ccsidr = getreg32(NVIC_CCSIDR);
sets = CCSIDR_SETS(ccsidr); /* (Number of sets) - 1 */
sshift = CCSIDR_LSSHIFT(ccsidr) + 4; /* log2(cache-line-size-in-bytes) */
ways = CCSIDR_WAYS(ccsidr); /* (Number of ways) - 1 */
/* Calculate the bit offset for the way field in the DCCISW register by
* counting the number of leading zeroes. For example:
*
* Number of Value of ways Field
* Ways 'ways' Offset
* 2 1 31
* 4 3 30
* 8 7 29
* ...
*/
wshift = arm_clz(ways) & 0x1f;
ARM_DSB();
/* Clean and invalidate the entire D-Cache */
do
{
int32_t tmpways = ways;
do
{
sw = ((tmpways << wshift) | (sets << sshift));
putreg32(sw, NVIC_DCCISW);
}
while (tmpways--);
}
while (sets--);
ARM_DSB();
ARM_ISB();
}
#endif /* CONFIG_ARMV7M_DCACHE && !CONFIG_ARMV7M_DCACHE_WRITETHROUGH */

217
arch/arm/src/armv7-m/arch_invalidate_dcache.c
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@ -1,217 +0,0 @@
/****************************************************************************
* arch/arm/src/armv7-m/arch_invalidate_dcache.c
*
* Copyright (C) 2015, 2018 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
* Bob Feretich <bob.feretich@rafresearch.com>
*
* Some logic in this header file derives from the ARM CMSIS core_cm7.h
* header file which has a compatible 3-clause BSD license:
*
* Copyright (c) 2009 - 2014 ARM LIMITED. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name ARM, NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "cache.h"
#ifdef CONFIG_ARMV7M_DCACHE
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: arch_invalidate_dcache
*
* Description:
* Invalidate the data cache within the specified region; we will be
* performing a DMA operation in this region and we want to purge old data
* in the cache. Note that this function invalidates all cache ways
* in sets that could be associated with the address range, regardless of
* whether the address range is contained in the cache or not.
*
* Input Parameters:
* start - virtual start address of region
* end - virtual end address of region + 1
*
* Returned Value:
* None
*
* Assumptions:
* This operation is not atomic. This function assumes that the caller
* has exclusive access to the address range so that no harm is done if
* the operation is pre-empted.
*
****************************************************************************/
void arch_invalidate_dcache(uintptr_t start, uintptr_t end)
{
uint32_t ccsidr;
uint32_t smask;
uint32_t sshift;
uint32_t ways;
uint32_t wshift;
uint32_t ssize;
uint32_t set;
uint32_t sw;
/* Get the characteristics of the D-Cache */
ccsidr = getreg32(NVIC_CCSIDR);
smask = CCSIDR_SETS(ccsidr); /* (Number of sets) - 1 */
sshift = CCSIDR_LSSHIFT(ccsidr) + 4; /* log2(cache-line-size-in-bytes) */
ways = CCSIDR_WAYS(ccsidr); /* (Number of ways) - 1 */
/* Calculate the bit offset for the way field in the DCISW register by
* counting the number of leading zeroes. For example:
*
* Number of Value of ways Field
* Ways 'ways' Offset
* 2 1 31
* 4 3 30
* 8 7 29
* ...
*/
wshift = arm_clz(ways) & 0x1f;
/* Invalidate the D-Cache over the range of addresses */
ssize = (1 << sshift);
start &= ~(ssize - 1);
ARM_DSB();
do
{
int32_t tmpways = ways;
/* Isolate the cache line associated with this address. For example
* if the cache line size is 32 bytes and the cache size is 16KB, then
*
* sshift = 5 : Offset to the beginning of the set field
* smask = 0x007f : Mask of the set field
*/
set = ((uint32_t)start >> sshift) & smask;
/* Clean and invalidate each way for this cacheline */
do
{
sw = ((tmpways << wshift) | (set << sshift));
putreg32(sw, NVIC_DCISW);
}
while (tmpways--);
/* Increment the address by the size of one cache line. */
start += ssize;
}
while (start < end);
ARM_DSB();
ARM_ISB();
}
/****************************************************************************
* Name: arch_invalidate_dcache_by_addr
*
* Description:
* Invalidate the data cache within the specified region; we will be
* performing a DMA operation in this region and we want to purge old data
* in the cache. Note that this function only invalidates cache sets that
* contain data from this address range.
*
* Input Parameters:
* start - virtual start address of region
* end - virtual end address of region + 1
*
* Returned Value:
* None
*
* Assumptions:
* This operation is not atomic. This function assumes that the caller
* has exclusive access to the address range so that no harm is done if
* the operation is pre-empted.
*
****************************************************************************/
void arch_invalidate_dcache_by_addr(uintptr_t start, uintptr_t end)
{
uint32_t ccsidr;
uint32_t sshift;
uint32_t ssize;
/* Get the characteristics of the D-Cache */
ccsidr = getreg32(NVIC_CCSIDR);
sshift = CCSIDR_LSSHIFT(ccsidr) + 4; /* log2(cache-line-size-in-bytes) */
/* Invalidate the D-Cache containing this range of addresses */
ssize = (1 << sshift);
/* Round down the start address to the nearest cache line boundary.
*
* sshift = 5 : Offset to the beginning of the set field
* (ssize - 1) = 0x007f : Mask of the set field
*/
start &= ~(ssize - 1);
ARM_DSB();
do
{
/* The below store causes the cache to check its directory and
* determine if this address is contained in the cache. If so, it
* invalidate that cache line. Only the cache way containing the
* address is invalidated. If the address is not in the cache, then
* nothing is invalidated.
*/
putreg32(start, NVIC_DCIMVAC);
/* Increment the address by the size of one cache line. */
start += ssize;
}
while (start < end);
ARM_DSB();
ARM_ISB();
}
#endif /* CONFIG_ARMV7M_DCACHE */

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/****************************************************************************
* arch/arm/src/armv7-m/arch_invalidate_dcache_all.c
*
* Copyright (C) 2015 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Some logic in this header file derives from the ARM CMSIS core_cm7.h
* header file which has a compatible 3-clause BSD license:
*
* Copyright (c) 2009 - 2014 ARM LIMITED. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name ARM, NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "cache.h"
#ifdef CONFIG_ARMV7M_DCACHE
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: arch_invalidate_dcache_all
*
* Description:
* Invalidate the entire contents of D cache.
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
****************************************************************************/
void arch_invalidate_dcache_all(void)
{
uint32_t ccsidr;
uint32_t sshift;
uint32_t wshift;
uint32_t sw;
uint32_t sets;
uint32_t ways;
/* Get the characteristics of the D-Cache */
ccsidr = getreg32(NVIC_CCSIDR);
sets = CCSIDR_SETS(ccsidr); /* (Number of sets) - 1 */
sshift = CCSIDR_LSSHIFT(ccsidr) + 4; /* log2(cache-line-size-in-bytes) */
ways = CCSIDR_WAYS(ccsidr); /* (Number of ways) - 1 */
/* Calculate the bit offset for the way field in the DCISW register by
* counting the number of leading zeroes. For example:
*
* Number of Value of ways Field
* Ways 'ways' Offset
* 2 1 31
* 4 3 30
* 8 7 29
* ...
*/
wshift = arm_clz(ways) & 0x1f;
ARM_DSB();
/* Invalidate the entire D-Cache */
do
{
int32_t tmpways = ways;
do
{
sw = ((tmpways << wshift) | (sets << sshift));
putreg32(sw, NVIC_DCISW);
}
while (tmpways--);
}
while (sets--);
ARM_DSB();
ARM_ISB();
}
#endif /* CONFIG_ARMV7M_DCACHE */

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arch/arm/src/armv7-m/cache.h
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/****************************************************************************
* arch/arm/src/armv7-m/cache.h
*
* Copyright (C) 2015, 2018 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Some logic in this header file derives from the ARM CMSIS core_cm7.h
* header file which has a compatible 3-clause BSD license:
*
* Copyright (c) 2009 - 2014 ARM LIMITED. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name ARM, NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_ARMV7_M_CACHE_H
#define __ARCH_ARM_SRC_ARMV7_M_CACHE_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "up_arch.h"
#include "nvic.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Cache Size ID (CCSIDR) register macros used by inline functions
* Given the value of the CCSIDR reginer (n):
*
* CCSIDR_WAYS - Returns the (number of ways) - 1
* CCSIDR_SETS - Returns the (number of sets) - 1
* CCSIDR_LSSHIFT - Returns log2(cache line size in words) - 2
* Eg. 0 -> 4 words
* 1 -> 8 words
* ...
*/
#define CCSIDR_WAYS(n) \
(((n) & NVIC_CCSIDR_ASSOCIATIVITY_MASK) >> NVIC_CCSIDR_ASSOCIATIVITY_SHIFT)
#define CCSIDR_SETS(n) \
(((n) & NVIC_CCSIDR_NUMSETS_MASK) >> NVIC_CCSIDR_NUMSETS_SHIFT)
#define CCSIDR_LSSHIFT(n) \
(((n) & NVIC_CCSIDR_LINESIZE_MASK) >> NVIC_CCSIDR_LINESIZE_SHIFT)
/* intrinsics are used in these inline functions */
#define arm_isb(n) __asm__ __volatile__ ("isb " #n : : : "memory")
#define arm_dsb(n) __asm__ __volatile__ ("dsb " #n : : : "memory")
#define arm_dmb(n) __asm__ __volatile__ ("dmb " #n : : : "memory")
#define ARM_DSB() arm_dsb(15)
#define ARM_ISB() arm_isb(15)
#define ARM_DMB() arm_dmb(15)
/****************************************************************************
* Inline Functions
****************************************************************************/
#ifndef __ASSEMBLY__
/****************************************************************************
* Name: arm_clz
*
* Description:
* Access to CLZ instructions
*
* Input Parameters:
* value - The value to perform the CLZ operation on
*
* Returned Value:
* None
*
****************************************************************************/
static inline uint32_t arm_clz(unsigned int value)
{
uint32_t ret;
__asm__ __volatile__ ("clz %0, %1" : "=r"(ret) : "r"(value));
return ret;
}
/****************************************************************************
* Name: arch_enable_icache
*
* Description:
* Enable the I-Cache
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
****************************************************************************/
static inline void arch_enable_icache(void)
{
#ifdef CONFIG_ARMV7M_ICACHE
uint32_t regval;
ARM_DSB();
ARM_ISB();
/* Invalidate the entire I-Cache */
putreg32(0, NVIC_ICIALLU);
/* Enable the I-Cache */
regval = getreg32(NVIC_CFGCON);
regval |= NVIC_CFGCON_IC;
putreg32(regval, NVIC_CFGCON);
ARM_DSB();
ARM_ISB();
#endif
}
/****************************************************************************
* Name: arch_disable_icache
*
* Description:
* Disable the I-Cache
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
****************************************************************************/
static inline void arch_disable_icache(void)
{
#ifdef CONFIG_ARMV7M_ICACHE
uint32_t regval;
ARM_DSB();
ARM_ISB();
/* Disable the I-Cache */
regval = getreg32(NVIC_CFGCON);
regval &= ~NVIC_CFGCON_IC;
putreg32(regval, NVIC_CFGCON);
/* Invalidate the entire I-Cache */
putreg32(0, NVIC_ICIALLU);
ARM_DSB();
ARM_ISB();
#endif
}
/****************************************************************************
* Name: arch_invalidate_icache_all
*
* Description:
* Invalidate the entire contents of I cache.
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
****************************************************************************/
static inline void arch_invalidate_icache_all(void)
{
#ifdef CONFIG_ARMV7M_ICACHE
ARM_DSB();
ARM_ISB();
/* Invalidate the entire I-Cache */
putreg32(0, NVIC_ICIALLU);
ARM_DSB();
ARM_ISB();
#endif
}
/****************************************************************************
* Name: arch_dcache_writethrough
*
* Description:
* Configure the D-Cache for Write-Through operation.
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
****************************************************************************/
#if defined(CONFIG_ARMV7M_DCACHE) && defined(CONFIG_ARMV7M_DCACHE_WRITETHROUGH)
static inline void arch_dcache_writethrough(void)
{
uint32_t regval = getreg32(NVIC_CACR);
regval |= NVIC_CACR_FORCEWT;
putreg32(regval, NVIC_CACR);
}
#else
# define arch_dcache_writethrough()
#endif
/****************************************************************************
* Public Data
****************************************************************************/
#ifdef __cplusplus
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
/****************************************************************************
* Name: arch_enable_dcache
*
* Description:
* Enable the D-Cache
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
****************************************************************************/
#ifdef CONFIG_ARMV7M_DCACHE
void arch_enable_dcache(void);
#else
# define arch_enable_dcache()
#endif
/****************************************************************************
* Name: arch_disable_dcache
*
* Description:
* Disable the D-Cache
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
****************************************************************************/
#ifdef CONFIG_ARMV7M_DCACHE
void arch_disable_dcache(void);
#else
# define arch_disable_dcache()
#endif
/****************************************************************************
* Name: arch_invalidate_dcache
*
* Description:
* Invalidate the data cache within the specified region; we will be
* performing a DMA operation in this region and we want to purge old data
* in the cache. Note that this function invalidates all cache ways
* in sets that could be associated with the address range, regardless of
* whether the address range is contained in the cache or not.
*
* Input Parameters:
* start - virtual start address of region
* end - virtual end address of region + 1
*
* Returned Value:
* None
*
* Assumptions:
* This operation is not atomic. This function assumes that the caller
* has exclusive access to the address range so that no harm is done if
* the operation is pre-empted.
*
****************************************************************************/
#ifdef CONFIG_ARMV7M_DCACHE
void arch_invalidate_dcache(uintptr_t start, uintptr_t end);
#else
# define arch_invalidate_dcache(s,e)
#endif
/****************************************************************************
* Name: arch_invalidate_dcache_by_addr
*
* Description:
* Invalidate the data cache within the specified region; we will be
* performing a DMA operation in this region and we want to purge old data
* in the cache. Note that this function only invalidates cache sets that
* contain data from this address range.
*
* Input Parameters:
* start - virtual start address of region
* end - virtual end address of region + 1
*
* Returned Value:
* None
*
* Assumptions:
* This operation is not atomic. This function assumes that the caller
* has exclusive access to the address range so that no harm is done if
* the operation is pre-empted.
*
****************************************************************************/
#ifdef CONFIG_ARMV7M_DCACHE
void arch_invalidate_dcache_by_addr(uintptr_t start, uintptr_t end);
#else
# define arch_invalidate_dcache_by_addr(s,e)
#endif
/****************************************************************************
* Name: arch_invalidate_dcache_all
*
* Description:
* Invalidate the entire contents of D cache.
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
****************************************************************************/
#ifdef CONFIG_ARMV7M_DCACHE
void arch_invalidate_dcache_all(void);
#else
# define arch_invalidate_dcache_all()
#endif
/****************************************************************************
* Name: arch_clean_dcache
*
* Description:
* Clean the data cache within the specified region by flushing the
* contents of the data cache to memory.
*
* NOTE: This operation is un-necessary if the DCACHE is configured in
* write-through mode.
*
* Input Parameters:
* start - virtual start address of region
* end - virtual end address of region + 1
*
* Returned Value:
* None
*
* Assumptions:
* This operation is not atomic. This function assumes that the caller
* has exclusive access to the address range so that no harm is done if
* the operation is pre-empted.
*
****************************************************************************/
#if defined(CONFIG_ARMV7M_DCACHE) && !defined(CONFIG_ARMV7M_DCACHE_WRITETHROUGH)
void arch_clean_dcache(uintptr_t start, uintptr_t end);
#else
# define arch_clean_dcache(s,e)
#endif
/****************************************************************************
* Name: arch_clean_dcache_all
*
* Description:
* Clean the entire data cache within the specified region by flushing the
* contents of the data cache to memory.
*
* NOTE: This operation is un-necessary if the DCACHE is configured in
* write-through mode.
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
* Assumptions:
* This operation is not atomic. This function assumes that the caller
* has exclusive access to the address range so that no harm is done if
* the operation is pre-empted.
*
****************************************************************************/
#if defined(CONFIG_ARMV7M_DCACHE) && !defined(CONFIG_ARMV7M_DCACHE_WRITETHROUGH)
void arch_clean_dcache_all(void);
#else
# define arch_clean_dcache_all()
#endif
/****************************************************************************
* Name: arch_flush_dcache
*
* Description:
* Flush the data cache within the specified region by cleaning and
* invalidating the D cache.
*
* NOTE: If DCACHE write-through is configured, then this operation is the
* same as arch_invalidate_cache().
*
* Input Parameters:
* start - virtual start address of region
* end - virtual end address of region + 1
*
* Returned Value:
* None
*
* Assumptions:
* This operation is not atomic. This function assumes that the caller
* has exclusive access to the address range so that no harm is done if
* the operation is pre-empted.
*
****************************************************************************/
#ifdef CONFIG_ARMV7M_DCACHE
#ifdef CONFIG_ARMV7M_DCACHE_WRITETHROUGH
# define arch_flush_dcache(s,e) arch_invalidate_dcache(s,e)
#else
void arch_flush_dcache(uintptr_t start, uintptr_t end);
#endif
#else
# define arch_flush_dcache(s,e)
#endif
/****************************************************************************
* Name: arch_flush_dcache_all
*
* Description:
* Flush the entire data cache by cleaning and invalidating the D cache.
*
* NOTE: If DCACHE write-through is configured, then this operation is the
* same as arch_invalidate_cache_all().
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
* Assumptions:
* This operation is not atomic. This function assumes that the caller
* has exclusive access to the address range so that no harm is done if
* the operation is pre-empted.
*
****************************************************************************/
#ifdef CONFIG_ARMV7M_DCACHE
#ifdef CONFIG_ARMV7M_DCACHE_WRITETHROUGH
# define arch_flush_dcache_all() arch_invalidate_dcache_all()
#else
void arch_flush_dcache_all(void);
#endif
#else
# define arch_flush_dcache_all()
#endif
#undef EXTERN
#ifdef __cplusplus
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_ARM_SRC_ARMV7_M_CACHE_H */

2
arch/arm/src/armv7-m/mpu.h
View file

@ -268,7 +268,6 @@ static inline void mpu_control(bool enable, bool hfnmiena, bool privdefena)
*
****************************************************************************/
#if defined(CONFIG_ARMV7M_HAVE_ICACHE) || defined(CONFIG_ARMV7M_DCACHE)
static inline void mpu_priv_stronglyordered(uintptr_t base, size_t size)
{
unsigned int region = mpu_allocregion();
@ -300,7 +299,6 @@ static inline void mpu_priv_stronglyordered(uintptr_t base, size_t size)
MPU_RASR_AP_RWNO; /* P:RW U:None */
putreg32(regval, MPU_RASR);
}
#endif
/****************************************************************************
* Name: mpu_user_flash

832
arch/arm/src/armv7-m/up_cache.c Normal file
View file

@ -0,0 +1,832 @@
/****************************************************************************
* arch/arm/src/armv7-m/up_cache.c
*
* Copyright (C) 2015, 2018 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
* Bob Feretich <bob.feretich@rafresearch.com>
*
* Some logic in this header file derives from the ARM CMSIS core_cm7.h
* header file which has a compatible 3-clause BSD license:
*
* Copyright (c) 2009 - 2014 ARM LIMITED. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name ARM, NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <nuttx/cache.h>
#include "up_arch.h"
#include "nvic.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Cache Size ID (CCSIDR) register macros used by inline functions
* Given the value of the CCSIDR reginer (n):
*
* CCSIDR_WAYS - Returns the (number of ways) - 1
* CCSIDR_SETS - Returns the (number of sets) - 1
* CCSIDR_LSSHIFT - Returns log2(cache line size in words) - 2
* Eg. 0 -> 4 words
* 1 -> 8 words
* ...
*/
#define CCSIDR_WAYS(n) \
(((n) & NVIC_CCSIDR_ASSOCIATIVITY_MASK) >> NVIC_CCSIDR_ASSOCIATIVITY_SHIFT)
#define CCSIDR_SETS(n) \
(((n) & NVIC_CCSIDR_NUMSETS_MASK) >> NVIC_CCSIDR_NUMSETS_SHIFT)
#define CCSIDR_LSSHIFT(n) \
(((n) & NVIC_CCSIDR_LINESIZE_MASK) >> NVIC_CCSIDR_LINESIZE_SHIFT)
/* intrinsics are used in these inline functions */
#define arm_isb(n) __asm__ __volatile__ ("isb " #n : : : "memory")
#define arm_dsb(n) __asm__ __volatile__ ("dsb " #n : : : "memory")
#define arm_dmb(n) __asm__ __volatile__ ("dmb " #n : : : "memory")
#define ARM_DSB() arm_dsb(15)
#define ARM_ISB() arm_isb(15)
#define ARM_DMB() arm_dmb(15)
/****************************************************************************
* Inline Functions
****************************************************************************/
/****************************************************************************
* Name: arm_clz
*
* Description:
* Access to CLZ instructions
*
* Input Parameters:
* value - The value to perform the CLZ operation on
*
* Returned Value:
* None
*
****************************************************************************/
static inline uint32_t arm_clz(unsigned int value)
{
uint32_t ret;
__asm__ __volatile__ ("clz %0, %1" : "=r"(ret) : "r"(value));
return ret;
}
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: up_enable_icache
*
* Description:
* Enable the I-Cache
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
****************************************************************************/
#ifdef CONFIG_ARMV7M_ICACHE
void up_enable_icache(void)
{
uint32_t regval;
ARM_DSB();
ARM_ISB();
/* Invalidate the entire I-Cache */
putreg32(0, NVIC_ICIALLU);
/* Enable the I-Cache */
regval = getreg32(NVIC_CFGCON);
regval |= NVIC_CFGCON_IC;
putreg32(regval, NVIC_CFGCON);
ARM_DSB();
ARM_ISB();
}
#endif
/****************************************************************************
* Name: up_disable_icache
*
* Description:
* Disable the I-Cache
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
****************************************************************************/
#ifdef CONFIG_ARMV7M_ICACHE
void up_disable_icache(void)
{
uint32_t regval;
ARM_DSB();
ARM_ISB();
/* Disable the I-Cache */
regval = getreg32(NVIC_CFGCON);
regval &= ~NVIC_CFGCON_IC;
putreg32(regval, NVIC_CFGCON);
/* Invalidate the entire I-Cache */
putreg32(0, NVIC_ICIALLU);
ARM_DSB();
ARM_ISB();
}
#endif
/****************************************************************************
* Name: up_invalidate_icache_all
*
* Description:
* Invalidate the entire contents of I cache.
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
****************************************************************************/
#ifdef CONFIG_ARMV7M_ICACHE
void up_invalidate_icache_all(void)
{
ARM_DSB();
ARM_ISB();
/* Invalidate the entire I-Cache */
putreg32(0, NVIC_ICIALLU);
ARM_DSB();
ARM_ISB();
}
#endif
/****************************************************************************
* Name: up_enable_dcache
*
* Description:
* Enable the D-Cache
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
****************************************************************************/
#ifdef CONFIG_ARMV7M_DCACHE
void up_enable_dcache(void)
{
uint32_t ccsidr;
uint32_t ccr;
uint32_t sshift;
uint32_t wshift;
uint32_t sw;
uint32_t sets;
uint32_t ways;
/* Get the characteristics of the D-Cache */
ccsidr = getreg32(NVIC_CCSIDR);
sets = CCSIDR_SETS(ccsidr); /* (Number of sets) - 1 */
sshift = CCSIDR_LSSHIFT(ccsidr) + 4; /* log2(cache-line-size-in-bytes) */
ways = CCSIDR_WAYS(ccsidr); /* (Number of ways) - 1 */
/* Calculate the bit offset for the way field in the DCISW register by
* counting the number of leading zeroes. For example:
*
* Number of Value of ways Field
* Ways 'ways' Offset
* 2 1 31
* 4 3 30
* 8 7 29
* ...
*/
wshift = arm_clz(ways) & 0x1f;
/* Invalidate the entire D-Cache */
ARM_DSB();
do
{
int32_t tmpways = ways;
do
{
sw = ((tmpways << wshift) | (sets << sshift));
putreg32(sw, NVIC_DCISW);
}
while (tmpways--);
}
while (sets--);
ARM_DSB();
#ifdef CONFIG_ARMV7M_DCACHE_WRITETHROUGH
ccr = getreg32(NVIC_CACR);
ccr |= NVIC_CACR_FORCEWT;
putreg32(ccr, NVIC_CACR);
#endif
/* Enable the D-Cache */
ccr = getreg32(NVIC_CFGCON);
ccr |= NVIC_CFGCON_DC;
putreg32(ccr, NVIC_CFGCON);
ARM_DSB();
ARM_ISB();
}
#endif /* CONFIG_ARMV7M_DCACHE */
/****************************************************************************
* Name: up_disable_dcache
*
* Description:
* Disable the D-Cache
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
****************************************************************************/
#ifdef CONFIG_ARMV7M_DCACHE
void up_disable_dcache(void)
{
uint32_t ccsidr;
uint32_t ccr;
uint32_t sshift;
uint32_t wshift;
uint32_t sw;
uint32_t sets;
uint32_t ways;
/* Get the characteristics of the D-Cache */
ccsidr = getreg32(NVIC_CCSIDR);
sets = CCSIDR_SETS(ccsidr); /* (Number of sets) - 1 */
sshift = CCSIDR_LSSHIFT(ccsidr) + 4; /* log2(cache-line-size-in-bytes) */
ways = CCSIDR_WAYS(ccsidr); /* (Number of ways) - 1 */
/* Calculate the bit offset for the way field in the DCCISW register by
* counting the number of leading zeroes. For example:
*
* Number of Value of ways Field
* Ways 'ways' Offset
* 2 1 31
* 4 3 30
* 8 7 29
* ...
*/
wshift = arm_clz(ways) & 0x1f;
ARM_DSB();
/* Disable the D-Cache */
ccr = getreg32(NVIC_CFGCON);
ccr &= ~NVIC_CFGCON_DC;
putreg32(ccr, NVIC_CFGCON);
/* Clean and invalidate the entire D-Cache */
do
{
int32_t tmpways = ways;
do
{
sw = ((tmpways << wshift) | (sets << sshift));
putreg32(sw, NVIC_DCCISW);
}
while (tmpways--);
}
while (sets--);
ARM_DSB();
ARM_ISB();
}
#endif /* CONFIG_ARMV7M_DCACHE */
/****************************************************************************
* Name: up_invalidate_dcache
*
* Description:
* Invalidate the data cache within the specified region; we will be
* performing a DMA operation in this region and we want to purge old data
* in the cache. Note that this function invalidates all cache ways
* in sets that could be associated with the address range, regardless of
* whether the address range is contained in the cache or not.
*
* Input Parameters:
* start - virtual start address of region
* end - virtual end address of region + 1
*
* Returned Value:
* None
*
* Assumptions:
* This operation is not atomic. This function assumes that the caller
* has exclusive access to the address range so that no harm is done if
* the operation is pre-empted.
*
****************************************************************************/
#ifdef CONFIG_ARMV7M_DCACHE
void up_invalidate_dcache(uintptr_t start, uintptr_t end)
{
uint32_t ccsidr;
uint32_t sshift;
uint32_t ssize;
/* Get the characteristics of the D-Cache */
ccsidr = getreg32(NVIC_CCSIDR);
sshift = CCSIDR_LSSHIFT(ccsidr) + 4; /* log2(cache-line-size-in-bytes) */
/* Invalidate the D-Cache containing this range of addresses */
ssize = (1 << sshift);
/* Round down the start address to the nearest cache line boundary.
*
* sshift = 5 : Offset to the beginning of the set field
* (ssize - 1) = 0x007f : Mask of the set field
*/
start &= ~(ssize - 1);
ARM_DSB();
do
{
/* The below store causes the cache to check its directory and
* determine if this address is contained in the cache. If so, it
* invalidate that cache line. Only the cache way containing the
* address is invalidated. If the address is not in the cache, then
* nothing is invalidated.
*/
putreg32(start, NVIC_DCIMVAC);
/* Increment the address by the size of one cache line. */
start += ssize;
}
while (start < end);
ARM_DSB();
ARM_ISB();
}
#endif /* CONFIG_ARMV7M_DCACHE */
/****************************************************************************
* Name: up_invalidate_dcache_all
*
* Description:
* Invalidate the entire contents of D cache.
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
****************************************************************************/
#ifdef CONFIG_ARMV7M_DCACHE
void up_invalidate_dcache_all(void)
{
uint32_t ccsidr;
uint32_t sshift;
uint32_t wshift;
uint32_t sw;
uint32_t sets;
uint32_t ways;
/* Get the characteristics of the D-Cache */
ccsidr = getreg32(NVIC_CCSIDR);
sets = CCSIDR_SETS(ccsidr); /* (Number of sets) - 1 */
sshift = CCSIDR_LSSHIFT(ccsidr) + 4; /* log2(cache-line-size-in-bytes) */
ways = CCSIDR_WAYS(ccsidr); /* (Number of ways) - 1 */
/* Calculate the bit offset for the way field in the DCISW register by
* counting the number of leading zeroes. For example:
*
* Number of Value of ways Field
* Ways 'ways' Offset
* 2 1 31
* 4 3 30
* 8 7 29
* ...
*/
wshift = arm_clz(ways) & 0x1f;
ARM_DSB();
/* Invalidate the entire D-Cache */
do
{
int32_t tmpways = ways;
do
{
sw = ((tmpways << wshift) | (sets << sshift));
putreg32(sw, NVIC_DCISW);
}
while (tmpways--);
}
while (sets--);
ARM_DSB();
ARM_ISB();
}
#endif /* CONFIG_ARMV7M_DCACHE */
/****************************************************************************
* Name: up_clean_dcache
*
* Description:
* Clean the data cache within the specified region by flushing the
* contents of the data cache to memory.
*
* NOTE: This operation is un-necessary if the DCACHE is configured in
* write-through mode.
*
* Input Parameters:
* start - virtual start address of region
* end - virtual end address of region + 1
*
* Returned Value:
* None
*
* Assumptions:
* This operation is not atomic. This function assumes that the caller
* has exclusive access to the address range so that no harm is done if
* the operation is pre-empted.
*
****************************************************************************/
#ifdef CONFIG_ARMV7M_DCACHE
void up_clean_dcache(uintptr_t start, uintptr_t end)
{
#ifndef CONFIG_ARMV7M_DCACHE_WRITETHROUGH
uint32_t ccsidr;
uint32_t sshift;
uint32_t ssize;
/* Get the characteristics of the D-Cache */
ccsidr = getreg32(NVIC_CCSIDR);
sshift = CCSIDR_LSSHIFT(ccsidr) + 4; /* log2(cache-line-size-in-bytes) */
/* Clean the D-Cache over the range of addresses */
ssize = (1 << sshift);
start &= ~(ssize - 1);
ARM_DSB();
do
{
/* The below store causes the cache to check its directory and
* determine if this address is contained in the cache. If so, it
* clean that cache line. Only the cache way containing the
* address is invalidated. If the address is not in the cache, then
* nothing is invalidated.
*/
putreg32(start, NVIC_DCCMVAC);
/* Increment the address by the size of one cache line. */
start += ssize;
}
while (start < end);
ARM_DSB();
ARM_ISB();
#endif /* !CONFIG_ARMV7M_DCACHE_WRITETHROUGH */
}
#endif /* CONFIG_ARMV7M_DCACHE */
/****************************************************************************
* Name: up_clean_dcache_all
*
* Description:
* Clean the entire data cache within the specified region by flushing the
* contents of the data cache to memory.
*
* NOTE: This operation is un-necessary if the DCACHE is configured in
* write-through mode.
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
* Assumptions:
* This operation is not atomic. This function assumes that the caller
* has exclusive access to the address range so that no harm is done if
* the operation is pre-empted.
*
****************************************************************************/
#ifdef CONFIG_ARMV7M_DCACHE
void up_clean_dcache_all(void)
{
#ifndef CONFIG_ARMV7M_DCACHE_WRITETHROUGH
uint32_t ccsidr;
uint32_t sshift;
uint32_t wshift;
uint32_t sw;
uint32_t sets;
uint32_t ways;
/* Get the characteristics of the D-Cache */
ccsidr = getreg32(NVIC_CCSIDR);
sets = CCSIDR_SETS(ccsidr); /* (Number of sets) - 1 */
sshift = CCSIDR_LSSHIFT(ccsidr) + 4; /* log2(cache-line-size-in-bytes) */
ways = CCSIDR_WAYS(ccsidr); /* (Number of ways) - 1 */
/* Calculate the bit offset for the way field in the DCCSW register by
* counting the number of leading zeroes. For example:
*
* Number of Value of ways Field
* Ways 'ways' Offset
* 2 1 31
* 4 3 30
* 8 7 29
* ...
*/
wshift = arm_clz(ways) & 0x1f;
ARM_DSB();
/* Clean the entire D-Cache */
do
{
int32_t tmpways = ways;
do
{
sw = ((tmpways << wshift) | (sets << sshift));
putreg32(sw, NVIC_DCCSW);
}
while (tmpways--);
}
while (sets--);
ARM_DSB();
ARM_ISB();
#endif /* !CONFIG_ARMV7M_DCACHE_WRITETHROUGH */
}
#endif /* CONFIG_ARMV7M_DCACHE */
/****************************************************************************
* Name: up_flush_dcache
*
* Description:
* Flush the data cache within the specified region by cleaning and
* invalidating the D cache.
*
* NOTE: If DCACHE write-through is configured, then this operation is the
* same as up_invalidate_cache().
*
* Input Parameters:
* start - virtual start address of region
* end - virtual end address of region + 1
*
* Returned Value:
* None
*
* Assumptions:
* This operation is not atomic. This function assumes that the caller
* has exclusive access to the address range so that no harm is done if
* the operation is pre-empted.
*
****************************************************************************/
#ifdef CONFIG_ARMV7M_DCACHE
void up_flush_dcache(uintptr_t start, uintptr_t end)
{
#ifndef CONFIG_ARMV7M_DCACHE_WRITETHROUGH
uint32_t ccsidr;
uint32_t sshift;
uint32_t ssize;
/* Get the characteristics of the D-Cache */
ccsidr = getreg32(NVIC_CCSIDR);
sshift = CCSIDR_LSSHIFT(ccsidr) + 4; /* log2(cache-line-size-in-bytes) */
/* Clean and invalidate the D-Cache over the range of addresses */
ssize = (1 << sshift);
start &= ~(ssize - 1);
ARM_DSB();
do
{
/* The below store causes the cache to check its directory and
* determine if this address is contained in the cache. If so, it clean
* and invalidate that cache line. Only the cache way containing the
* address is invalidated. If the address is not in the cache, then
* nothing is invalidated.
*/
putreg32(start, NVIC_DCCIMVAC);
/* Increment the address by the size of one cache line. */
start += ssize;
}
while (start < end);
ARM_DSB();
ARM_ISB();
#else
up_invalidate_dcache(start, end);
#endif /* !CONFIG_ARMV7M_DCACHE_WRITETHROUGH */
}
#endif /* CONFIG_ARMV7M_DCACHE */
/****************************************************************************
* Name: up_flush_dcache_all
*
* Description:
* Flush the entire data cache by cleaning and invalidating the D cache.
*
* NOTE: If DCACHE write-through is configured, then this operation is the
* same as up_invalidate_cache_all().
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
* Assumptions:
* This operation is not atomic. This function assumes that the caller
* has exclusive access to the address range so that no harm is done if
* the operation is pre-empted.
*
****************************************************************************/
#ifdef CONFIG_ARMV7M_DCACHE
void up_flush_dcache_all(void)
{
#ifndef CONFIG_ARMV7M_DCACHE_WRITETHROUGH
uint32_t ccsidr;
uint32_t sshift;
uint32_t wshift;
uint32_t sw;
uint32_t sets;
uint32_t ways;
/* Get the characteristics of the D-Cache */
ccsidr = getreg32(NVIC_CCSIDR);
sets = CCSIDR_SETS(ccsidr); /* (Number of sets) - 1 */
sshift = CCSIDR_LSSHIFT(ccsidr) + 4; /* log2(cache-line-size-in-bytes) */
ways = CCSIDR_WAYS(ccsidr); /* (Number of ways) - 1 */
/* Calculate the bit offset for the way field in the DCCISW register by
* counting the number of leading zeroes. For example:
*
* Number of Value of ways Field
* Ways 'ways' Offset
* 2 1 31
* 4 3 30
* 8 7 29
* ...
*/
wshift = arm_clz(ways) & 0x1f;
ARM_DSB();
/* Clean and invalidate the entire D-Cache */
do
{
int32_t tmpways = ways;
do
{
sw = ((tmpways << wshift) | (sets << sshift));
putreg32(sw, NVIC_DCCISW);
}
while (tmpways--);
}
while (sets--);
ARM_DSB();
ARM_ISB();
#else
up_invalidate_dcache_all();
#endif /* !CONFIG_ARMV7M_DCACHE_WRITETHROUGH */
}
#endif /* CONFIG_ARMV7M_DCACHE */
/****************************************************************************
* Name: up_coherent_dcache
*
* Description:
* Ensure that the I and D caches are coherent within specified region
* by cleaning the D cache (i.e., flushing the D cache contents to memory
* and invalidating the I cache. This is typically used when code has been
* written to a memory region, and will be executed.
*
* Input Parameters:
* addr - virtual start address of region
* len - Size of the address region in bytes
*
* Returned Value:
* None
*
****************************************************************************/
#ifdef CONFIG_ARMV7M_ICACHE
void up_coherent_dcache(uintptr_t addr, size_t len)
{
uintptr_t end;
if (len > 0)
{
/* Flush any dirtcy D-Cache lines to memory */
end = addr + len;
up_clean_dcache(addr, end);
UNUSED(end);
/* Invalidate the entire I-Cache */
up_invalidate_icache_all();
}
}
#endif

87
arch/arm/src/armv7-m/up_coherent_dcache.c
View file

@ -1,87 +0,0 @@
/****************************************************************************
* arch/arm/src/armv7-m/up_coherent_dcache.c
*
* Copyright (C) 2015 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <sys/types.h>
#include <stdint.h>
#include "cache.h"
#include <nuttx/arch.h>
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: up_coherent_dcache
*
* Description:
* Ensure that the I and D caches are coherent within specified region
* by cleaning the D cache (i.e., flushing the D cache contents to memory
* and invalidating the I cache. This is typically used when code has been
* written to a memory region, and will be executed.
*
* Input Parameters:
* addr - virtual start address of region
* len - Size of the address region in bytes
*
* Returned Value:
* None
*
****************************************************************************/
void up_coherent_dcache(uintptr_t addr, size_t len)
{
uintptr_t end;
if (len > 0)
{
/* Flush any dirtcy D-Cache lines to memory */
end = addr + len;
arch_clean_dcache(addr, end);
UNUSED(end);
/* Invalidate the entire I-Cache */
arch_invalidate_icache_all();
}
}

23
arch/arm/src/armv7-r/Kconfig
View file

@ -26,29 +26,6 @@ config ARMV7R_MEMINIT
the memory initialization first, then explicitly call
arm_data_initialize().
config ARMV7R_HAVE_ICACHE
bool
default n
config ARMV7R_HAVE_DCACHE
bool
default n
config ARMV7R_ICACHE
bool "Use I-Cache"
default n
depends on ARMV7R_HAVE_ICACHE
config ARMV7R_DCACHE
bool "Use D-Cache"
default n
depends on ARMV7R_HAVE_DCACHE
config ARMV7R_DCACHE_WRITETHROUGH
bool "D-Cache Write-Through"
default n
depends on ARMV7R_DCACHE
config ARMV7R_HAVE_L2CC
bool
default n

172
arch/arm/src/armv7-a/cache.h → arch/arm/src/armv7-r/arm_cache.c
View file

@ -1,7 +1,7 @@
/************************************************************************************
* arch/arm/src/armv7-a/cache.h
/****************************************************************************
* arch/arm/src/armv7-r/arm_cache.c
*
* Copyright (C) 2014 Gregory Nutt. All rights reserved.
* Copyright (C) 2015, 2019 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
@ -31,24 +31,22 @@
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_SRC_ARMV7_A_CACHE_H
#define __ARCH_ARM_SRC_ARMV7_A_CACHE_H
/************************************************************************************
/****************************************************************************
* Included Files
************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
#include <nuttx/cache.h>
#include <nuttx/irq.h>
#include "cp15_cacheops.h"
#include "l2cc.h"
/************************************************************************************
/****************************************************************************
* Pre-processor Definitions
************************************************************************************/
****************************************************************************/
/* Intrinsics are used in these inline functions */
@ -60,14 +58,12 @@
#define ARM_ISB() arm_isb(15)
#define ARM_DMB() arm_dmb(15)
/************************************************************************************
* Inline Functions
************************************************************************************/
#ifndef __ASSEMBLY__
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: arch_invalidate_dcache
* Name: up_invalidate_dcache
*
* Description:
* Invalidate the data cache within the specified region; we will be
@ -88,14 +84,14 @@
*
****************************************************************************/
static inline void arch_invalidate_dcache(uintptr_t start, uintptr_t end)
void up_invalidate_dcache(uintptr_t start, uintptr_t end)
{
cp15_invalidate_dcache(start, end);
l2cc_invalidate(start, end);
}
/****************************************************************************
* Name: arch_invalidate_dcache_all
* Name: up_invalidate_dcache_all
*
* Description:
* Invalidate the entire contents of D cache.
@ -111,7 +107,7 @@ static inline void arch_invalidate_dcache(uintptr_t start, uintptr_t end)
*
****************************************************************************/
static inline void arch_invalidate_dcache_all(void)
void up_invalidate_dcache_all(void)
{
#ifdef CONFIG_ARCH_L2CACHE
irqstate_t flags = enter_critical_section();
@ -123,11 +119,12 @@ static inline void arch_invalidate_dcache_all(void)
#endif
}
/************************************************************************************
* Name: arch_invalidate_icache
/****************************************************************************
* Name: up_invalidate_icache_all
*
* Description:
* Invalidate all instruction caches to PoU, also flushes branch target cache
* Invalidate all instruction caches to PoU, also flushes branch target
* cache
*
* Input Parameters:
* None
@ -135,12 +132,15 @@ static inline void arch_invalidate_dcache_all(void)
* Returned Value:
* None
*
************************************************************************************/
****************************************************************************/
#define arch_invalidate_icache() cp15_invalidate_icache()
void up_invalidate_icache_all(void)
{
cp15_invalidate_icache();
}
/****************************************************************************
* Name: arch_clean_dcache
* Name: up_clean_dcache
*
* Description:
* Clean the data cache within the specified region by flushing the
@ -160,14 +160,14 @@ static inline void arch_invalidate_dcache_all(void)
*
****************************************************************************/
static inline void arch_clean_dcache(uintptr_t start, uintptr_t end)
void up_clean_dcache(uintptr_t start, uintptr_t end)
{
cp15_clean_dcache(start, end);
l2cc_clean(start, end);
}
/****************************************************************************
* Name: arch_flush_dcache
* Name: up_flush_dcache
*
* Description:
* Flush the data cache within the specified region by cleaning and
@ -187,32 +187,120 @@ static inline void arch_clean_dcache(uintptr_t start, uintptr_t end)
*
****************************************************************************/
static inline void arch_flush_dcache(uintptr_t start, uintptr_t end)
void up_flush_dcache(uintptr_t start, uintptr_t end)
{
cp15_flush_dcache(start, end);
l2cc_flush(start, end);
}
/****************************************************************************
* Public Data
* Name: up_enable_icache
*
* Description:
* Enable the I-Cache
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
****************************************************************************/
#ifdef __cplusplus
#define EXTERN extern "C"
extern "C"
void up_enable_icache(void)
{
#else
#define EXTERN extern
#endif
cp15_enable_icache();
}
/****************************************************************************
* Public Function Prototypes
* Name: up_disable_icache
*
* Description:
* Disable the I-Cache
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
****************************************************************************/
#undef EXTERN
#ifdef __cplusplus
void up_disable_icache(void)
{
cp15_disable_icache();
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_ARM_SRC_ARMV7_A_CACHE_H */
/****************************************************************************
* Name: up_enable_dcache
*
* Description:
* Enable the D-Cache
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
****************************************************************************/
void up_enable_dcache(void)
{
cp15_enable_dcache();
l2cc_enable();
}
/****************************************************************************
* Name: up_disable_dcache
*
* Description:
* Disable the D-Cache
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
****************************************************************************/
void up_disable_dcache(void)
{
cp15_disable_dcache();
l2cc_disable();
}
/****************************************************************************
* Name: up_coherent_dcache
*
* Description:
* Ensure that the I and D caches are coherent within specified region
* by cleaning the D cache (i.e., flushing the D cache contents to memory
* and invalidating the I cache. This is typically used when code has been
* written to a memory region, and will be executed.
*
* Input Parameters:
* addr - virtual start address of region
* len - Size of the address region in bytes
*
* Returned Value:
* None
*
****************************************************************************/
void up_coherent_dcache(uintptr_t addr, size_t len)
{
if (len > 0)
{
/* Perform the operation on the L1 cache */
cp15_coherent_dcache(addr, addr + len);
#ifdef CONFIG_ARCH_L2CACHE
/* If we have an L2 cache, then there more things that need to done */
# warning This is insufficient
#endif
}
}

97
arch/arm/src/armv7-r/arm_coherent_dcache.c
View file

@ -1,97 +0,0 @@
/****************************************************************************
* arch/arm/src/armv7-r/up_coherent_dcache.c
*
* Copyright (C) 2015 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <sys/types.h>
#include <stdint.h>
#include "cp15_cacheops.h"
#include <nuttx/arch.h>
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/****************************************************************************
* Private Data
****************************************************************************/
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: up_coherent_dcache
*
* Description:
* Ensure that the I and D caches are coherent within specified region
* by cleaning the D cache (i.e., flushing the D cache contents to memory
* and invalidating the I cache. This is typically used when code has been
* written to a memory region, and will be executed.
*
* Input Parameters:
* addr - virtual start address of region
* len - Size of the address region in bytes
*
* Returned Value:
* None
*
****************************************************************************/
void up_coherent_dcache(uintptr_t addr, size_t len)
{
if (len > 0)
{
/* Perform the operation on the L1 cache */
cp15_coherent_dcache(addr, addr + len - 1);
#ifdef CONFIG_ARCH_L2CACHE
/* If we have an L2 cache, then there more things that need to done */
# warning This is insufficient
#endif
}
}

2
arch/arm/src/armv7-r/arm_head.S
View file

@ -467,7 +467,7 @@ arm_data_initialize:
adr r3, ..Lramfunc
ldmia r3, {r0, r1}
ldr r3, =arch_clean_dcache
ldr r3, =up_clean_dcache
b r3
#else
/* Otherwise return to the caller */

110
arch/arm/src/armv7-r/cp15_cacheops.h
View file

@ -201,6 +201,26 @@
#ifdef __ASSEMBLY__
/************************************************************************************
* Name: cp15_enable_dcache
*
* Description:
* Enable L1 D Cache
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
************************************************************************************/
.macro cp15_enable_dcache, tmp
mrc p15, 0, \tmp, c1, c0, 0 /* Read SCTLR */
orr \tmp, \tmp, #(0x1 << 2) /* Enable D cache */
mcr p15, 0, \tmp, c1, c0, 0 /* Update the SCTLR */
.endm
/************************************************************************************
* Name: cp15_disable_dcache
*
@ -222,10 +242,10 @@
.endm
/************************************************************************************
* Name: cp15_disable_caches
* Name: cp15_enable_icache
*
* Description:
* Disable L1 Caches
* Enable L1 I Cache
*
* Input Parameters:
* None
@ -235,10 +255,29 @@
*
************************************************************************************/
.macro cp15_disable_caches, tmp
.macro cp15_enable_icache, tmp
mrc p15, 0, \tmp, c1, c0, 0 /* Read SCTLR */
orr \tmp, \tmp, #(0x1 << 12) /* Enable I cache */
mcr p15, 0, \tmp, c1, c0, 0 /* Update the SCTLR */
.endm
/************************************************************************************
* Name: cp15_disable_icache
*
* Description:
* Disable L1 I Cache
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
************************************************************************************/
.macro cp15_disable_icache, tmp
mrc p15, 0, \tmp, c1, c0, 0 /* Read SCTLR */
bic \tmp, \tmp, #(0x1 << 12) /* Disable I cache */
bic \tmp, \tmp, #(0x1 << 2) /* Disable D cache */
mcr p15, 0, \tmp, c1, c0, 0 /* Update the SCTLR */
.endm
@ -489,11 +528,38 @@
#ifndef __ASSEMBLY__
/************************************************************************************
* Name: cp15_enable_dcache
*
* Description:
* Enable L1 D Cache
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
************************************************************************************/
static inline void cp15_enable_dcache(void)
{
__asm__ __volatile__
(
"\tmrc p15, 0, r0, c1, c0, 0\n" /* Read SCTLR */
"\torr r0, r0, #(1 << 2)\n" /* Enable D cache */
"\tmcr p15, 0, r0, c1, c0, 0\n" /* Update the SCTLR */
:
:
: "r0", "memory"
);
}
/************************************************************************************
* Name: cp15_disable_dcache
*
* Description:
* Disable L1 Caches
* Disable L1 D Cache
*
* Input Parameters:
* None
@ -517,10 +583,10 @@ static inline void cp15_disable_dcache(void)
}
/************************************************************************************
* Name: cp15_disable_caches
* Name: cp15_enable_icache
*
* Description:
* Disable L1 Caches
* Enable L1 I Cache
*
* Input Parameters:
* None
@ -530,13 +596,39 @@ static inline void cp15_disable_dcache(void)
*
************************************************************************************/
static inline void cp15_disable_caches(void)
static inline void cp15_enable_icache(void)
{
__asm__ __volatile__
(
"\tmrc p15, 0, r0, c1, c0, 0\n" /* Read SCTLR */
"\torr r0, r0, #(1 << 12)\n" /* Enable I cache */
"\tmcr p15, 0, r0, c1, c0, 0\n" /* Update the SCTLR */
:
:
: "r0", "memory"
);
}
/************************************************************************************
* Name: cp15_disable_icache
*
* Description:
* Disable L1 I Cache
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
************************************************************************************/
static inline void cp15_disable_icache(void)
{
__asm__ __volatile__
(
"\tmrc p15, 0, r0, c1, c0, 0\n" /* Read SCTLR */
"\tbic r0, r0, #(1 << 12)\n" /* Disable I cache */
"\tbic r0, r0, #(1 << 2)\n" /* Disable D cache */
"\tmcr p15, 0, r0, c1, c0, 0\n" /* Update the SCTLR */
:
:

3
arch/arm/src/armv7-r/mpu.h
View file

@ -49,7 +49,6 @@
# include <debug.h>
# include "up_arch.h"
# include "cache.h"
# include "sctlr.h"
# include "cp15.h"
#endif
@ -410,7 +409,6 @@ static inline void mpu_control(bool enable)
*
****************************************************************************/
#if defined(CONFIG_ARMV7R_HAVE_ICACHE) || defined(CONFIG_ARMV7R_DCACHE)
static inline void mpu_priv_stronglyordered(uintptr_t base, size_t size)
{
unsigned int region = mpu_allocregion();
@ -444,7 +442,6 @@ static inline void mpu_priv_stronglyordered(uintptr_t base, size_t size)
((uint32_t)subregions << MPU_RASR_SRD_SHIFT); /* Sub-regions */
mpu_set_drsr(regval);
}
#endif
/****************************************************************************
* Name: mpu_user_flash

6
arch/arm/src/imx6/Make.defs
View file

@ -123,11 +123,7 @@ CMN_CSRCS += arm_virtpgaddr.c
endif
endif
ifeq ($(CONFIG_ELF),y)
CMN_CSRCS += arm_coherent_dcache.c
else ifeq ($(CONFIG_MODULE),y)
CMN_CSRCS += arm_coherent_dcache.c
endif
CMN_CSRCS += arm_cache.c
ifeq ($(CONFIG_ARCH_FPU),y)
CMN_ASRCS += arm_savefpu.S arm_restorefpu.S

6
arch/arm/src/imx6/imx_boot.c
View file

@ -43,6 +43,7 @@
#include <assert.h>
#include <debug.h>
#include <nuttx/cache.h>
#ifdef CONFIG_PAGING
# include <nuttx/page.h>
#endif
@ -53,7 +54,6 @@
#include "arm.h"
#include "mmu.h"
#include "scu.h"
#include "cache.h"
#include "fpu.h"
#include "up_internal.h"
#include "up_arch.h"
@ -287,7 +287,7 @@ static void imx_copyvectorblock(void)
#else
/* Flush the DCache to assure that the vector data is in physical RAM */
arch_clean_dcache((uintptr_t)IMX_VECTOR_VSRAM,
up_clean_dcache((uintptr_t)IMX_VECTOR_VSRAM,
(uintptr_t)IMX_VECTOR_VSRAM + imx_vectorsize());
#endif
}
@ -453,7 +453,7 @@ void arm_boot(void)
* be available when fetched into the I-Cache.
*/
arch_clean_dcache((uintptr_t)&_sramfuncs, (uintptr_t)&_eramfuncs)
up_clean_dcache((uintptr_t)&_sramfuncs, (uintptr_t)&_eramfuncs)
PROGRESS('F');
#endif

9
arch/arm/src/imxrt/Make.defs
View file

@ -79,14 +79,7 @@ ifeq ($(CONFIG_STACK_COLORATION),y)
CMN_CSRCS += up_checkstack.c
endif
ifeq ($(CONFIG_ARMV7M_DCACHE),y)
CMN_CSRCS += arch_enable_dcache.c arch_disable_dcache.c
CMN_CSRCS += arch_invalidate_dcache.c arch_invalidate_dcache_all.c
ifneq ($(CONFIG_ARMV7M_DCACHE_WRITETHROUGH),y)
CMN_CSRCS += arch_clean_dcache.c arch_clean_dcache_all.c
CMN_CSRCS += arch_flush_dcache.c arch_flush_dcache_all.c
endif
endif
CMN_CSRCS += up_cache.c
ifeq ($(CONFIG_ARCH_FPU),y)
CMN_ASRCS += up_fpu.S

9
arch/arm/src/imxrt/imxrt_edma.c
View file

@ -58,7 +58,6 @@
#include <nuttx/arch.h>
#include "up_arch.h"
#include "cache.h"
#include "up_internal.h"
#include "sched/sched.h"
@ -1105,7 +1104,7 @@ int imxrt_dmach_xfrsetup(DMACH_HANDLE *handle,
/* Clean cache associated with the previous TCD memory */
arch_clean_dcache((uintptr_t)prev,
up_clean_dcache((uintptr_t)prev,
(uintptr_t)prev + sizeof(struct imxrt_edmatcd_s));
/* Check if the TCD block in the DMA channel registers is the same as
@ -1130,7 +1129,7 @@ int imxrt_dmach_xfrsetup(DMACH_HANDLE *handle,
/* Clean cache associated with the TCD memory */
arch_clean_dcache((uintptr_t)tcd,
up_clean_dcache((uintptr_t)tcd,
(uintptr_t)tcd + sizeof(struct imxrt_edmatcd_s));
#else
/* Scatter/gather DMA is NOT supported */
@ -1168,7 +1167,7 @@ int imxrt_dmach_xfrsetup(DMACH_HANDLE *handle,
* is one.
*/
arch_invalidate_dcache((uintptr_t)config->daddr,
up_invalidate_dcache((uintptr_t)config->daddr,
(uintptr_t)config->daddr + config->nbytes);
}
@ -1183,7 +1182,7 @@ int imxrt_dmach_xfrsetup(DMACH_HANDLE *handle,
*/
#warning Missing logic
arch_clean_dcache((uintptr_t)config->saddr,
up_clean_dcache((uintptr_t)config->saddr,
(uintptr_t)config->saddr + config->nbytes);
}

9
arch/arm/src/imxrt/imxrt_enet.c
View file

@ -64,7 +64,6 @@
#endif
#include "up_arch.h"
#include "cache.h"
#include "chip.h"
#include "imxrt_config.h"
#include "chip/imxrt_enet.h"
@ -502,7 +501,7 @@ static int imxrt_transmit(FAR struct imxrt_driver_s *priv)
}
#ifdef CONFIG_DEBUG_ASSERTIONS
arch_invalidate_dcache((uintptr_t)txdesc,
up_invalidate_dcache((uintptr_t)txdesc,
(uintptr_t)txdesc + sizeof(struct enet_desc_s));
DEBUGASSERT(priv->txtail != priv->txhead &&
@ -816,7 +815,7 @@ static void imxrt_receive(FAR struct imxrt_driver_s *priv)
*/
rxdesc = &priv->rxdesc[priv->rxtail];
arch_invalidate_dcache((uintptr_t)rxdesc,
up_invalidate_dcache((uintptr_t)rxdesc,
(uintptr_t)rxdesc + sizeof(struct enet_desc_s));
/* Check if the data buffer associated with the descriptor has
@ -837,7 +836,7 @@ static void imxrt_receive(FAR struct imxrt_driver_s *priv)
* from memory when the packet content is accessed.
*/
arch_invalidate_dcache((uintptr_t)priv->dev.d_buf,
up_invalidate_dcache((uintptr_t)priv->dev.d_buf,
(uintptr_t)priv->dev.d_buf + priv->dev.d_len);
/* Dispatch (or drop) the newly received packet */
@ -911,7 +910,7 @@ static void imxrt_txdone(FAR struct imxrt_driver_s *priv)
*/
txdesc = &priv->txdesc[priv->txtail];
arch_invalidate_dcache((uintptr_t)txdesc,
up_invalidate_dcache((uintptr_t)txdesc,
(uintptr_t)txdesc + sizeof(struct enet_desc_s));
txdone = false;

1
arch/arm/src/imxrt/imxrt_lpspi.c
View file

@ -82,7 +82,6 @@
#include "up_internal.h"
#include "up_arch.h"
#include "cache.h"
#include "chip.h"
#include "imxrt_lpspi.h"

1
arch/arm/src/imxrt/imxrt_mpuinit.c
View file

@ -44,7 +44,6 @@
#include <nuttx/userspace.h>
#include "mpu.h"
#include "cache.h"
#include "chip/imxrt_memorymap.h"
#include "imxrt_mpuinit.h"

7
arch/arm/src/imxrt/imxrt_start.c
View file

@ -43,13 +43,13 @@
#include <assert.h>
#include <debug.h>
#include <nuttx/cache.h>
#include <nuttx/init.h>
#include <arch/board/board.h>
#include "up_arch.h"
#include "up_internal.h"
#include "cache.h"
#ifdef CONFIG_ARCH_FPU
# include "nvic.h"
#endif
@ -377,9 +377,8 @@ void __start(void)
/* Enable I- and D-Caches */
arch_dcache_writethrough();
arch_enable_icache();
arch_enable_dcache();
up_enable_icache();
up_enable_dcache();
/* Perform early serial initialization */

3
arch/arm/src/imxrt/imxrt_usdhc.c
View file

@ -59,7 +59,6 @@
#include <nuttx/irq.h>
#include <arch/board/board.h>
#include "cache.h"
#include "chip.h"
#include "up_arch.h"
@ -996,7 +995,7 @@ static void imxrt_endtransfer(struct imxrt_dev_s *priv,
/* DMA modified the buffer, so we need to flush its cache lines. */
arch_invalidate_dcache((uintptr_t)priv->buffer,
up_invalidate_dcache((uintptr_t)priv->buffer,
(uintptr_t)priv->bufferend);
/* Debug instrumentation */

3
arch/arm/src/kinetis/kinetis_serial.c
View file

@ -61,7 +61,6 @@
#include <arch/board/board.h>
#include "cache.h"
#include "up_arch.h"
#include "up_internal.h"
@ -1582,7 +1581,7 @@ static int up_dma_receive(struct uart_dev_s *dev, unsigned int *status)
{
/* Invalidate the DMA buffer */
arch_invalidate_dcache((uintptr_t)priv->rxfifo,
up_invalidate_dcache((uintptr_t)priv->rxfifo,
(uintptr_t)priv->rxfifo + RXDMA_BUFFER_SIZE);
/* Now read from the DMA buffer */

43
arch/arm/src/lpc31xx/lpc31_ehci.c
View file

@ -61,8 +61,6 @@
#include <nuttx/usb/usbhost_trace.h>
#include "up_arch.h"
#include "cache.h"
#include "chip.h"
#include "lpc31.h"
#include "lpc31_cgudrvr.h"
@ -1371,7 +1369,7 @@ static int lpc31_qtd_invalidate(struct lpc31_qtd_s *qtd, uint32_t **bp, void *ar
* memory over the specified address range.
*/
cp15_invalidate_dcache((uintptr_t)&qtd->hw,
up_invalidate_dcache((uintptr_t)&qtd->hw,
(uintptr_t)&qtd->hw + sizeof(struct ehci_qtd_s));
return OK;
}
@ -1390,7 +1388,7 @@ static int lpc31_qh_invalidate(struct lpc31_qh_s *qh)
{
/* Invalidate the QH first so that we reload the qTD list head */
cp15_invalidate_dcache((uintptr_t)&qh->hw,
up_invalidate_dcache((uintptr_t)&qh->hw,
(uintptr_t)&qh->hw + sizeof(struct ehci_qh_s));
/* Then invalidate all of the qTD entries in the queue */
@ -1415,9 +1413,7 @@ static int lpc31_qtd_flush(struct lpc31_qtd_s *qtd, uint32_t **bp, void *arg)
* to force re-loading of the data from memory when next accessed.
*/
cp15_flush_idcache((uintptr_t)&qtd->hw,
(uintptr_t)&qtd->hw + sizeof(struct ehci_qtd_s));
cp15_invalidate_dcache((uintptr_t)&qtd->hw,
up_flush_dcache((uintptr_t)&qtd->hw,
(uintptr_t)&qtd->hw + sizeof(struct ehci_qtd_s));
return OK;
@ -1438,9 +1434,7 @@ static int lpc31_qh_flush(struct lpc31_qh_s *qh)
* reloaded from D-Cache.
*/
cp15_flush_idcache((uintptr_t)&qh->hw,
(uintptr_t)&qh->hw + sizeof(struct ehci_qh_s));
cp15_invalidate_dcache((uintptr_t)&qh->hw,
up_flush_dcache((uintptr_t)&qh->hw,
(uintptr_t)&qh->hw + sizeof(struct ehci_qh_s));
/* Then flush all of the qTD entries in the queue */
@ -1672,7 +1666,7 @@ static void lpc31_qh_enqueue(struct lpc31_qh_s *qhead, struct lpc31_qh_s *qh)
physaddr = (uintptr_t)lpc31_physramaddr((uintptr_t)qh);
qhead->hw.hlp = lpc31_swap32(physaddr | QH_HLP_TYP_QH);
cp15_flush_idcache((uintptr_t)&qhead->hw,
up_clean_dcache((uintptr_t)&qhead->hw,
(uintptr_t)&qhead->hw + sizeof(struct ehci_qh_s));
}
@ -1832,8 +1826,7 @@ static int lpc31_qtd_addbpl(struct lpc31_qtd_s *qtd, const void *buffer, size_t
* will be accessed for an OUT DMA.
*/
cp15_flush_idcache((uintptr_t)buffer, (uintptr_t)buffer + buflen);
cp15_invalidate_dcache((uintptr_t)buffer, (uintptr_t)buffer + buflen);
up_flush_dcache((uintptr_t)buffer, (uintptr_t)buffer + buflen);
/* Loop, adding the aligned physical addresses of the buffer to the buffer page
* list. Only the first entry need not be aligned (because only the first
@ -2523,7 +2516,7 @@ static ssize_t lpc31_transfer_wait(struct lpc31_epinfo_s *epinfo)
* invalid in this memory region.
*/
cp15_invalidate_dcache((uintptr_t)buffer, (uintptr_t)buffer + buflen);
up_invalidate_dcache((uintptr_t)buffer, (uintptr_t)buffer + buflen);
}
#endif
@ -2673,7 +2666,7 @@ static int lpc31_qtd_ioccheck(struct lpc31_qtd_s *qtd, uint32_t **bp, void *arg)
/* Make sure we reload the QH from memory */
cp15_invalidate_dcache((uintptr_t)&qtd->hw,
up_invalidate_dcache((uintptr_t)&qtd->hw,
(uintptr_t)&qtd->hw + sizeof(struct ehci_qtd_s));
lpc31_qtd_print(qtd);
@ -2724,7 +2717,7 @@ static int lpc31_qh_ioccheck(struct lpc31_qh_s *qh, uint32_t **bp, void *arg)
/* Make sure we reload the QH from memory */
cp15_invalidate_dcache((uintptr_t)&qh->hw,
up_invalidate_dcache((uintptr_t)&qh->hw,
(uintptr_t)&qh->hw + sizeof(struct ehci_qh_s));
lpc31_qh_print(qh);
@ -2778,7 +2771,7 @@ static int lpc31_qh_ioccheck(struct lpc31_qh_s *qh, uint32_t **bp, void *arg)
*/
**bp = qh->hw.hlp;
cp15_flush_idcache((uintptr_t)*bp, (uintptr_t)*bp + sizeof(uint32_t));
up_clean_dcache((uintptr_t)*bp, (uintptr_t)*bp + sizeof(uint32_t));
/* Check for errors, update the data toggle */
@ -2878,7 +2871,7 @@ static int lpc31_qtd_cancel(struct lpc31_qtd_s *qtd, uint32_t **bp, void *arg)
/* Make sure we reload the QH from memory */
cp15_invalidate_dcache((uintptr_t)&qtd->hw,
up_invalidate_dcache((uintptr_t)&qtd->hw,
(uintptr_t)&qtd->hw + sizeof(struct ehci_qtd_s));
lpc31_qtd_print(qtd);
@ -2923,7 +2916,7 @@ static int lpc31_qh_cancel(struct lpc31_qh_s *qh, uint32_t **bp, void *arg)
/* Make sure we reload the QH from memory */
cp15_invalidate_dcache((uintptr_t)&qh->hw,
up_invalidate_dcache((uintptr_t)&qh->hw,
(uintptr_t)&qh->hw + sizeof(struct ehci_qh_s));
lpc31_qh_print(qh);
@ -2953,7 +2946,7 @@ static int lpc31_qh_cancel(struct lpc31_qh_s *qh, uint32_t **bp, void *arg)
*/
**bp = qh->hw.hlp;
cp15_flush_idcache((uintptr_t)*bp, (uintptr_t)*bp + sizeof(uint32_t));
up_clean_dcache((uintptr_t)*bp, (uintptr_t)*bp + sizeof(uint32_t));
/* Re-enable the schedules (if they were enabled before. */
@ -3003,7 +2996,7 @@ static inline void lpc31_ioc_bottomhalf(void)
/* Check the Asynchronous Queue */
/* Make sure that the head of the asynchronous queue is invalidated */
cp15_invalidate_dcache((uintptr_t)&g_asynchead.hw,
up_invalidate_dcache((uintptr_t)&g_asynchead.hw,
(uintptr_t)&g_asynchead.hw + sizeof(struct ehci_qh_s));
/* Set the back pointer to the forward QH pointer of the asynchronous
@ -3034,7 +3027,7 @@ static inline void lpc31_ioc_bottomhalf(void)
/* Check the Interrupt Queue */
/* Make sure that the head of the interrupt queue is invalidated */
cp15_invalidate_dcache((uintptr_t)&g_intrhead.hw,
up_invalidate_dcache((uintptr_t)&g_intrhead.hw,
(uintptr_t)&g_intrhead.hw + sizeof(struct ehci_qh_s));
/* Set the back pointer to the forward qTD pointer of the asynchronous
@ -5200,7 +5193,7 @@ FAR struct usbhost_connection_s *lpc31_ehci_initialize(int controller)
g_asynchead.hw.overlay.token = lpc31_swap32(QH_TOKEN_HALTED);
g_asynchead.fqp = lpc31_swap32(QTD_NQP_T);
cp15_flush_idcache((uintptr_t)&g_asynchead.hw,
up_clean_dcache((uintptr_t)&g_asynchead.hw,
(uintptr_t)&g_asynchead.hw + sizeof(struct ehci_qh_s));
/* Set the Current Asynchronous List Address. */
@ -5231,9 +5224,9 @@ FAR struct usbhost_connection_s *lpc31_ehci_initialize(int controller)
/* Set the Periodic Frame List Base Address. */
cp15_flush_idcache((uintptr_t)&g_intrhead.hw,
up_clean_dcache((uintptr_t)&g_intrhead.hw,
(uintptr_t)&g_intrhead.hw + sizeof(struct ehci_qh_s));
cp15_flush_idcache((uintptr_t)g_framelist,
up_clean_dcache((uintptr_t)g_framelist,
(uintptr_t)g_framelist + FRAME_LIST_SIZE * sizeof(uint32_t));
physaddr = lpc31_physramaddr((uintptr_t)g_framelist);

1
arch/arm/src/lpc43xx/lpc43_can.c
View file

@ -52,7 +52,6 @@
#include "up_internal.h"
#include "up_arch.h"
#include "cache.h"
#include "chip.h"
#include "lpc43_gpio.h"

1
arch/arm/src/nrf52/nrf52_nvmc.c
View file

@ -44,7 +44,6 @@
#include <nuttx/config.h>
#include <stdbool.h>
#include "cache.h"
#include "chip/nrf52_ficr.h"
#include "chip/nrf52_nvmc.h"

6
arch/arm/src/sama5/Make.defs
View file

@ -113,11 +113,7 @@ CMN_CSRCS += arm_virtpgaddr.c
endif
endif
ifeq ($(CONFIG_ELF),y)
CMN_CSRCS += arm_coherent_dcache.c
else ifeq ($(CONFIG_MODULE),y)
CMN_CSRCS += arm_coherent_dcache.c
endif
CMN_CSRCS += arm_cache.c
ifeq ($(CONFIG_ARCH_FPU),y)
CMN_ASRCS += arm_savefpu.S arm_restorefpu.S

3
arch/arm/src/sama5/sam_adc.c
View file

@ -71,7 +71,6 @@
#include "up_arch.h"
#include "chip.h"
#include "cache.h"
#include "chip/sam_adc.h"
#include "chip/sam_pmc.h"
#include "chip/sam_pinmap.h"
@ -662,7 +661,7 @@ static void sam_adc_dmadone(void *arg)
* newly DMAed data from RAM.
*/
arch_invalidate_dcache((uintptr_t)buffer,
up_invalidate_dcache((uintptr_t)buffer,
(uintptr_t)buffer + SAMA5_ADC_SAMPLES * sizeof(uint16_t));
/* Process each sample */

6
arch/arm/src/sama5/sam_boot.c
View file

@ -43,6 +43,7 @@
#include <assert.h>
#include <debug.h>
#include <nuttx/cache.h>
#ifdef CONFIG_PAGING
# include <nuttx/page.h>
#endif
@ -52,7 +53,6 @@
#include "chip.h"
#include "arm.h"
#include "mmu.h"
#include "cache.h"
#include "fpu.h"
#include "up_internal.h"
#include "up_arch.h"
@ -283,7 +283,7 @@ static void sam_copyvectorblock(void)
#else
/* Flush the DCache to assure that the vector data is in physical in ISRAM */
arch_clean_dcache((uintptr_t)SAM_VECTOR_VSRAM,
up_clean_dcache((uintptr_t)SAM_VECTOR_VSRAM,
(uintptr_t)SAM_VECTOR_VSRAM + sam_vectorsize());
#endif
}
@ -457,7 +457,7 @@ void arm_boot(void)
* be available when fetched into the I-Cache.
*/
arch_clean_dcache((uintptr_t)&_sramfuncs, (uintptr_t)&_eramfuncs)
up_clean_dcache((uintptr_t)&_sramfuncs, (uintptr_t)&_eramfuncs)
#endif
/* Setup up vector block. _vector_start and _vector_end are exported from

9
arch/arm/src/sama5/sam_dmac.c
View file

@ -50,7 +50,6 @@
#include <nuttx/arch.h>
#include "up_arch.h"
#include "cache.h"
#include "up_internal.h"
#include "sched/sched.h"
@ -1449,7 +1448,7 @@ sam_allocdesc(struct sam_dmach_s *dmach, struct dma_linklist_s *prev,
* that hardware will be accessing the descriptor via DMA.
*/
arch_clean_dcache((uintptr_t)desc,
up_clean_dcache((uintptr_t)desc,
(uintptr_t)desc + sizeof(struct dma_linklist_s));
break;
}
@ -1773,7 +1772,7 @@ static void sam_dmaterminate(struct sam_dmach_s *dmach, int result)
if (dmach->rx)
{
arch_invalidate_dcache(dmach->rxaddr, dmach->rxaddr + dmach->rxsize);
up_invalidate_dcache(dmach->rxaddr, dmach->rxaddr + dmach->rxsize);
}
/* Perform the DMA complete callback */
@ -2187,7 +2186,7 @@ int sam_dmatxsetup(DMA_HANDLE handle, uint32_t paddr, uint32_t maddr,
/* Clean caches associated with the DMA memory */
arch_clean_dcache(maddr, maddr + nbytes);
up_clean_dcache(maddr, maddr + nbytes);
return ret;
}
@ -2268,7 +2267,7 @@ int sam_dmarxsetup(DMA_HANDLE handle, uint32_t paddr, uint32_t maddr,
/* Clean caches associated with the DMA memory */
arch_clean_dcache(maddr, maddr + nbytes);
up_clean_dcache(maddr, maddr + nbytes);
return ret;
}

48
arch/arm/src/sama5/sam_ehci.c
View file

@ -60,8 +60,6 @@
#include <nuttx/usb/usbhost_trace.h>
#include "up_arch.h"
#include "cache.h"
#include "chip.h"
#include "sam_periphclks.h"
#include "sam_memories.h"
@ -1173,7 +1171,7 @@ static int sam_qtd_invalidate(struct sam_qtd_s *qtd, uint32_t **bp, void *arg)
* memory over the specified address range.
*/
arch_invalidate_dcache((uintptr_t)&qtd->hw,
up_invalidate_dcache((uintptr_t)&qtd->hw,
(uintptr_t)&qtd->hw + sizeof(struct ehci_qtd_s));
return OK;
}
@ -1192,7 +1190,7 @@ static int sam_qh_invalidate(struct sam_qh_s *qh)
{
/* Invalidate the QH first so that we reload the qTD list head */
arch_invalidate_dcache((uintptr_t)&qh->hw,
up_invalidate_dcache((uintptr_t)&qh->hw,
(uintptr_t)&qh->hw + sizeof(struct ehci_qh_s));
/* Then invalidate all of the qTD entries in the queue */
@ -1218,12 +1216,12 @@ static int sam_qtd_flush(struct sam_qtd_s *qtd, uint32_t **bp, void *arg)
*/
#if 0 /* Didn't behave as expected */
arch_flush_dcache((uintptr_t)&qtd->hw,
up_flush_dcache((uintptr_t)&qtd->hw,
(uintptr_t)&qtd->hw + sizeof(struct ehci_qtd_s));
#else
arch_clean_dcache((uintptr_t)&qtd->hw,
up_clean_dcache((uintptr_t)&qtd->hw,
(uintptr_t)&qtd->hw + sizeof(struct ehci_qtd_s));
arch_invalidate_dcache((uintptr_t)&qtd->hw,
up_invalidate_dcache((uintptr_t)&qtd->hw,
(uintptr_t)&qtd->hw + sizeof(struct ehci_qtd_s));
#endif
@ -1246,12 +1244,12 @@ static int sam_qh_flush(struct sam_qh_s *qh)
*/
#if 0 /* Didn't behave as expected */
arch_flush_dcache((uintptr_t)&qh->hw,
up_flush_dcache((uintptr_t)&qh->hw,
(uintptr_t)&qh->hw + sizeof(struct ehci_qh_s));
#else
arch_clean_dcache((uintptr_t)&qh->hw,
up_clean_dcache((uintptr_t)&qh->hw,
(uintptr_t)&qh->hw + sizeof(struct ehci_qh_s));
arch_invalidate_dcache((uintptr_t)&qh->hw,
up_invalidate_dcache((uintptr_t)&qh->hw,
(uintptr_t)&qh->hw + sizeof(struct ehci_qh_s));
#endif
@ -1484,7 +1482,7 @@ static void sam_qh_enqueue(struct sam_qh_s *qhead, struct sam_qh_s *qh)
physaddr = (uintptr_t)sam_physramaddr((uintptr_t)qh);
qhead->hw.hlp = sam_swap32(physaddr | QH_HLP_TYP_QH);
arch_clean_dcache((uintptr_t)&qhead->hw,
up_clean_dcache((uintptr_t)&qhead->hw,
(uintptr_t)&qhead->hw + sizeof(struct ehci_qh_s));
}
@ -1645,10 +1643,10 @@ static int sam_qtd_addbpl(struct sam_qtd_s *qtd, const void *buffer, size_t bufl
*/
#if 0 /* Didn't behave as expected */
arch_flush_dcache((uintptr_t)buffer, (uintptr_t)buffer + buflen);
up_flush_dcache((uintptr_t)buffer, (uintptr_t)buffer + buflen);
#else
arch_clean_dcache((uintptr_t)buffer, (uintptr_t)buffer + buflen);
arch_invalidate_dcache((uintptr_t)buffer, (uintptr_t)buffer + buflen);
up_clean_dcache((uintptr_t)buffer, (uintptr_t)buffer + buflen);
up_invalidate_dcache((uintptr_t)buffer, (uintptr_t)buffer + buflen);
#endif
/* Loop, adding the aligned physical addresses of the buffer to the buffer page
@ -2338,7 +2336,7 @@ static ssize_t sam_transfer_wait(struct sam_epinfo_s *epinfo)
* invalid in this memory region.
*/
arch_invalidate_dcache((uintptr_t)buffer, (uintptr_t)buffer + buflen);
up_invalidate_dcache((uintptr_t)buffer, (uintptr_t)buffer + buflen);
}
#endif
@ -2488,7 +2486,7 @@ static int sam_qtd_ioccheck(struct sam_qtd_s *qtd, uint32_t **bp, void *arg)
/* Make sure we reload the QH from memory */
arch_invalidate_dcache((uintptr_t)&qtd->hw,
up_invalidate_dcache((uintptr_t)&qtd->hw,
(uintptr_t)&qtd->hw + sizeof(struct ehci_qtd_s));
sam_qtd_print(qtd);
@ -2539,7 +2537,7 @@ static int sam_qh_ioccheck(struct sam_qh_s *qh, uint32_t **bp, void *arg)
/* Make sure we reload the QH from memory */
arch_invalidate_dcache((uintptr_t)&qh->hw,
up_invalidate_dcache((uintptr_t)&qh->hw,
(uintptr_t)&qh->hw + sizeof(struct ehci_qh_s));
sam_qh_print(qh);
@ -2593,7 +2591,7 @@ static int sam_qh_ioccheck(struct sam_qh_s *qh, uint32_t **bp, void *arg)
*/
**bp = qh->hw.hlp;
arch_clean_dcache((uintptr_t)*bp, (uintptr_t)*bp + sizeof(uint32_t));
up_clean_dcache((uintptr_t)*bp, (uintptr_t)*bp + sizeof(uint32_t));
/* Check for errors, update the data toggle */
@ -2692,7 +2690,7 @@ static int sam_qtd_cancel(struct sam_qtd_s *qtd, uint32_t **bp, void *arg)
/* Make sure we reload the QH from memory */
arch_invalidate_dcache((uintptr_t)&qtd->hw,
up_invalidate_dcache((uintptr_t)&qtd->hw,
(uintptr_t)&qtd->hw + sizeof(struct ehci_qtd_s));
sam_qtd_print(qtd);
@ -2735,7 +2733,7 @@ static int sam_qh_cancel(struct sam_qh_s *qh, uint32_t **bp, void *arg)
/* Make sure we reload the QH from memory */
arch_invalidate_dcache((uintptr_t)&qh->hw,
up_invalidate_dcache((uintptr_t)&qh->hw,
(uintptr_t)&qh->hw + sizeof(struct ehci_qh_s));
sam_qh_print(qh);
@ -2814,7 +2812,7 @@ static inline void sam_ioc_bottomhalf(void)
/* Check the Asynchronous Queue */
/* Make sure that the head of the asynchronous queue is invalidated */
arch_invalidate_dcache((uintptr_t)&g_asynchead.hw,
up_invalidate_dcache((uintptr_t)&g_asynchead.hw,
(uintptr_t)&g_asynchead.hw + sizeof(struct ehci_qh_s));
/* Set the back pointer to the forward QH pointer of the asynchronous
@ -2845,7 +2843,7 @@ static inline void sam_ioc_bottomhalf(void)
/* Check the Interrupt Queue */
/* Make sure that the head of the interrupt queue is invalidated */
arch_invalidate_dcache((uintptr_t)&g_intrhead.hw,
up_invalidate_dcache((uintptr_t)&g_intrhead.hw,
(uintptr_t)&g_intrhead.hw + sizeof(struct ehci_qh_s));
/* Set the back pointer to the forward qTD pointer of the asynchronous
@ -5012,7 +5010,7 @@ FAR struct usbhost_connection_s *sam_ehci_initialize(int controller)
g_asynchead.hw.overlay.token = sam_swap32(QH_TOKEN_HALTED);
g_asynchead.fqp = sam_swap32(QTD_NQP_T);
arch_clean_dcache((uintptr_t)&g_asynchead.hw,
up_clean_dcache((uintptr_t)&g_asynchead.hw,
(uintptr_t)&g_asynchead.hw + sizeof(struct ehci_qh_s));
/* Set the Current Asynchronous List Address. */
@ -5043,9 +5041,9 @@ FAR struct usbhost_connection_s *sam_ehci_initialize(int controller)
/* Set the Periodic Frame List Base Address. */
arch_clean_dcache((uintptr_t)&g_intrhead.hw,
up_clean_dcache((uintptr_t)&g_intrhead.hw,
(uintptr_t)&g_intrhead.hw + sizeof(struct ehci_qh_s));
arch_clean_dcache((uintptr_t)g_framelist,
up_clean_dcache((uintptr_t)g_framelist,
(uintptr_t)g_framelist + FRAME_LIST_SIZE * sizeof(uint32_t));
physaddr = sam_physramaddr((uintptr_t)g_framelist);

27
arch/arm/src/sama5/sam_emaca.c
View file

@ -77,7 +77,6 @@
#include "up_arch.h"
#include "up_internal.h"
#include "cache.h"
#include "chip.h"
#include "chip/sam_pinmap.h"
@ -785,7 +784,7 @@ static int sam_transmit(struct sam_emac_s *priv)
virtaddr = sam_virtramaddr(txdesc->addr);
memcpy((void *)virtaddr, dev->d_buf, dev->d_len);
arch_clean_dcache((uint32_t)virtaddr, (uint32_t)virtaddr + dev->d_len);
up_clean_dcache((uint32_t)virtaddr, (uint32_t)virtaddr + dev->d_len);
}
/* Update TX descriptor status. */
@ -799,7 +798,7 @@ static int sam_transmit(struct sam_emac_s *priv)
/* Update the descriptor status and flush the updated value to RAM */
txdesc->status = status;
arch_clean_dcache((uint32_t)txdesc,
up_clean_dcache((uint32_t)txdesc,
(uint32_t)txdesc + sizeof(struct emac_txdesc_s));
/* Increment the head index */
@ -1015,7 +1014,7 @@ static int sam_recvframe(struct sam_emac_s *priv)
/* Invalidate the RX descriptor to force re-fetching from RAM */
arch_invalidate_dcache((uintptr_t)rxdesc,
up_invalidate_dcache((uintptr_t)rxdesc,
(uintptr_t)rxdesc + sizeof(struct emac_rxdesc_s));
ninfo("rxndx: %d\n", rxndx);
@ -1039,7 +1038,7 @@ static int sam_recvframe(struct sam_emac_s *priv)
/* Flush the modified RX descriptor to RAM */
arch_clean_dcache((uintptr_t)rxdesc,
up_clean_dcache((uintptr_t)rxdesc,
(uintptr_t)rxdesc +
sizeof(struct emac_rxdesc_s));
@ -1084,7 +1083,7 @@ static int sam_recvframe(struct sam_emac_s *priv)
/* Flush the modified RX descriptor to RAM */
arch_clean_dcache((uintptr_t)rxdesc,
up_clean_dcache((uintptr_t)rxdesc,
(uintptr_t)rxdesc +
sizeof(struct emac_rxdesc_s));
@ -1114,7 +1113,7 @@ static int sam_recvframe(struct sam_emac_s *priv)
physaddr = (uintptr_t)(rxdesc->addr & EMACRXD_ADDR_MASK);
src = (const uint8_t *)sam_virtramaddr(physaddr);
arch_invalidate_dcache((uintptr_t)src, (uintptr_t)src + copylen);
up_invalidate_dcache((uintptr_t)src, (uintptr_t)src + copylen);
/* And do the copy */
@ -1144,7 +1143,7 @@ static int sam_recvframe(struct sam_emac_s *priv)
/* Flush the modified RX descriptor to RAM */
arch_clean_dcache((uintptr_t)rxdesc,
up_clean_dcache((uintptr_t)rxdesc,
(uintptr_t)rxdesc +
sizeof(struct emac_rxdesc_s));
@ -1184,7 +1183,7 @@ static int sam_recvframe(struct sam_emac_s *priv)
/* Flush the modified RX descriptor to RAM */
arch_clean_dcache((uintptr_t)rxdesc,
up_clean_dcache((uintptr_t)rxdesc,
(uintptr_t)rxdesc +
sizeof(struct emac_rxdesc_s));
@ -1197,7 +1196,7 @@ static int sam_recvframe(struct sam_emac_s *priv)
/* Invalidate the RX descriptor to force re-fetching from RAM */
arch_invalidate_dcache((uintptr_t)rxdesc,
up_invalidate_dcache((uintptr_t)rxdesc,
(uintptr_t)rxdesc + sizeof(struct emac_rxdesc_s));
}
@ -1405,7 +1404,7 @@ static void sam_txdone(struct sam_emac_s *priv)
/* Yes.. check the next buffer at the tail of the list */
txdesc = &priv->txdesc[priv->txtail];
arch_invalidate_dcache((uintptr_t)txdesc,
up_invalidate_dcache((uintptr_t)txdesc,
(uintptr_t)txdesc + sizeof(struct emac_txdesc_s));
/* Is this TX descriptor still in use? */
@ -1425,7 +1424,7 @@ static void sam_txdone(struct sam_emac_s *priv)
sam_physramaddr((uintptr_t)txdesc) != sam_getreg(priv, SAM_EMAC_TBQP))
{
txdesc->status = (uint32_t)EMACTXD_STA_USED;
arch_clean_dcache((uintptr_t)txdesc,
up_clean_dcache((uintptr_t)txdesc,
(uintptr_t)txdesc + sizeof(struct emac_txdesc_s));
}
else
@ -3324,7 +3323,7 @@ static void sam_txreset(struct sam_emac_s *priv)
/* Flush the entire TX descriptor table to RAM */
arch_clean_dcache((uintptr_t)txdesc,
up_clean_dcache((uintptr_t)txdesc,
(uintptr_t)txdesc +
CONFIG_SAMA5_EMAC_NTXBUFFERS * sizeof(struct emac_txdesc_s));
@ -3388,7 +3387,7 @@ static void sam_rxreset(struct sam_emac_s *priv)
/* Flush the entire RX descriptor table to RAM */
arch_clean_dcache((uintptr_t)rxdesc,
up_clean_dcache((uintptr_t)rxdesc,
(uintptr_t)rxdesc +
CONFIG_SAMA5_EMAC_NRXBUFFERS * sizeof(struct emac_rxdesc_s));

29
arch/arm/src/sama5/sam_emacb.c
View file

@ -91,7 +91,6 @@
#include "up_arch.h"
#include "up_internal.h"
#include "cache.h"
#include "chip.h"
#include "chip/sam_pinmap.h"
@ -1120,7 +1119,7 @@ static int sam_transmit(struct sam_emac_s *priv)
virtaddr = sam_virtramaddr(txdesc->addr);
memcpy((void *)virtaddr, dev->d_buf, dev->d_len);
arch_clean_dcache((uint32_t)virtaddr, (uint32_t)virtaddr + dev->d_len);
up_clean_dcache((uint32_t)virtaddr, (uint32_t)virtaddr + dev->d_len);
}
/* Update TX descriptor status. */
@ -1134,7 +1133,7 @@ static int sam_transmit(struct sam_emac_s *priv)
/* Update the descriptor status and flush the updated value to RAM */
txdesc->status = status;
arch_clean_dcache((uint32_t)txdesc,
up_clean_dcache((uint32_t)txdesc,
(uint32_t)txdesc + sizeof(struct emac_txdesc_s));
/* Increment the head index */
@ -1351,7 +1350,7 @@ static int sam_recvframe(struct sam_emac_s *priv)
/* Invalidate the RX descriptor to force re-fetching from RAM */
arch_invalidate_dcache((uintptr_t)rxdesc,
up_invalidate_dcache((uintptr_t)rxdesc,
(uintptr_t)rxdesc + sizeof(struct emac_rxdesc_s));
ninfo("rxndx: %d\n", rxndx);
@ -1374,7 +1373,7 @@ static int sam_recvframe(struct sam_emac_s *priv)
/* Flush the modified RX descriptor to RAM */
arch_clean_dcache((uintptr_t)rxdesc,
up_clean_dcache((uintptr_t)rxdesc,
(uintptr_t)rxdesc +
sizeof(struct emac_rxdesc_s));
@ -1419,7 +1418,7 @@ static int sam_recvframe(struct sam_emac_s *priv)
/* Flush the modified RX descriptor to RAM */
arch_clean_dcache((uintptr_t)rxdesc,
up_clean_dcache((uintptr_t)rxdesc,
(uintptr_t)rxdesc +
sizeof(struct emac_rxdesc_s));
@ -1449,7 +1448,7 @@ static int sam_recvframe(struct sam_emac_s *priv)
physaddr = (uintptr_t)(rxdesc->addr & EMACRXD_ADDR_MASK);
src = (const uint8_t *)sam_virtramaddr(physaddr);
arch_invalidate_dcache((uintptr_t)src, (uintptr_t)src + copylen);
up_invalidate_dcache((uintptr_t)src, (uintptr_t)src + copylen);
/* And do the copy */
@ -1479,7 +1478,7 @@ static int sam_recvframe(struct sam_emac_s *priv)
/* Flush the modified RX descriptor to RAM */
arch_clean_dcache((uintptr_t)rxdesc,
up_clean_dcache((uintptr_t)rxdesc,
(uintptr_t)rxdesc +
sizeof(struct emac_rxdesc_s));
@ -1519,7 +1518,7 @@ static int sam_recvframe(struct sam_emac_s *priv)
/* Flush the modified RX descriptor to RAM */
arch_clean_dcache((uintptr_t)rxdesc,
up_clean_dcache((uintptr_t)rxdesc,
(uintptr_t)rxdesc +
sizeof(struct emac_rxdesc_s));
@ -1532,7 +1531,7 @@ static int sam_recvframe(struct sam_emac_s *priv)
/* Invalidate the RX descriptor to force re-fetching from RAM */
arch_invalidate_dcache((uintptr_t)rxdesc,
up_invalidate_dcache((uintptr_t)rxdesc,
(uintptr_t)rxdesc + sizeof(struct emac_rxdesc_s));
}
@ -1743,7 +1742,7 @@ static void sam_txdone(struct sam_emac_s *priv)
/* Yes.. check the next buffer at the tail of the list */
txdesc = &priv->txdesc[priv->txtail];
arch_invalidate_dcache((uintptr_t)txdesc,
up_invalidate_dcache((uintptr_t)txdesc,
(uintptr_t)txdesc + sizeof(struct emac_txdesc_s));
/* Is this TX descriptor still in use? */
@ -1776,7 +1775,7 @@ static void sam_txdone(struct sam_emac_s *priv)
sam_physramaddr((uintptr_t)txdesc) != sam_getreg(priv, SAM_EMAC_TBQB_OFFSET))
{
txdesc->status = (uint32_t)EMACTXD_STA_USED;
arch_clean_dcache((uintptr_t)txdesc,
up_clean_dcache((uintptr_t)txdesc,
(uintptr_t)txdesc + sizeof(struct emac_txdesc_s));
}
else
@ -1794,7 +1793,7 @@ static void sam_txdone(struct sam_emac_s *priv)
/* Make sure that the USED bit is set */
txdesc->status = (uint32_t)EMACTXD_STA_USED;
arch_clean_dcache((uintptr_t)txdesc,
up_clean_dcache((uintptr_t)txdesc,
(uintptr_t)txdesc + sizeof(struct emac_txdesc_s));
#endif
@ -3884,7 +3883,7 @@ static void sam_txreset(struct sam_emac_s *priv)
/* Flush the entire TX descriptor table to RAM */
arch_clean_dcache((uintptr_t)txdesc,
up_clean_dcache((uintptr_t)txdesc,
(uintptr_t)txdesc +
priv->attr->ntxbuffers * sizeof(struct emac_txdesc_s));
@ -3948,7 +3947,7 @@ static void sam_rxreset(struct sam_emac_s *priv)
/* Flush the entire RX descriptor table to RAM */
arch_clean_dcache((uintptr_t)rxdesc,
up_clean_dcache((uintptr_t)rxdesc,
(uintptr_t)rxdesc +
priv->attr->nrxbuffers * sizeof(struct emac_rxdesc_s));

27
arch/arm/src/sama5/sam_gmac.c
View file

@ -74,7 +74,6 @@
#include "up_arch.h"
#include "up_internal.h"
#include "cache.h"
#include "chip.h"
#include "chip/sam_pinmap.h"
@ -717,7 +716,7 @@ static int sam_transmit(struct sam_gmac_s *priv)
virtaddr = sam_virtramaddr(txdesc->addr);
memcpy((void *)virtaddr, dev->d_buf, dev->d_len);
arch_clean_dcache((uint32_t)virtaddr, (uint32_t)virtaddr + dev->d_len);
up_clean_dcache((uint32_t)virtaddr, (uint32_t)virtaddr + dev->d_len);
}
/* Update TX descriptor status. */
@ -731,7 +730,7 @@ static int sam_transmit(struct sam_gmac_s *priv)
/* Update the descriptor status and flush the updated value to RAM */
txdesc->status = status;
arch_clean_dcache((uint32_t)txdesc,
up_clean_dcache((uint32_t)txdesc,
(uint32_t)txdesc + sizeof(struct gmac_txdesc_s));
/* Increment the head index */
@ -947,7 +946,7 @@ static int sam_recvframe(struct sam_gmac_s *priv)
/* Invalidate the RX descriptor to force re-fetching from RAM */
arch_invalidate_dcache((uintptr_t)rxdesc,
up_invalidate_dcache((uintptr_t)rxdesc,
(uintptr_t)rxdesc + sizeof(struct gmac_rxdesc_s));
ninfo("rxndx: %d\n", rxndx);
@ -971,7 +970,7 @@ static int sam_recvframe(struct sam_gmac_s *priv)
/* Flush the modified RX descriptor to RAM */
arch_clean_dcache((uintptr_t)rxdesc,
up_clean_dcache((uintptr_t)rxdesc,
(uintptr_t)rxdesc +
sizeof(struct gmac_rxdesc_s));
@ -1016,7 +1015,7 @@ static int sam_recvframe(struct sam_gmac_s *priv)
/* Flush the modified RX descriptor to RAM */
arch_clean_dcache((uintptr_t)rxdesc,
up_clean_dcache((uintptr_t)rxdesc,
(uintptr_t)rxdesc +
sizeof(struct gmac_rxdesc_s));
@ -1046,7 +1045,7 @@ static int sam_recvframe(struct sam_gmac_s *priv)
physaddr = (uintptr_t)(rxdesc->addr & GMACRXD_ADDR_MASK);
src = (const uint8_t *)sam_virtramaddr(physaddr);
arch_invalidate_dcache((uintptr_t)src, (uintptr_t)src + copylen);
up_invalidate_dcache((uintptr_t)src, (uintptr_t)src + copylen);
/* And do the copy */
@ -1076,7 +1075,7 @@ static int sam_recvframe(struct sam_gmac_s *priv)
/* Flush the modified RX descriptor to RAM */
arch_clean_dcache((uintptr_t)rxdesc,
up_clean_dcache((uintptr_t)rxdesc,
(uintptr_t)rxdesc +
sizeof(struct gmac_rxdesc_s));
@ -1114,7 +1113,7 @@ static int sam_recvframe(struct sam_gmac_s *priv)
/* Flush the modified RX descriptor to RAM */
arch_clean_dcache((uintptr_t)rxdesc,
up_clean_dcache((uintptr_t)rxdesc,
(uintptr_t)rxdesc +
sizeof(struct gmac_rxdesc_s));
@ -1127,7 +1126,7 @@ static int sam_recvframe(struct sam_gmac_s *priv)
/* Invalidate the RX descriptor to force re-fetching from RAM */
arch_invalidate_dcache((uintptr_t)rxdesc,
up_invalidate_dcache((uintptr_t)rxdesc,
(uintptr_t)rxdesc + sizeof(struct gmac_rxdesc_s));
}
@ -1335,7 +1334,7 @@ static void sam_txdone(struct sam_gmac_s *priv)
/* Yes.. check the next buffer at the tail of the list */
txdesc = &priv->txdesc[priv->txtail];
arch_invalidate_dcache((uintptr_t)txdesc,
up_invalidate_dcache((uintptr_t)txdesc,
(uintptr_t)txdesc + sizeof(struct gmac_txdesc_s));
/* Is this TX descriptor still in use? */
@ -1354,7 +1353,7 @@ static void sam_txdone(struct sam_gmac_s *priv)
sam_physramaddr((uintptr_t)txdesc) != sam_getreg(priv, SAM_GMAC_TBQB))
{
txdesc->status = (uint32_t)GMACTXD_STA_USED;
arch_clean_dcache((uintptr_t)txdesc,
up_clean_dcache((uintptr_t)txdesc,
(uintptr_t)txdesc + sizeof(struct gmac_txdesc_s));
}
else
@ -3372,7 +3371,7 @@ static void sam_txreset(struct sam_gmac_s *priv)
/* Flush the entire TX descriptor table to RAM */
arch_clean_dcache((uintptr_t)txdesc,
up_clean_dcache((uintptr_t)txdesc,
(uintptr_t)txdesc +
CONFIG_SAMA5_GMAC_NTXBUFFERS * sizeof(struct gmac_txdesc_s));
@ -3436,7 +3435,7 @@ static void sam_rxreset(struct sam_gmac_s *priv)
/* Flush the entire RX descriptor table to RAM */
arch_clean_dcache((uintptr_t)rxdesc,
up_clean_dcache((uintptr_t)rxdesc,
(uintptr_t)rxdesc +
CONFIG_SAMA5_GMAC_NRXBUFFERS * sizeof(struct gmac_rxdesc_s));

2
arch/arm/src/sama5/sam_irq.c
View file

@ -55,7 +55,7 @@
#include "chip.h"
#include "mmu.h"
#include "cache.h"
#include "cp15_cacheops.h"
#include "sctlr.h"
#include "chip/sam_aic.h"
#include "chip/sam_matrix.h"

5
arch/arm/src/sama5/sam_nand.c
View file

@ -69,7 +69,6 @@
#include <arch/board/board.h>
#include "up_arch.h"
#include "cache.h"
#include "sam_memories.h"
#include "sam_dmac.h"
@ -1294,7 +1293,7 @@ static int nand_dma_read(struct sam_nandcs_s *priv,
* that memory will be re-cached after the DMA completes).
*/
arch_invalidate_dcache(vdest, vdest + nbytes);
up_invalidate_dcache(vdest, vdest + nbytes);
/* DMA will need physical addresses. */
@ -1379,7 +1378,7 @@ static int nand_dma_write(struct sam_nandcs_s *priv,
* the data to be transferred lies in physical memory
*/
arch_clean_dcache(vsrc, vsrc + nbytes);
up_clean_dcache(vsrc, vsrc + nbytes);
/* DMA will need physical addresses. */

59
arch/arm/src/sama5/sam_ohci.c
View file

@ -65,7 +65,6 @@
#include "up_arch.h"
#include "up_internal.h"
#include "cache.h"
#include "chip.h"
#include "sam_periphclks.h"
#include "sam_memories.h"
@ -851,7 +850,7 @@ static int sam_addctrled(struct sam_ed_s *ed)
/* Add the new control ED to the head of the control list */
ed->hw.nexted = sam_getreg(SAM_USBHOST_CTRLHEADED);
arch_clean_dcache((uintptr_t)ed, (uintptr_t)ed + sizeof(struct ohci_ed_s));
up_clean_dcache((uintptr_t)ed, (uintptr_t)ed + sizeof(struct ohci_ed_s));
physed = sam_physramaddr((uintptr_t)ed);
sam_putreg((uint32_t)physed, SAM_USBHOST_CTRLHEADED);
@ -921,7 +920,7 @@ static inline int sam_remctrled(struct sam_ed_s *ed)
*/
prev->hw.nexted = ed->hw.nexted;
arch_clean_dcache((uintptr_t)prev,
up_clean_dcache((uintptr_t)prev,
(uintptr_t)prev + sizeof(struct sam_ed_s));
}
}
@ -969,7 +968,7 @@ static inline int sam_addbulked(struct sam_ed_s *ed)
/* Add the new bulk ED to the head of the bulk list */
ed->hw.nexted = sam_getreg(SAM_USBHOST_BULKHEADED);
arch_clean_dcache((uintptr_t)ed, (uintptr_t)ed + sizeof(struct ohci_ed_s));
up_clean_dcache((uintptr_t)ed, (uintptr_t)ed + sizeof(struct ohci_ed_s));
physed = sam_physramaddr((uintptr_t)ed);
sam_putreg((uint32_t)physed, SAM_USBHOST_BULKHEADED);
@ -1043,7 +1042,7 @@ static inline int sam_rembulked(struct sam_ed_s *ed)
*/
prev->hw.nexted = ed->hw.nexted;
arch_clean_dcache((uintptr_t)prev,
up_clean_dcache((uintptr_t)prev,
(uintptr_t)prev + sizeof(struct sam_ed_s));
}
}
@ -1133,7 +1132,7 @@ static void sam_setinttab(uint32_t value, unsigned int interval, unsigned int of
/* Make sure that the modified table value is flushed to RAM */
inttbl = (uintptr_t)g_hcca.inttbl;
arch_clean_dcache(inttbl, inttbl + sizeof(uint32_t)*HCCA_INTTBL_WSIZE);
up_clean_dcache(inttbl, inttbl + sizeof(uint32_t)*HCCA_INTTBL_WSIZE);
}
#endif
@ -1236,7 +1235,7 @@ static inline int sam_addinted(const struct usbhost_epdesc_s *epdesc,
*/
ed->hw.nexted = physhead;
arch_clean_dcache((uintptr_t)ed, (uintptr_t)ed + sizeof(struct ohci_ed_s));
up_clean_dcache((uintptr_t)ed, (uintptr_t)ed + sizeof(struct ohci_ed_s));
physed = sam_physramaddr((uintptr_t)ed);
sam_setinttab((uint32_t)physed, interval, offset);
@ -1473,7 +1472,7 @@ static int sam_enqueuetd(struct sam_rhport_s *rhport, struct sam_eplist_s *eplis
/* Skip processing of this ED while we modify the TD list. */
ed->hw.ctrl |= ED_CONTROL_K;
arch_clean_dcache((uintptr_t)ed,
up_clean_dcache((uintptr_t)ed,
(uintptr_t)ed + sizeof(struct ohci_ed_s));
/* Get the tail ED for this hub port */
@ -1513,19 +1512,19 @@ static int sam_enqueuetd(struct sam_rhport_s *rhport, struct sam_eplist_s *eplis
if (buffer && buflen > 0)
{
arch_clean_dcache((uintptr_t)buffer,
up_clean_dcache((uintptr_t)buffer,
(uintptr_t)buffer + buflen);
}
arch_clean_dcache((uintptr_t)tdtail,
up_clean_dcache((uintptr_t)tdtail,
(uintptr_t)tdtail + sizeof(struct ohci_gtd_s));
arch_clean_dcache((uintptr_t)td,
up_clean_dcache((uintptr_t)td,
(uintptr_t)td + sizeof(struct ohci_gtd_s));
/* Resume processing of this ED */
ed->hw.ctrl &= ~ED_CONTROL_K;
arch_clean_dcache((uintptr_t)ed,
up_clean_dcache((uintptr_t)ed,
(uintptr_t)ed + sizeof(struct ohci_ed_s));
ret = OK;
}
@ -1606,9 +1605,9 @@ static int sam_ep0enqueue(struct sam_rhport_s *rhport)
/* Flush the affected control ED and tail TD to RAM */
arch_clean_dcache((uintptr_t)edctrl,
up_clean_dcache((uintptr_t)edctrl,
(uintptr_t)edctrl + sizeof(struct ohci_ed_s));
arch_clean_dcache((uintptr_t)tdtail,
up_clean_dcache((uintptr_t)tdtail,
(uintptr_t)tdtail + sizeof(struct ohci_gtd_s));
/* Add the ED to the control list */
@ -1684,7 +1683,7 @@ static void sam_ep0dequeue(struct sam_eplist_s *ep0)
/* Flush the modified ED to RAM */
arch_clean_dcache((uintptr_t)preved,
up_clean_dcache((uintptr_t)preved,
(uintptr_t)preved + sizeof(struct ohci_ed_s));
}
else
@ -2106,10 +2105,10 @@ static void sam_wdh_bottomhalf(void)
/* Invalidate D-cache to force re-reading of the Done Head */
#if 0 /* Apparently insufficient */
arch_invalidate_dcache((uintptr_t)&g_hcca.donehead,
up_invalidate_dcache((uintptr_t)&g_hcca.donehead,
(uintptr_t)&g_hcca.donehead + sizeof(uint32_t));
#else
arch_invalidate_dcache((uintptr_t)&g_hcca,
up_invalidate_dcache((uintptr_t)&g_hcca,
(uintptr_t)&g_hcca + sizeof(struct ohci_hcca_s));
#endif
@ -2126,7 +2125,7 @@ static void sam_wdh_bottomhalf(void)
* reloaded from memory.
*/
arch_invalidate_dcache((uintptr_t)td,
up_invalidate_dcache((uintptr_t)td,
(uintptr_t)td + sizeof(struct ohci_gtd_s));
/* Get the ED in which this TD was enqueued */
@ -2153,7 +2152,7 @@ static void sam_wdh_bottomhalf(void)
* memory.
*/
arch_invalidate_dcache((uintptr_t)ed,
up_invalidate_dcache((uintptr_t)ed,
(uintptr_t)ed + sizeof(struct ohci_ed_s));
/* Save the condition code from the (single) TD status/control
@ -2605,7 +2604,7 @@ static int sam_ep0configure(struct usbhost_driver_s *drvr, usbhost_ep_t ep0,
/* Flush the modified control ED to RAM */
arch_clean_dcache((uintptr_t)edctrl,
up_clean_dcache((uintptr_t)edctrl,
(uintptr_t)edctrl + sizeof(struct ohci_ed_s));
sam_givesem(&g_ohci.exclsem);
@ -2764,9 +2763,9 @@ static int sam_epalloc(struct usbhost_driver_s *drvr,
/* Make sure these settings are flushed to RAM */
arch_clean_dcache((uintptr_t)ed,
up_clean_dcache((uintptr_t)ed,
(uintptr_t)ed + sizeof(struct ohci_ed_s));
arch_clean_dcache((uintptr_t)td,
up_clean_dcache((uintptr_t)td,
(uintptr_t)td + sizeof(struct ohci_gtd_s));
/* Now add the endpoint descriptor to the appropriate list */
@ -3142,7 +3141,7 @@ static int sam_ctrlin(struct usbhost_driver_s *drvr, usbhost_ep_t ep0,
*/
sam_givesem(&g_ohci.exclsem);
arch_invalidate_dcache((uintptr_t)buffer, (uintptr_t)buffer + len);
up_invalidate_dcache((uintptr_t)buffer, (uintptr_t)buffer + len);
return ret;
}
@ -3383,7 +3382,7 @@ static ssize_t sam_transfer(struct usbhost_driver_s *drvr, usbhost_ep_t ep,
/* Invalidate the D cache to force the ED to be reloaded from RAM */
arch_invalidate_dcache((uintptr_t)ed,
up_invalidate_dcache((uintptr_t)ed,
(uintptr_t)ed + sizeof(struct ohci_ed_s));
/* Check the TD completion status bits */
@ -3396,7 +3395,7 @@ static ssize_t sam_transfer(struct usbhost_driver_s *drvr, usbhost_ep_t ep,
if (in)
{
arch_invalidate_dcache((uintptr_t)buffer,
up_invalidate_dcache((uintptr_t)buffer,
(uintptr_t)buffer + buflen);
}
@ -3467,7 +3466,7 @@ static void sam_asynch_completion(struct sam_eplist_s *eplist)
/* Invalidate the D cache to force the ED to be reloaded from RAM */
arch_invalidate_dcache((uintptr_t)ed,
up_invalidate_dcache((uintptr_t)ed,
(uintptr_t)ed + sizeof(struct ohci_ed_s));
/* Check the TD completion status bits */
@ -3481,7 +3480,7 @@ static void sam_asynch_completion(struct sam_eplist_s *eplist)
if ((ed->hw.ctrl & ED_CONTROL_D_MASK) == ED_CONTROL_D_IN)
{
uintptr_t buffaddr = (uintptr_t)eplist->buffer;
arch_invalidate_dcache(buffaddr, buffaddr + eplist->buflen);
up_invalidate_dcache(buffaddr, buffaddr + eplist->buflen);
}
nbytes = eplist->xfrd;
@ -3688,7 +3687,7 @@ static int sam_cancel(struct usbhost_driver_s *drvr, usbhost_ep_t ep)
paddr = sam_physramaddr((uintptr_t)eplist->tail);
ed->hw.headp = paddr;
arch_clean_dcache((uintptr_t)ed,
up_clean_dcache((uintptr_t)ed,
(uintptr_t)ed + sizeof(struct ohci_ed_s));
/* Re-enable bulk list processing, if it was enabled before */
@ -3706,7 +3705,7 @@ static int sam_cancel(struct usbhost_driver_s *drvr, usbhost_ep_t ep)
paddr = sam_physramaddr((uintptr_t)eplist->tail);
ed->hw.headp = paddr;
arch_clean_dcache((uintptr_t)ed,
up_clean_dcache((uintptr_t)ed,
(uintptr_t)ed + sizeof(struct ohci_ed_s));
}
@ -3989,7 +3988,7 @@ struct usbhost_connection_s *sam_ohci_initialize(int controller)
memset((void *)&g_hcca, 0, sizeof(struct ohci_hcca_s));
arch_clean_dcache((uint32_t)&g_hcca,
up_clean_dcache((uint32_t)&g_hcca,
(uint32_t)&g_hcca + sizeof(struct ohci_hcca_s));
/* Initialize user-configurable EDs */

1
arch/arm/src/sama5/sam_pgalloc.c
View file

@ -49,7 +49,6 @@
#include "chip.h"
#include "mmu.h"
#include "cache.h"
#include "sam_pgalloc.h"

5
arch/arm/src/sama5/sam_ssc.c
View file

@ -62,7 +62,6 @@
#include "up_internal.h"
#include "up_arch.h"
#include "cache.h"
#include "chip.h"
#include "sam_pio.h"
@ -1339,7 +1338,7 @@ static int ssc_rxdma_setup(struct sam_ssc_s *priv)
* DMA buffer after starting the DMA transfer.
*/
arch_invalidate_dcache((uintptr_t)apb->samp,
up_invalidate_dcache((uintptr_t)apb->samp,
(uintptr_t)apb->samp + apb->nmaxbytes);
}
@ -1754,7 +1753,7 @@ static int ssc_txdma_setup(struct sam_ssc_s *priv)
* before starting the DMA.
*/
arch_clean_dcache(samp, samp + nbytes);
up_clean_dcache(samp, samp + nbytes);
}
#if 1 /* REVISIT: Chained TX transfers */
while (0);

7
arch/arm/src/sama5/sam_udphs.c
View file

@ -66,7 +66,6 @@
#include "up_arch.h"
#include "up_internal.h"
#include "cache.h"
#include "sam_periphclks.h"
#include "sam_memories.h"
@ -904,7 +903,7 @@ static void sam_dma_single(uint8_t epno, struct sam_req_s *privreq,
/* Flush the contents of the DMA buffer to RAM */
buffer = (uintptr_t)&privreq->req.buf[privreq->req.xfrd];
arch_clean_dcache(buffer, buffer + privreq->inflight);
up_clean_dcache(buffer, buffer + privreq->inflight);
/* Set up the DMA */
@ -2414,7 +2413,7 @@ static void sam_dma_interrupt(struct sam_usbdev_s *priv, int epno)
DEBUGASSERT(USB_ISEPOUT(privep->ep.eplog));
buf = &privreq->req.buf[privreq->req.xfrd];
arch_invalidate_dcache((uintptr_t)buf, (uintptr_t)buf + xfrsize);
up_invalidate_dcache((uintptr_t)buf, (uintptr_t)buf + xfrsize);
/* Complete this transfer, return the request to the class
* implementation, and try to start the next, queue read request.
@ -2470,7 +2469,7 @@ static void sam_dma_interrupt(struct sam_usbdev_s *priv, int epno)
*/
buf = &privreq->req.buf[privreq->req.xfrd];
arch_invalidate_dcache((uintptr_t)buf, (uintptr_t)buf + xfrsize);
up_invalidate_dcache((uintptr_t)buf, (uintptr_t)buf + xfrsize);
/* Complete this transfer, return the request to the class
* implementation, and try to start the next, queue read request.

9
arch/arm/src/sama5/sam_xdmac.c
View file

@ -50,7 +50,6 @@
#include <nuttx/arch.h>
#include "up_arch.h"
#include "cache.h"
#include "up_internal.h"
#include "sched/sched.h"
@ -1399,7 +1398,7 @@ sam_allocdesc(struct sam_xdmach_s *xdmach, struct chnext_view1_s *prev,
* that hardware will be accessing the descriptor via DMA.
*/
arch_clean_dcache((uintptr_t)descr,
up_clean_dcache((uintptr_t)descr,
(uintptr_t)descr + sizeof(struct chnext_view1_s));
break;
}
@ -1803,7 +1802,7 @@ static void sam_dmaterminate(struct sam_xdmach_s *xdmach, int result)
if (xdmach->rx)
{
arch_invalidate_dcache(xdmach->rxaddr, xdmach->rxaddr + xdmach->rxsize);
up_invalidate_dcache(xdmach->rxaddr, xdmach->rxaddr + xdmach->rxsize);
}
/* Perform the DMA complete callback */
@ -2223,7 +2222,7 @@ int sam_dmatxsetup(DMA_HANDLE handle, uint32_t paddr, uint32_t maddr,
/* Clean caches associated with the DMA memory */
arch_clean_dcache(maddr, maddr + nbytes);
up_clean_dcache(maddr, maddr + nbytes);
return ret;
}
@ -2304,7 +2303,7 @@ int sam_dmarxsetup(DMA_HANDLE handle, uint32_t paddr, uint32_t maddr,
/* Clean caches associated with the DMA memory */
arch_clean_dcache(maddr, maddr + nbytes);
up_clean_dcache(maddr, maddr + nbytes);
return ret;
}

15
arch/arm/src/samv7/Make.defs
View file

@ -72,14 +72,7 @@ CMN_ASRCS += up_exception.S
endif
CMN_CSRCS += up_vectors.c
ifeq ($(CONFIG_ARMV7M_DCACHE),y)
CMN_CSRCS += arch_enable_dcache.c arch_disable_dcache.c
CMN_CSRCS += arch_invalidate_dcache.c arch_invalidate_dcache_all.c
ifneq ($(CONFIG_ARMV7M_DCACHE_WRITETHROUGH),y)
CMN_CSRCS += arch_clean_dcache.c arch_clean_dcache_all.c
CMN_CSRCS += arch_flush_dcache.c arch_flush_dcache_all.c
endif
endif
CMN_CSRCS += up_cache.c
ifeq ($(CONFIG_ARCH_FPU),y)
CMN_ASRCS += up_fpu.S
@ -101,12 +94,6 @@ endif
endif
endif
ifeq ($(CONFIG_ELF),y)
CMN_CSRCS += up_coherent_dcache.c
else ifeq ($(CONFIG_MODULE),y)
CMN_CSRCS += up_coherent_dcache.c
endif
ifeq ($(CONFIG_STACK_COLORATION),y)
CMN_CSRCS += up_checkstack.c
endif

1
arch/arm/src/samv7/sam_dac.c
View file

@ -54,7 +54,6 @@
#include "up_internal.h"
#include "up_arch.h"
#include "cache.h"
#include "chip/sam_dacc.h"
#include "chip/sam_pmc.h"

31
arch/arm/src/samv7/sam_emac.c
View file

@ -83,7 +83,6 @@
#include "up_arch.h"
#include "up_internal.h"
#include "cache.h"
#include "chip/sam_pinmap.h"
#include "chip/sam_chipid.h"
@ -1419,7 +1418,7 @@ static int sam_transmit(struct sam_emac_s *priv, int qid)
*/
memcpy((void *)txdesc->addr, dev->d_buf, dev->d_len);
arch_clean_dcache((uint32_t)txdesc->addr,
up_clean_dcache((uint32_t)txdesc->addr,
(uint32_t)txdesc->addr + dev->d_len);
}
@ -1434,7 +1433,7 @@ static int sam_transmit(struct sam_emac_s *priv, int qid)
/* Update the descriptor status and flush the updated value to RAM */
txdesc->status = status;
arch_clean_dcache((uint32_t)txdesc,
up_clean_dcache((uint32_t)txdesc,
(uint32_t)txdesc + sizeof(struct emac_txdesc_s));
/* Increment the head index */
@ -1665,7 +1664,7 @@ static int sam_recvframe(struct sam_emac_s *priv, int qid)
/* Invalidate the RX descriptor to force re-fetching from RAM. */
arch_invalidate_dcache((uintptr_t)rxdesc,
up_invalidate_dcache((uintptr_t)rxdesc,
(uintptr_t)rxdesc + sizeof(struct emac_rxdesc_s));
ninfo("Entry rxndx[%d]: %d\n", qid, rxndx);
@ -1693,7 +1692,7 @@ static int sam_recvframe(struct sam_emac_s *priv, int qid)
/* Flush the modified RX descriptor to RAM */
arch_clean_dcache((uintptr_t)rxdesc,
up_clean_dcache((uintptr_t)rxdesc,
(uintptr_t)rxdesc +
sizeof(struct emac_rxdesc_s));
@ -1741,7 +1740,7 @@ static int sam_recvframe(struct sam_emac_s *priv, int qid)
/* Flush the modified RX descriptor to RAM */
arch_clean_dcache((uintptr_t)rxdesc,
up_clean_dcache((uintptr_t)rxdesc,
(uintptr_t)rxdesc +
sizeof(struct emac_rxdesc_s));
@ -1771,7 +1770,7 @@ static int sam_recvframe(struct sam_emac_s *priv, int qid)
*/
src = (const uint8_t *)(rxdesc->addr & EMACRXD_ADDR_MASK);
arch_invalidate_dcache((uintptr_t)src, (uintptr_t)src + copylen);
up_invalidate_dcache((uintptr_t)src, (uintptr_t)src + copylen);
/* Copy the data from the driver managed the ring buffer. If we
* wanted to support zero copy transfers, we would need to make
@ -1805,7 +1804,7 @@ static int sam_recvframe(struct sam_emac_s *priv, int qid)
/* Flush the modified RX descriptor to RAM */
arch_clean_dcache((uintptr_t)rxdesc,
up_clean_dcache((uintptr_t)rxdesc,
(uintptr_t)rxdesc +
sizeof(struct emac_rxdesc_s));
@ -1850,7 +1849,7 @@ static int sam_recvframe(struct sam_emac_s *priv, int qid)
/* Flush the modified RX descriptor to RAM */
arch_clean_dcache((uintptr_t)rxdesc,
up_clean_dcache((uintptr_t)rxdesc,
(uintptr_t)rxdesc +
sizeof(struct emac_rxdesc_s));
@ -1869,7 +1868,7 @@ static int sam_recvframe(struct sam_emac_s *priv, int qid)
/* Invalidate the RX descriptor to force re-fetching from RAM */
arch_invalidate_dcache((uintptr_t)rxdesc,
up_invalidate_dcache((uintptr_t)rxdesc,
(uintptr_t)rxdesc + sizeof(struct emac_rxdesc_s));
}
@ -2090,7 +2089,7 @@ static void sam_txdone(struct sam_emac_s *priv, int qid)
/* Yes.. check the next buffer at the tail of the list */
txdesc = &xfrq->txdesc[tail];
arch_invalidate_dcache((uintptr_t)txdesc,
up_invalidate_dcache((uintptr_t)txdesc,
(uintptr_t)txdesc + sizeof(struct emac_txdesc_s));
/* Break out of the loop if frame has not yet been sent. On TX
@ -2123,7 +2122,7 @@ static void sam_txdone(struct sam_emac_s *priv, int qid)
/* Get the next TX descriptor */
txdesc = &xfrq->txdesc[tail];
arch_invalidate_dcache((uintptr_t)txdesc,
up_invalidate_dcache((uintptr_t)txdesc,
(uintptr_t)txdesc + sizeof(struct emac_txdesc_s));
}
@ -2218,7 +2217,7 @@ static void sam_txerr_interrupt(FAR struct sam_emac_s *priv, int qid)
/* Make H/W updates to the TX descriptor visible to the CPU. */
arch_invalidate_dcache((uintptr_t)txdesc,
up_invalidate_dcache((uintptr_t)txdesc,
(uintptr_t)txdesc + sizeof(struct emac_txdesc_s));
/* Go to the last buffer descriptor of the frame */
@ -2236,7 +2235,7 @@ static void sam_txerr_interrupt(FAR struct sam_emac_s *priv, int qid)
/* Get the next TX descriptor */
txdesc = &xfrq->txdesc[tail];
arch_invalidate_dcache((uintptr_t)txdesc,
up_invalidate_dcache((uintptr_t)txdesc,
(uintptr_t)txdesc + sizeof(struct emac_txdesc_s));
}
@ -4387,7 +4386,7 @@ static void sam_txreset(struct sam_emac_s *priv, int qid)
/* Flush the entire TX descriptor table to RAM */
arch_clean_dcache((uintptr_t)txdesc,
up_clean_dcache((uintptr_t)txdesc,
(uintptr_t)txdesc +
xfrq->ntxbuffers * sizeof(struct emac_txdesc_s));
@ -4458,7 +4457,7 @@ static void sam_rxreset(struct sam_emac_s *priv, int qid)
/* Flush the entire RX descriptor table to RAM */
arch_clean_dcache((uintptr_t)rxdesc,
up_clean_dcache((uintptr_t)rxdesc,
(uintptr_t)rxdesc +
xfrq->nrxbuffers * sizeof(struct emac_rxdesc_s));

9
arch/arm/src/samv7/sam_mcan.c
View file

@ -58,7 +58,6 @@
#include <nuttx/semaphore.h>
#include <nuttx/can/can.h>
#include "cache.h"
#include "up_internal.h"
#include "up_arch.h"
@ -1815,7 +1814,7 @@ static int mcan_add_extfilter(FAR struct sam_mcan_s *priv,
/* Flush the filter entry into physical RAM */
arch_clean_dcache((uintptr_t)extfilter, (uintptr_t)exfilter + 8);
up_clean_dcache((uintptr_t)extfilter, (uintptr_t)exfilter + 8);
/* Is this the first extended filter? */
@ -2066,7 +2065,7 @@ static int mcan_add_stdfilter(FAR struct sam_mcan_s *priv,
/* Flush the filter entry into physical RAM */
arch_clean_dcache((uintptr_t)stdfilter, (uintptr_t)stdfilter + 4);
up_clean_dcache((uintptr_t)stdfilter, (uintptr_t)stdfilter + 4);
/* Is this the first standard filter? */
@ -2953,7 +2952,7 @@ static int mcan_send(FAR struct can_dev_s *dev, FAR struct can_msg_s *msg)
/* Flush the D-Cache to memory before initiating the transfer */
msglen = 2 * sizeof(uint32_t) + nbytes;
arch_clean_dcache((uintptr_t)txbuffer, (uintptr_t)txbuffer + msglen);
up_clean_dcache((uintptr_t)txbuffer, (uintptr_t)txbuffer + msglen);
UNUSED(msglen);
/* Enable transmit interrupts from the TX FIFOQ buffer by setting TC
@ -3327,7 +3326,7 @@ static void mcan_receive(FAR struct can_dev_s *dev, FAR uint32_t *rxbuffer,
/* Invalidate the D-Cache so that we reread the RX buffer data from memory. */
nbytes = (nwords << 2);
arch_invalidate_dcache((uintptr_t)rxbuffer, (uintptr_t)rxbuffer + nbytes);
up_invalidate_dcache((uintptr_t)rxbuffer, (uintptr_t)rxbuffer + nbytes);
/* Format the CAN header */
/* Work R0 contains the CAN ID */

1
arch/arm/src/samv7/sam_mpuinit.c
View file

@ -44,7 +44,6 @@
#include <nuttx/userspace.h>
#include "mpu.h"
#include "cache.h"
#include "chip/sam_memorymap.h"
#include "sam_mpuinit.h"

5
arch/arm/src/samv7/sam_progmem.c
View file

@ -47,7 +47,6 @@
#include <arch/samv7/chip.h>
#include "up_arch.h"
#include "cache.h"
#include "chip/sam_memorymap.h"
#include "sam_progmem.h"
@ -593,7 +592,7 @@ ssize_t up_progmem_ispageerased(size_t cluster)
/* Flush and invalidate D-Cache for this address range */
address = (cluster << SAMV7_CLUSTER_SHIFT) + SAMV7_PROGMEM_START;
arch_flush_dcache(address, address + SAMV7_CLUSTER_SIZE);
up_flush_dcache(address, address + SAMV7_CLUSTER_SIZE);
/* Verify that the cluster is erased (i.e., all 0xff) */
@ -731,7 +730,7 @@ ssize_t up_progmem_write(size_t address, const void *buffer, size_t buflen)
/* Flush the data cache to memory */
arch_clean_dcache(address, address + SAMV7_PAGE_SIZE);
up_clean_dcache(address, address + SAMV7_PAGE_SIZE);
/* Send the write command */

1
arch/arm/src/samv7/sam_qspi.c
View file

@ -60,7 +60,6 @@
#include "up_internal.h"
#include "up_arch.h"
#include "cache.h"
#include "sam_gpio.h"
#include "sam_xdmac.h"

3
arch/arm/src/samv7/sam_spi.c
View file

@ -61,7 +61,6 @@
#include "up_internal.h"
#include "up_arch.h"
#include "cache.h"
#include "sam_gpio.h"
#include "sam_xdmac.h"
@ -1760,7 +1759,7 @@ static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer,
* the DMA completes
*/
arch_invalidate_dcache((uintptr_t)rxbuffer, (uintptr_t)rxbuffer + nbytes);
up_invalidate_dcache((uintptr_t)rxbuffer, (uintptr_t)rxbuffer + nbytes);
/* Use normal RX memory incrementing. */

7
arch/arm/src/samv7/sam_ssc.c
View file

@ -62,7 +62,6 @@
#include "up_internal.h"
#include "up_arch.h"
#include "cache.h"
#include "sam_gpio.h"
#include "sam_xdmac.h"
@ -1314,7 +1313,7 @@ static int ssc_rxdma_setup(struct sam_ssc_s *priv)
*/
#warning Not yet supported
#if 0
arch_invalidate_dcache((uintptr_t)apb->samp,
up_invalidate_dcache((uintptr_t)apb->samp,
(uintptr_t)apb->samp + apb->nmaxbytes);
#endif
}
@ -1730,9 +1729,9 @@ static int ssc_txdma_setup(struct sam_ssc_s *priv)
*/
#warning REVISIT
#if 1
arch_invalidate_dcache_all();
up_invalidate_dcache_all();
#else
arch_clean_dcache(samp, samp + nbytes);
up_clean_dcache(samp, samp + nbytes);
#endif
}
#if 1 /* REVISIT: Chained TX transfers */

7
arch/arm/src/samv7/sam_start.c
View file

@ -43,13 +43,13 @@
#include <assert.h>
#include <debug.h>
#include <nuttx/cache.h>
#include <nuttx/init.h>
#include <arch/board/board.h>
#include "up_arch.h"
#include "up_internal.h"
#include "cache.h"
#ifdef CONFIG_ARCH_FPU
# include "nvic.h"
#endif
@ -391,9 +391,8 @@ void __start(void)
/* Enable I- and D-Caches */
arch_dcache_writethrough();
arch_enable_icache();
arch_enable_dcache();
up_enable_icache();
up_enable_dcache();
/* Perform early serial initialization */

7
arch/arm/src/samv7/sam_usbdevhs.c
View file

@ -70,7 +70,6 @@
#include "up_arch.h"
#include "up_internal.h"
#include "cache.h"
#include "chip.h"
#include "sam_periphclks.h"
@ -972,7 +971,7 @@ static void sam_dma_single(uint8_t epno, struct sam_req_s *privreq,
/* Flush the contents of the DMA buffer to RAM */
buffer = (uintptr_t)&privreq->req.buf[privreq->req.xfrd];
arch_clean_dcache(buffer, buffer + privreq->inflight);
up_clean_dcache(buffer, buffer + privreq->inflight);
/* Set up the DMA */
@ -2584,7 +2583,7 @@ static void sam_dma_interrupt(struct sam_usbdev_s *priv, int epno)
DEBUGASSERT(USB_ISEPOUT(privep->ep.eplog));
buf = &privreq->req.buf[privreq->req.xfrd];
arch_invalidate_dcache((uintptr_t)buf, (uintptr_t)buf + xfrsize);
up_invalidate_dcache((uintptr_t)buf, (uintptr_t)buf + xfrsize);
/* Complete this transfer, return the request to the class
* implementation, and try to start the next, queue read request.
@ -2643,7 +2642,7 @@ static void sam_dma_interrupt(struct sam_usbdev_s *priv, int epno)
*/
buf = &privreq->req.buf[privreq->req.xfrd];
arch_invalidate_dcache((uintptr_t)buf, (uintptr_t)buf + xfrsize);
up_invalidate_dcache((uintptr_t)buf, (uintptr_t)buf + xfrsize);
/* Complete this transfer, return the request to the class
* implementation, and try to start the next, queue read request.

9
arch/arm/src/samv7/sam_xdmac.c
View file

@ -51,7 +51,6 @@
#include <arch/samv7/chip.h>
#include "up_arch.h"
#include "cache.h"
#include "up_internal.h"
#include "sched/sched.h"
@ -1090,7 +1089,7 @@ sam_allocdesc(struct sam_xdmach_s *xdmach, struct chnext_view1_s *prev,
* that hardware will be accessing the descriptor via DMA.
*/
arch_clean_dcache((uintptr_t)descr,
up_clean_dcache((uintptr_t)descr,
(uintptr_t)descr + sizeof(struct chnext_view1_s));
break;
}
@ -1853,7 +1852,7 @@ int sam_dmatxsetup(DMA_HANDLE handle, uint32_t paddr, uint32_t maddr,
/* Clean caches associated with the DMA memory */
arch_clean_dcache(maddr, maddr + nbytes);
up_clean_dcache(maddr, maddr + nbytes);
return ret;
}
@ -1934,7 +1933,7 @@ int sam_dmarxsetup(DMA_HANDLE handle, uint32_t paddr, uint32_t maddr,
/* Clean caches associated with the DMA memory */
arch_clean_dcache(maddr, maddr + nbytes);
up_clean_dcache(maddr, maddr + nbytes);
return ret;
}
@ -1972,7 +1971,7 @@ int sam_dmastart(DMA_HANDLE handle, dma_callback_t callback, void *arg)
if (xdmach->rx)
{
arch_flush_dcache(xdmach->rxaddr, xdmach->rxaddr + xdmach->rxsize);
up_flush_dcache(xdmach->rxaddr, xdmach->rxaddr + xdmach->rxsize);
}
/* Is this a single block transfer? Or a multiple block transfer? */

15
arch/arm/src/stm32f7/Make.defs
View file

@ -72,14 +72,7 @@ CMN_ASRCS += up_exception.S
endif
CMN_CSRCS += up_vectors.c
ifeq ($(CONFIG_ARMV7M_DCACHE),y)
CMN_CSRCS += arch_enable_dcache.c arch_disable_dcache.c
CMN_CSRCS += arch_invalidate_dcache.c arch_invalidate_dcache_all.c
ifneq ($(CONFIG_ARMV7M_DCACHE_WRITETHROUGH),y)
CMN_CSRCS += arch_clean_dcache.c arch_clean_dcache_all.c
CMN_CSRCS += arch_flush_dcache.c arch_flush_dcache_all.c
endif
endif
CMN_CSRCS += up_cache.c
ifeq ($(CONFIG_ARCH_FPU),y)
CMN_ASRCS += up_fpu.S
@ -98,12 +91,6 @@ CMN_UASRCS += up_signal_handler.S
endif
endif
ifeq ($(CONFIG_ELF),y)
CMN_CSRCS += up_coherent_dcache.c
else ifeq ($(CONFIG_MODULE),y)
CMN_CSRCS += up_coherent_dcache.c
endif
ifeq ($(CONFIG_STACK_COLORATION),y)
CMN_CSRCS += up_checkstack.c
endif

3
arch/arm/src/stm32f7/stm32_adc.c
View file

@ -69,7 +69,6 @@
#include "up_internal.h"
#include "up_arch.h"
#include "cache.h"
#include "chip.h"
#include "stm32_rcc.h"
#include "stm32_tim.h"
@ -1190,7 +1189,7 @@ static void adc_dmaconvcallback(DMA_HANDLE handle, uint8_t isr, FAR void *arg)
FAR struct stm32_dev_s *priv = (FAR struct stm32_dev_s *)dev->ad_priv;
int i;
arch_invalidate_dcache((uintptr_t)priv->dmabuffer,
up_invalidate_dcache((uintptr_t)priv->dmabuffer,
(uintptr_t)priv->dmabuffer + sizeof(priv->dmabuffer));
/* Verify that the upper-half driver has bound its callback functions */

4
arch/arm/src/stm32f7/stm32_dma.c
View file

@ -918,8 +918,8 @@ bool stm32_dmacapable(uint32_t maddr, uint32_t count, uint32_t ccr)
# if defined(CONFIG_ARMV7M_DCACHE) && !defined(CONFIG_ARMV7M_DCACHE_WRITETHROUGH)
/* buffer alignment is required for DMA transfers with dcache in buffered
* mode (not write-through) because a) arch_invalidate_dcache could lose
* buffered writes and b) arch_flush_dcache could corrupt adjacent memory if
* mode (not write-through) because a) up_invalidate_dcache could lose
* buffered writes and b) up_flush_dcache could corrupt adjacent memory if
* the maddr and the mend+1, the next next address are not on
* ARMV7M_DCACHE_LINESIZE boundaries.
*/

27
arch/arm/src/stm32f7/stm32_ethernet.c
View file

@ -61,7 +61,6 @@
# include <nuttx/net/pkt.h>
#endif
#include "cache.h"
#include "up_internal.h"
#include "chip/stm32_syscfg.h"
@ -1067,7 +1066,7 @@ static int stm32_transmit(struct stm32_ethmac_s *priv)
/* Flush the contents of the TX buffer into physical memory */
arch_clean_dcache((uintptr_t)priv->dev.d_buf,
up_clean_dcache((uintptr_t)priv->dev.d_buf,
(uintptr_t)priv->dev.d_buf + priv->dev.d_len);
/* Is the size to be sent greater than the size of the Ethernet buffer? */
@ -1140,7 +1139,7 @@ static int stm32_transmit(struct stm32_ethmac_s *priv)
* memory.
*/
arch_clean_dcache((uintptr_t)txdesc,
up_clean_dcache((uintptr_t)txdesc,
(uintptr_t)txdesc + sizeof(struct eth_txdesc_s));
/* Get the next descriptor in the link list */
@ -1176,7 +1175,7 @@ static int stm32_transmit(struct stm32_ethmac_s *priv)
* memory.
*/
arch_clean_dcache((uintptr_t)txdesc,
up_clean_dcache((uintptr_t)txdesc,
(uintptr_t)txdesc + sizeof(struct eth_txdesc_s));
/* Point to the next available TX descriptor */
@ -1528,7 +1527,7 @@ static void stm32_freesegment(struct stm32_ethmac_s *priv,
* memory.
*/
arch_clean_dcache((uintptr_t)rxdesc,
up_clean_dcache((uintptr_t)rxdesc,
(uintptr_t)rxdesc + sizeof(struct eth_rxdesc_s));
/* Get the next RX descriptor in the chain (cache coherency should not
@ -1614,7 +1613,7 @@ static int stm32_recvframe(struct stm32_ethmac_s *priv)
/* Forces the first RX descriptor to be re-read from physical memory */
arch_invalidate_dcache((uintptr_t)rxdesc,
up_invalidate_dcache((uintptr_t)rxdesc,
(uintptr_t)rxdesc + sizeof(struct eth_rxdesc_s));
for (i = 0;
@ -1693,7 +1692,7 @@ static int stm32_recvframe(struct stm32_ethmac_s *priv)
* physical memory.
*/
arch_clean_dcache((uintptr_t)rxcurr,
up_clean_dcache((uintptr_t)rxcurr,
(uintptr_t)rxdesc + sizeof(struct eth_rxdesc_s));
/* Remember where we should re-start scanning and reset the segment
@ -1707,7 +1706,7 @@ static int stm32_recvframe(struct stm32_ethmac_s *priv)
* physical memory.
*/
arch_invalidate_dcache((uintptr_t)dev->d_buf,
up_invalidate_dcache((uintptr_t)dev->d_buf,
(uintptr_t)dev->d_buf + dev->d_len);
ninfo("rxhead: %p d_buf: %p d_len: %d\n",
@ -1734,7 +1733,7 @@ static int stm32_recvframe(struct stm32_ethmac_s *priv)
/* Force the next RX descriptor to be re-read from physical memory */
arch_invalidate_dcache((uintptr_t)rxdesc,
up_invalidate_dcache((uintptr_t)rxdesc,
(uintptr_t)rxdesc + sizeof(struct eth_rxdesc_s));
}
@ -1946,7 +1945,7 @@ static void stm32_freeframe(struct stm32_ethmac_s *priv)
/* Force re-reading of the TX descriptor for physical memory */
arch_invalidate_dcache((uintptr_t)txdesc,
up_invalidate_dcache((uintptr_t)txdesc,
(uintptr_t)txdesc + sizeof(struct eth_txdesc_s));
for (i = 0; (txdesc->tdes0 & ETH_TDES0_OWN) == 0; i++)
@ -1977,7 +1976,7 @@ static void stm32_freeframe(struct stm32_ethmac_s *priv)
* physical memory.
*/
arch_clean_dcache((uintptr_t)txdesc,
up_clean_dcache((uintptr_t)txdesc,
(uintptr_t)txdesc + sizeof(struct eth_txdesc_s));
/* Check if this is the last segment of a TX frame */
@ -2010,7 +2009,7 @@ static void stm32_freeframe(struct stm32_ethmac_s *priv)
/* Force re-reading of the TX descriptor for physical memory */
arch_invalidate_dcache((uintptr_t)txdesc,
up_invalidate_dcache((uintptr_t)txdesc,
(uintptr_t)txdesc + sizeof(struct eth_txdesc_s));
}
@ -2833,7 +2832,7 @@ static void stm32_txdescinit(struct stm32_ethmac_s *priv,
/* Flush all of the initialized TX descriptors to physical memory */
arch_clean_dcache((uintptr_t)txtable,
up_clean_dcache((uintptr_t)txtable,
(uintptr_t)txtable +
TXTABLE_SIZE * sizeof(union stm32_txdesc_u));
@ -2923,7 +2922,7 @@ static void stm32_rxdescinit(struct stm32_ethmac_s *priv,
/* Flush all of the initialized RX descriptors to physical memory */
arch_clean_dcache((uintptr_t)rxtable,
up_clean_dcache((uintptr_t)rxtable,
(uintptr_t)rxtable +
RXTABLE_SIZE * sizeof(union stm32_rxdesc_u));

1
arch/arm/src/stm32f7/stm32_flash.c
View file

@ -60,7 +60,6 @@
#include "chip/stm32_flash.h"
#include "up_arch.h"
#include "cache.h"
/****************************************************************************
* Pre-processor Definitions

13
arch/arm/src/stm32f7/stm32_sdmmc.c
View file

@ -60,7 +60,6 @@
#include <nuttx/irq.h>
#include <arch/board/board.h>
#include "cache.h"
#include "chip.h"
#include "up_arch.h"
@ -2995,7 +2994,7 @@ static int stm32_dmarecvsetup(FAR struct sdio_dev_s *dev, FAR uint8_t *buffer,
#else
# if defined(CONFIG_ARMV7M_DCACHE) && !defined(CONFIG_ARMV7M_DCACHE_WRITETHROUGH)
/* buffer alignment is required for DMA transfers with dcache in buffered
* mode (not write-through) because the arch_invalidate_dcache could lose
* mode (not write-through) because the up_invalidate_dcache could lose
* buffered buffered writes if the buffer alignment and sizes are not on
* ARMV7M_DCACHE_LINESIZE boundaries.
*/
@ -3044,7 +3043,7 @@ static int stm32_dmarecvsetup(FAR struct sdio_dev_s *dev, FAR uint8_t *buffer,
if ((uintptr_t)buffer < DTCM_START || (uintptr_t)buffer + buflen > DTCM_END)
{
#if !defined(CONFIG_ARCH_HAVE_SDIO_DELAYED_INVLDT)
arch_invalidate_dcache_by_addr((uintptr_t)buffer,(uintptr_t)buffer + buflen);
up_invalidate_dcache((uintptr_t)buffer,(uintptr_t)buffer + buflen);
#endif
}
@ -3090,7 +3089,7 @@ static int stm32_dmasendsetup(FAR struct sdio_dev_s *dev,
#else
# if defined(CONFIG_ARMV7M_DCACHE) && !defined(CONFIG_ARMV7M_DCACHE_WRITETHROUGH)
/* buffer alignment is required for DMA transfers with dcache in buffered
* mode (not write-through) because the arch_flush_dcache would corrupt adjacent
* mode (not write-through) because the up_flush_dcache would corrupt adjacent
* memory if the buffer alignment and sizes are not on ARMV7M_DCACHE_LINESIZE
* boundaries.
*/
@ -3117,9 +3116,9 @@ static int stm32_dmasendsetup(FAR struct sdio_dev_s *dev,
if ((uintptr_t)buffer < DTCM_START || (uintptr_t)buffer + buflen > DTCM_END)
{
#ifdef CONFIG_ARMV7M_DCACHE_WRITETHROUGH
arch_invalidate_dcache_by_addr((uintptr_t)buffer, (uintptr_t)buffer + buflen);
up_invalidate_dcache((uintptr_t)buffer, (uintptr_t)buffer + buflen);
#else
arch_flush_dcache((uintptr_t)buffer, (uintptr_t)buffer + buflen);
up_flush_dcache((uintptr_t)buffer, (uintptr_t)buffer + buflen);
#endif
}
@ -3184,7 +3183,7 @@ static int stm32_dmadelydinvldt(FAR struct sdio_dev_s *dev,
if ((uintptr_t)buffer < DTCM_START ||
(uintptr_t)buffer + buflen > DTCM_END)
{
arch_invalidate_dcache_by_addr((uintptr_t)buffer,
up_invalidate_dcache((uintptr_t)buffer,
(uintptr_t)buffer + buflen);
}

3
arch/arm/src/stm32f7/stm32_serial.c
View file

@ -59,7 +59,6 @@
# include <termios.h>
#endif
#include "cache.h"
#include "up_arch.h"
#include "up_internal.h"
@ -2575,7 +2574,7 @@ static int up_dma_receive(struct uart_dev_s *dev, unsigned int *status)
/* Invalidate the DMA buffer range */
addr = (uintptr_t)&priv->rxfifo[priv->rxdmanext];
arch_invalidate_dcache(addr, addr + rxdmaavail);
up_invalidate_dcache(addr, addr + rxdmaavail);
/* We don't need to invalidate the data cache for the next
* rxdmaavail number of next bytes.

7
arch/arm/src/stm32f7/stm32_spi.c
View file

@ -82,7 +82,6 @@
#include "up_internal.h"
#include "up_arch.h"
#include "cache.h"
#include "chip.h"
#include "stm32_gpio.h"
#include "stm32_dma.h"
@ -1712,7 +1711,7 @@ static void spi_exchange(FAR struct spi_dev_s *dev, FAR const void *txbuffer,
if (txbuffer)
{
arch_flush_dcache((uintptr_t)txbuffer, (uintptr_t)txbuffer + buflen);
up_flush_dcache((uintptr_t)txbuffer, (uintptr_t)txbuffer + buflen);
}
#ifdef CONFIG_SPI_TRIGGER
@ -1751,12 +1750,12 @@ static void spi_exchange(FAR struct spi_dev_s *dev, FAR const void *txbuffer,
if (rxbuffer)
{
arch_invalidate_dcache((uintptr_t)rxbuffer,
up_invalidate_dcache((uintptr_t)rxbuffer,
(uintptr_t)rxbuffer + buflen);
}
else
{
arch_invalidate_dcache((uintptr_t)rxdummy,
up_invalidate_dcache((uintptr_t)rxdummy,
(uintptr_t)rxdummy + sizeof(rxdummy));
}
}

7
arch/arm/src/stm32f7/stm32_start.c
View file

@ -43,13 +43,13 @@
#include <assert.h>
#include <debug.h>
#include <nuttx/cache.h>
#include <nuttx/init.h>
#include <arch/board/board.h>
#include "up_arch.h"
#include "up_internal.h"
#include "cache.h"
#ifdef CONFIG_ARCH_FPU
# include "nvic.h"
#endif
@ -372,9 +372,8 @@ void __start(void)
/* Enable I- and D-Caches */
arch_dcache_writethrough();
arch_enable_icache();
arch_enable_dcache();
up_enable_icache();
up_enable_dcache();
/* Perform early serial initialization */

16
arch/arm/src/stm32h7/Make.defs
View file

@ -64,15 +64,7 @@ CMN_ASRCS += up_exception.S
endif
CMN_CSRCS += up_vectors.c
ifeq ($(CONFIG_ARMV7M_DCACHE),y)
CMN_CSRCS += arch_enable_dcache.c arch_disable_dcache.c
CMN_CSRCS += arch_invalidate_dcache.c arch_invalidate_dcache_all.c
ifneq ($(CONFIG_ARMV7M_DCACHE_WRITETHROUGH),y)
CMN_CSRCS += arch_clean_dcache.c arch_clean_dcache_all.c
CMN_CSRCS += arch_flush_dcache.c arch_flush_dcache_all.c
endif
endif
CMN_CSRCS += up_cache.c
ifeq ($(CONFIG_ARCH_FPU),y)
CMN_ASRCS += up_fpu.S
CMN_CSRCS += up_copyarmstate.c
@ -94,12 +86,6 @@ CMN_UASRCS += up_signal_handler.S
endif
endif
ifeq ($(CONFIG_ELF),y)
CMN_CSRCS += up_coherent_dcache.c
else ifeq ($(CONFIG_MODULE),y)
CMN_CSRCS += up_coherent_dcache.c
endif
ifeq ($(CONFIG_STACK_COLORATION),y)
CMN_CSRCS += up_checkstack.c
endif

1
arch/arm/src/stm32h7/stm32_serial.c
View file

@ -59,7 +59,6 @@
# include <termios.h>
#endif
#include "cache.h"
#include "up_arch.h"
#include "up_internal.h"

7
arch/arm/src/stm32h7/stm32_spi.c
View file

@ -83,7 +83,6 @@
#include "up_internal.h"
#include "up_arch.h"
#include "cache.h"
#include "chip.h"
#include "stm32_rcc.h"
#include "stm32_gpio.h"
@ -1763,7 +1762,7 @@ static void spi_exchange(FAR struct spi_dev_s *dev, FAR const void *txbuffer,
if (txbuffer)
{
arch_flush_dcache((uintptr_t)txbuffer, (uintptr_t)txbuffer + buflen);
up_flush_dcache((uintptr_t)txbuffer, (uintptr_t)txbuffer + buflen);
}
/* REVISIT: Master transfer start */
@ -1806,12 +1805,12 @@ static void spi_exchange(FAR struct spi_dev_s *dev, FAR const void *txbuffer,
if (rxbuffer)
{
arch_invalidate_dcache((uintptr_t)rxbuffer,
up_invalidate_dcache((uintptr_t)rxbuffer,
(uintptr_t)rxbuffer + buflen);
}
else
{
arch_invalidate_dcache((uintptr_t)rxdummy,
up_invalidate_dcache((uintptr_t)rxdummy,
(uintptr_t)rxdummy + sizeof(rxdummy));
}
}

7
arch/arm/src/stm32h7/stm32_start.c
View file

@ -43,13 +43,13 @@
#include <assert.h>
#include <debug.h>
#include <nuttx/cache.h>
#include <nuttx/init.h>
#include <arch/board/board.h>
#include "up_arch.h"
#include "up_internal.h"
#include "cache.h"
#ifdef CONFIG_ARCH_FPU
# include "nvic.h"
#endif
@ -390,9 +390,8 @@ void __start(void)
/* Enable I- and D-Caches */
arch_dcache_writethrough();
arch_enable_icache();
arch_enable_dcache();
up_enable_icache();
up_enable_dcache();
showprogress('C');
/* Perform early serial initialization */

1
arch/arm/src/stm32l4/stm32l4_qspi.c
View file

@ -60,7 +60,6 @@
#include "up_internal.h"
#include "up_arch.h"
#include "cache.h"
#include "stm32l4_gpio.h"
#include "stm32l4_dma.h"

9
arch/arm/src/stm32l4/stm32l4_sdmmc.c
View file

@ -60,7 +60,6 @@
#include <nuttx/irq.h>
#include <arch/board/board.h>
#include "cache.h"
#include "chip.h"
#include "up_arch.h"
@ -2813,7 +2812,7 @@ static int stm32_dmarecvsetup(FAR struct sdio_dev_s *dev, FAR uint8_t *buffer,
#else
# if defined(CONFIG_ARMV7M_DCACHE) && !defined(CONFIG_ARMV7M_DCACHE_WRITETHROUGH)
/* buffer alignment is required for DMA transfers with dcache in buffered
* mode (not write-through) because the arch_invalidate_dcache could lose
* mode (not write-through) because the up_invalidate_dcache could lose
* buffered buffered writes if the buffer alignment and sizes are not on
* ARMV7M_DCACHE_LINESIZE boundaries.
*/
@ -2859,7 +2858,7 @@ static int stm32_dmarecvsetup(FAR struct sdio_dev_s *dev, FAR uint8_t *buffer,
/* Force RAM reread */
arch_invalidate_dcache((uintptr_t)buffer,(uintptr_t)buffer + buflen);
up_invalidate_dcache((uintptr_t)buffer,(uintptr_t)buffer + buflen);
/* Start the DMA */
@ -2903,7 +2902,7 @@ static int stm32_dmasendsetup(FAR struct sdio_dev_s *dev,
#else
# if defined(CONFIG_ARMV7M_DCACHE) && !defined(CONFIG_ARMV7M_DCACHE_WRITETHROUGH)
/* buffer alignment is required for DMA transfers with dcache in buffered
* mode (not write-through) because the arch_flush_dcache would corrupt adjacent
* mode (not write-through) because the up_flush_dcache would corrupt adjacent
* memory if the buffer alignment and sizes are not on ARMV7M_DCACHE_LINESIZE
* boundaries.
*/
@ -2927,7 +2926,7 @@ static int stm32_dmasendsetup(FAR struct sdio_dev_s *dev,
/* Flush cache to physical memory */
arch_flush_dcache((uintptr_t)buffer, (uintptr_t)buffer + buflen);
up_flush_dcache((uintptr_t)buffer, (uintptr_t)buffer + buflen);
/* Save the source buffer information for use by the interrupt handler */

6
arch/arm/src/tms570/Make.defs
View file

@ -84,11 +84,7 @@ ifeq ($(CONFIG_ARMV7R_L2CC_PL310),y)
CMN_CSRCS += arm_l2cc_pl310.c
endif
ifeq ($(CONFIG_ELF),y)
CMN_CSRCS += arm_coherent_dcache.c
else ifeq ($(CONFIG_MODULE),y)
CMN_CSRCS += arm_coherent_dcache.c
endif
CMN_CSRCS += arm_cache.c
ifeq ($(CONFIG_ARCH_FPU),y)
CMN_ASRCS += arm_savefpu.S arm_restorefpu.S

1
arch/arm/src/tms570/tms570_boot.c
View file

@ -54,7 +54,6 @@
#include "chip.h"
#include "arm.h"
#include "cache.h"
#include "fpu.h"
#include "sctlr.h"
#include "up_internal.h"

4
arch/or1k/src/common/up_initialize.c
View file

@ -68,7 +68,7 @@
****************************************************************************/
#ifdef CONFIG_OR1K_ICACHE
static void up_enable_icache(void)
void up_enable_icache(void)
{
uint32_t iccfg;
uint32_t sr;
@ -98,7 +98,7 @@ static void up_enable_icache(void)
#endif
#ifdef CONFIG_OR1K_DCACHE
static void up_enable_dcache(void)
void up_enable_dcache(void)
{
uint32_t dccfg;
uint32_t sr;

2
arch/or1k/src/mor1kx/Kconfig
View file

@ -25,10 +25,12 @@ config OR1K_CPU_FREQUENCY
config OR1K_ICACHE
bool "Enable Instruction Cache"
default n
select ARCH_ICACHE
config OR1K_DCACHE
bool "Enable Data Cache"
default n
select ARCH_DCACHE
config OR1K_MMU
bool "Enable MMU"

2
binfmt/libelf/libelf_bind.c
View file

@ -452,7 +452,7 @@ int elf_bind(FAR struct elf_loadinfo_s *loadinfo,
}
}
#elif defined(CONFIG_ARCH_HAVE_COHERENT_DCACHE)
#else
/* Ensure that the I and D caches are coherent before starting the newly
* loaded module by cleaning the D cache (i.e., flushing the D cache
* contents to memory and invalidating the I cache).

7
configs/sama5d3x-ek/src/nor_main.c
View file

@ -42,11 +42,12 @@
#include <stdio.h>
#include <debug.h>
#include <nuttx/cache.h>
#include <arch/irq.h>
#include "up_arch.h"
#include "mmu.h"
#include "cache.h"
#include "cp15_cacheops.h"
#include "sam_periphclks.h"
#include "chip/sam_hsmc.h"
@ -183,8 +184,8 @@ int nor_main(int argc, char *argv)
/* Invalidate caches and TLBs */
arch_invalidate_icache();
arch_invalidate_dcache_all();
up_invalidate_icache_all();
up_invalidate_dcache_all();
cp15_invalidate_tlbs();
/* Then jump into NOR flash */

8
configs/sama5d4-ek/src/dram_main.c
View file

@ -43,11 +43,12 @@
#include <debug.h>
#include <hex2bin.h>
#include <nuttx/cache.h>
#include <arch/irq.h>
#include "up_arch.h"
#include "mmu.h"
#include "cache.h"
#include "cp15_cacheops.h"
#include "sama5d4-ek.h"
@ -143,9 +144,8 @@ int dram_main(int argc, char *argv)
* we disable caching.
*/
arch_clean_dcache((uintptr_t)SAM_DDRCS_VSECTION,
(uintptr_t)(SAM_DDRCS_VSECTION +
CONFIG_SAMA5_DDRCS_SIZE));
up_clean_dcache((uintptr_t)SAM_DDRCS_VSECTION,
(uintptr_t)(SAM_DDRCS_VSECTION + CONFIG_SAMA5_DDRCS_SIZE));
/* Interrupts must be disabled through the following. In this
* configuration, there should only be timer interrupts. Your NuttX

1
configs/samv71-xult/src/sam_ili9488.c
View file

@ -139,7 +139,6 @@
#include <nuttx/irq.h>
#include <arch/board/board.h>
#include "cache.h"
#include "up_arch.h"
#include "sam_gpio.h"
#include "sam_periphclks.h"

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