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arch/arm/src/tiva: Rename TM4C123GH6PMI identifiers to TM4C123GH6PM
Rationale: In terms of firmware programming, there is no functional difference between these parts: TM4C123GH6PMI7 TM4C123GH6PMI7R TM4C123GH6PMT7 TM4C123GH6PMT7R From a programming standpoint, all of the above parts are TM4C123GH6PM, which means it doesn't make sense to differentiate between PM and PMI. (The PM means 64-LQFP. The I means temperature range -40C to +85C. It could be T meaning -40C to +105C. The R means it ships in Tape and Reel packaging as opposed to Tray.) arch/arm/include/tiva/chip.h: arch/arm/include/tiva/tm4c_irq.h: arch/arm/src/tiva/hardware/lm/lm3s_flash.h: arch/arm/src/tiva/hardware/tm4c/tm4c_pinmap.h: configs/tm4c123g-launchpad/README.txt: configs/tm4c123g-launchpad/nsh/defconfig: Rename: CONFIG_ARCH_CHIP_TM4C123GH6PMI to CONFIG_ARCH_CHIP_TM4C123GH6PM arch/arm/src/tiva/Kconfig: configs/Kconfig: Rename: ARCH_CHIP_TM4C123GH6PMI to ARCH_CHIP_TM4C123GH6PM arch/arm/src/tiva/hardware/tm4c/tm4c_memorymap.h: Rename: CONFIG_ARCH_CHIP_TM4C123GH6PMI to CONFIG_ARCH_CHIP_TM4C123GH6PM Remove redundant Peripheral Base Addresses section. There were two identical copies, one for CONFIG_ARCH_CHIP_TM4C123GH6PMI and another for CONFIG_ARCH_CHIP_TM4C123GH6PM.
This commit is contained in:
Nathan Hartman
Gregory Nutt
parent
4f27140331
commit
6e8b76c3ab
9 changed files with 10 additions and 81 deletions
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@ -224,7 +224,7 @@
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# define TIVA_NAES 0 /* No AES module */
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# define TIVA_NDES 0 /* No DES module */
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# define TIVA_NHASH 0 /* No SHA1/MD5 hash module */
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#elif defined(CONFIG_ARCH_CHIP_TM4C123GH6PMI)
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#elif defined(CONFIG_ARCH_CHIP_TM4C123GH6PM)
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# undef LM3S /* Not LM3S family */
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# undef LM4F /* Not LM4F family */
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# define TM4C 1 /* TM4C family */
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@ -210,7 +210,7 @@
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# define NR_IRQS (155) /* (Really fewer because of reserved vectors) */
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#elif defined(CONFIG_ARCH_CHIP_TM4C123GH6PMI)
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#elif defined(CONFIG_ARCH_CHIP_TM4C123GH6PM)
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# define TIVA_IRQ_GPIOA (16) /* Vector 16: GPIO Port A */
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# define TIVA_IRQ_GPIOB (17) /* Vector 17: GPIO Port B */
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# define TIVA_IRQ_GPIOC (18) /* Vector 18: GPIO Port C */
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@ -92,8 +92,8 @@ config ARCH_CHIP_TM4C123GH6ZRB
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select TIVA_HAVE_I2C4
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select TIVA_HAVE_I2C5
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config ARCH_CHIP_TM4C123GH6PMI
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bool "TM4C123GH6PMI"
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config ARCH_CHIP_TM4C123GH6PM
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bool "TM4C123GH6PM"
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depends on ARCH_CHIP_TIVA
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select ARCH_CHIP_TM4C
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select ARCH_CHIP_TM4C123
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@ -51,7 +51,7 @@
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#if defined(CONFIG_ARCH_CHIP_LM3S6965) || defined(CONFIG_ARCH_CHIP_LM4F120) || \
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defined(CONFIG_ARCH_CHIP_LM3S8962) || defined(CONFIG_ARCH_CHIP_LM3S9B96) || \
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defined(CONFIG_ARCH_CHIP_LM3S9B92) || \
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defined(CONFIG_ARCH_CHIP_TM4C123GH6ZRB) || defined(CONFIG_ARCH_CHIP_TM4C123GH6PMI)
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defined(CONFIG_ARCH_CHIP_TM4C123GH6ZRB) || defined(CONFIG_ARCH_CHIP_TM4C123GH6PM)
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/* These parts all support a 1KiB erase page size and a total FLASH memory size
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* of 256Kib or 256 pages.
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@ -70,7 +70,7 @@
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# define TIVA_ETM_BASE 0xe0041000 /* -0xe0041fff: Embedded Trace Macrocell */
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/* -0xffffffff: Reserved */
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#elif defined(CONFIG_ARCH_CHIP_TM4C123GH6PMI)
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#elif defined(CONFIG_ARCH_CHIP_TM4C123GH6PM)
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# define TIVA_FLASH_BASE 0x00000000 /* -0x0003ffff: On-chip FLASH */
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/* -0x00ffffff: Reserved */
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# define TIVA_ROM_BASE 0x01000000 /* -0x1fffffff: Reserved for ROM */
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@ -207,77 +207,6 @@
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# define TIVA_SYSCON_BASE (TIVA_PERIPH_BASE + 0xfe000) /* -0xfefff: System Control */
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# define TIVA_UDMA_BASE (TIVA_PERIPH_BASE + 0xff000) /* -0xfffff: Micro Direct Memory Access */
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#elif defined(CONFIG_ARCH_CHIP_TM4C123GH6PMI)
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/* Peripheral Base Addresses */
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# define TIVA_WDOG0_BASE (TIVA_PERIPH_BASE + 0x00000) /* -0x00fff: Watchdog Timer 0 */
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# define TIVA_WDOG1_BASE (TIVA_PERIPH_BASE + 0x01000) /* -0x00fff: Watchdog Timer 1 */
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/* -0x03fff: Reserved */
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# define TIVA_GPIOA_BASE (TIVA_PERIPH_BASE + 0x04000) /* -0x04fff: GPIO Port A */
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# define TIVA_GPIOB_BASE (TIVA_PERIPH_BASE + 0x05000) /* -0x05fff: GPIO Port B */
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# define TIVA_GPIOC_BASE (TIVA_PERIPH_BASE + 0x06000) /* -0x06fff: GPIO Port C */
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# define TIVA_GPIOD_BASE (TIVA_PERIPH_BASE + 0x07000) /* -0x07fff: GPIO Port D */
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# define TIVA_SSI0_BASE (TIVA_PERIPH_BASE + 0x08000) /* -0x08fff: SSI0 */
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# define TIVA_SSI1_BASE (TIVA_PERIPH_BASE + 0x09000) /* -0x09fff: SSI1 */
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# define TIVA_SSI2_BASE (TIVA_PERIPH_BASE + 0x0a000) /* -0x0afff: SSI2 */
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# define TIVA_SSI3_BASE (TIVA_PERIPH_BASE + 0x0b000) /* -0x0bfff: SSI3 */
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# define TIVA_UART0_BASE (TIVA_PERIPH_BASE + 0x0c000) /* -0x0cfff: UART0 */
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# define TIVA_UART1_BASE (TIVA_PERIPH_BASE + 0x0d000) /* -0x0dfff: UART1 */
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# define TIVA_UART2_BASE (TIVA_PERIPH_BASE + 0x0e000) /* -0x0efff: UART2 */
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# define TIVA_UART3_BASE (TIVA_PERIPH_BASE + 0x0f000) /* -0x0ffff: UART3 */
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# define TIVA_UART4_BASE (TIVA_PERIPH_BASE + 0x10000) /* -0x10fff: UART4 */
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# define TIVA_UART5_BASE (TIVA_PERIPH_BASE + 0x11000) /* -0x11fff: UART5 */
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# define TIVA_UART6_BASE (TIVA_PERIPH_BASE + 0x12000) /* -0x12fff: UART6 */
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# define TIVA_UART7_BASE (TIVA_PERIPH_BASE + 0x13000) /* -0x13fff: UART7 */
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/* -0x1ffff: Reserved */
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# define TIVA_I2C0_BASE (TIVA_PERIPH_BASE + 0x20000) /* -0x20fff: I2C0 */
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# define TIVA_I2C1_BASE (TIVA_PERIPH_BASE + 0x21000) /* -0x21fff: I2C1 */
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# define TIVA_I2C2_BASE (TIVA_PERIPH_BASE + 0x22000) /* -0x22fff: I2C2 */
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# define TIVA_I2C3_BASE (TIVA_PERIPH_BASE + 0x23000) /* -0x23fff: I2C3 */
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# define TIVA_GPIOE_BASE (TIVA_PERIPH_BASE + 0x24000) /* -0x24fff: GPIO Port E */
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# define TIVA_GPIOF_BASE (TIVA_PERIPH_BASE + 0x25000) /* -0x25fff: GPIO Port F */
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# define TIVA_PWM0_BASE (TIVA_PERIPH_BASE + 0x28000) /* -0x28fff: PWM 0 */
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# define TIVA_PWM1_BASE (TIVA_PERIPH_BASE + 0x29000) /* -0x29fff: PWM 1 */
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/* -0x2ffff: Reserved */
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# define TIVA_TIMER0_BASE (TIVA_PERIPH_BASE + 0x30000) /* -0x30fff: 16/32 Timer 0 */
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# define TIVA_TIMER1_BASE (TIVA_PERIPH_BASE + 0x31000) /* -0x31fff: 16/32 Timer 1 */
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# define TIVA_TIMER2_BASE (TIVA_PERIPH_BASE + 0x32000) /* -0x32fff: 16/32 Timer 2 */
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# define TIVA_TIMER3_BASE (TIVA_PERIPH_BASE + 0x33000) /* -0x33fff: 16/32 Timer 3 */
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# define TIVA_TIMER4_BASE (TIVA_PERIPH_BASE + 0x34000) /* -0x34fff: 16/32 Timer 4 */
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# define TIVA_TIMER5_BASE (TIVA_PERIPH_BASE + 0x35000) /* -0x35fff: 16/32 Timer 5 */
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# define TIVA_WTIMER0_BASE (TIVA_PERIPH_BASE + 0x36000) /* -0x36fff: 32/64 Wide Timer 0 */
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# define TIVA_WTIMER1_BASE (TIVA_PERIPH_BASE + 0x37000) /* -0x37fff: 32/64 Wide Timer 1 */
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# define TIVA_ADC0_BASE (TIVA_PERIPH_BASE + 0x38000) /* -0x38fff: ADC 0 */
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# define TIVA_ADC1_BASE (TIVA_PERIPH_BASE + 0x39000) /* -0x39fff: ADC 1 */
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/* -0x3bfff: Reserved */
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# define TIVA_CMP_BASE (TIVA_PERIPH_BASE + 0x3c000) /* -0x3cfff: Analog Comparators */
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/* -0x3ffff: Reserved */
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# define TIVA_CAN0_BASE (TIVA_PERIPH_BASE + 0x40000) /* -0x40fff: CAN Controller 0 */
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# define TIVA_CAN1_BASE (TIVA_PERIPH_BASE + 0x41000) /* -0x41fff: CAN Controller 1 */
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/* -0x4bfff: Reserved */
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# define TIVA_WTIMER2_BASE (TIVA_PERIPH_BASE + 0x4c000) /* -0x4cfff: 32/64 Wide Timer 2 */
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# define TIVA_WTIMER3_BASE (TIVA_PERIPH_BASE + 0x4d000) /* -0x4dfff: 32/64 Wide Timer 3 */
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# define TIVA_WTIMER4_BASE (TIVA_PERIPH_BASE + 0x4e000) /* -0x4efff: 32/64 Wide Timer 4 */
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# define TIVA_WTIMER5_BASE (TIVA_PERIPH_BASE + 0x4f000) /* -0x4ffff: 32/64 Wide Timer 5 */
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# define TIVA_USB_BASE (TIVA_PERIPH_BASE + 0x50000) /* -0x50fff: USB */
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/* -0x57fff: Reserved */
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# define TIVA_GPIOAAHB_BASE (TIVA_PERIPH_BASE + 0x58000) /* -0x58fff: GPIO Port A (AHB aperture) */
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# define TIVA_GPIOBAHB_BASE (TIVA_PERIPH_BASE + 0x59000) /* -0x59fff: GPIO Port B (AHB aperture) */
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# define TIVA_GPIOCAHB_BASE (TIVA_PERIPH_BASE + 0x5a000) /* -0x5afff: GPIO Port C (AHB aperture) */
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# define TIVA_GPIODAHB_BASE (TIVA_PERIPH_BASE + 0x5b000) /* -0x5bfff: GPIO Port D (AHB aperture) */
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# define TIVA_GPIOEAHB_BASE (TIVA_PERIPH_BASE + 0x5c000) /* -0x5cfff: GPIO Port E (AHB aperture) */
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# define TIVA_GPIOFAHB_BASE (TIVA_PERIPH_BASE + 0x5d000) /* -0x5dfff: GPIO Port F (AHB aperture) */
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/* -0xaefff: Reserved */
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# define TIVA_EEPROM_BASE (TIVA_PERIPH_BASE + 0xaf000) /* -0xaffff: EEPROM and Key Locker */
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/* -0xf8fff: Reserved */
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# define TIVA_SYSEXC_BASE (TIVA_PERIPH_BASE + 0xf9000) /* -0xf9fff: System Exception Control */
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/* -0xfbfff: Reserved */
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# define TIVA_HIBERNATE_BASE (TIVA_PERIPH_BASE + 0xfc000) /* -0xfcfff: Hibernation Controller */
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# define TIVA_FLASHCON_BASE (TIVA_PERIPH_BASE + 0xfd000) /* -0xfdfff: FLASH Control */
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# define TIVA_SYSCON_BASE (TIVA_PERIPH_BASE + 0xfe000) /* -0xfefff: System Control */
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# define TIVA_UDMA_BASE (TIVA_PERIPH_BASE + 0xff000) /* -0xfffff: Micro Direct Memory Access */
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#elif defined(CONFIG_ARCH_CHIP_TM4C123GH6PM)
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/* Peripheral Base Addresses */
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@ -451,7 +451,7 @@
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# define GPIO_WTIM5_CCP1_3 (GPIO_FUNC_PFIO | GPIO_ALT_7 | GPIO_PORTQ | GPIO_PIN_7)
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# define GPIO_WTIM5_CCP1_4 (GPIO_FUNC_PFIO | GPIO_ALT_8 | GPIO_PORTM | GPIO_PIN_3)
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#elif defined(CONFIG_ARCH_CHIP_TM4C123GH6PMI)
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#elif defined(CONFIG_ARCH_CHIP_TM4C123GH6PM)
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# define GPIO_ADC_AIN0 (GPIO_FUNC_ANINPUT | GPIO_PORTE | GPIO_PIN_3)
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# define GPIO_ADC_AIN1 (GPIO_FUNC_ANINPUT | GPIO_PORTE | GPIO_PIN_2)
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@ -1618,7 +1618,7 @@ config ARCH_BOARD_TEENSY_LC
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config ARCH_BOARD_TM4C123G_LAUNCHPAD
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bool "Tiva TM4C123G LaunchPad"
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depends on ARCH_CHIP_TM4C123GH6PMI
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depends on ARCH_CHIP_TM4C123GH6PM
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select ARCH_HAVE_LEDS
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select ARCH_HAVE_BUTTONS
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select ARCH_HAVE_IRQBUTTONS
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@ -467,7 +467,7 @@ TM4C123G LaunchPad Configuration Options
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CONFIG_ARCH_CHIP_name - For use in C code to identify the exact
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chip:
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CONFIG_ARCH_CHIP_TM4C123GH6PMI
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CONFIG_ARCH_CHIP_TM4C123GH6PM
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CONFIG_ARCH_BOARD - Identifies the configs subdirectory and
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hence, the board that supports the particular chip or SoC.
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@ -13,7 +13,7 @@ CONFIG_ARCH_BOARD="tm4c123g-launchpad"
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CONFIG_ARCH_BOARD_TM4C123G_LAUNCHPAD=y
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CONFIG_ARCH_CHIP_TIVA=y
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CONFIG_ARCH_CHIP_TM4C123=y
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CONFIG_ARCH_CHIP_TM4C123GH6PMI=y
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CONFIG_ARCH_CHIP_TM4C123GH6PM=y
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CONFIG_ARCH_CHIP_TM4C=y
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CONFIG_ARCH_STACKDUMP=y
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CONFIG_ARMV7M_OABI_TOOLCHAIN=y
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