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Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
This commit is contained in:
Xiang Xiao 2023-12-10 10:53:03 +08:00 committed by Alan Carvalho de Assis
parent 02aeb66644
commit ca5a9c711a
127 changed files with 986 additions and 1298 deletions
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17
arch/arm/include/cxd56xx/gnss.h
View file

@ -538,17 +538,15 @@ extern "C"
#define CXD56_GNSS_IOCTL_SET_1PPS_OUTPUT 52
/**
* Get the current 1PPS output setting
/* Get the current 1PPS output setting
*
* @param[out] arg
* param[out] arg
* enable(1) or disable(0)
*/
#define CXD56_GNSS_IOCTL_GET_1PPS_OUTPUT 53
/**
* Get the firmware version
/* Get the firmware version
*
* param[in] arg
* string array of CXD56_GNSS_VERSION_MAXLEN
@ -556,8 +554,7 @@ extern "C"
#define CXD56_GNSS_IOCTL_GET_VERSION 54
/**
* Sleep the firmware
/* Sleep the firmware
*
* param[in] arg
* CXD56_GNSS_SLEEP(0) or CXD56_GNSS_DEEPSLEEP(1)
@ -565,8 +562,7 @@ extern "C"
#define CXD56_GNSS_IOCTL_SLEEP 55
/**
* Wake up the firmware
/* Wake up the firmware
*
* param arg
* Parameter is Unnecessary. Set Zero.
@ -574,8 +570,7 @@ extern "C"
#define CXD56_GNSS_IOCTL_WAKEUP 56
/**
* Reset the firmware
/* Reset the firmware
*
* param arg
* Parameter is Unnecessary. Set Zero.

2
arch/arm/include/fvp-v8r-aarch32/chip.h
View file

@ -27,7 +27,7 @@
#include <nuttx/config.h>
/* Number of bytes in @p x kibibytes/mebibytes/gibibytes */
/* Number of bytes in x kibibytes/mebibytes/gibibytes */
#define KB(x) ((x) << 10)
#define MB(x) (KB(x) << 10)

4
arch/arm/src/armv7-m/etm.h
View file

@ -8,9 +8,9 @@
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
* claim that you wrote the original software.@n
* claim that you wrote the original software.
* 2. Altered source versions must be plainly marked as such, and must not be
* misrepresented as being the original software.@n
* misrepresented as being the original software.
* 3. This notice may not be removed or altered from any source distribution.
*
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.

4
arch/arm/src/armv8-m/etm.h
View file

@ -8,9 +8,9 @@
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
* claim that you wrote the original software.@n
* claim that you wrote the original software.
* 2. Altered source versions must be plainly marked as such, and must not be
* misrepresented as being the original software.@n
* misrepresented as being the original software.
* 3. This notice may not be removed or altered from any source distribution.
*
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.

39
arch/arm/src/cxd56xx/cxd56_scu.c
View file

@ -1693,8 +1693,7 @@ static int seq_scuirqhandler(int irq, void *context, void *arg)
}
}
/**
* Detect all FIFO underrun errors
/* Detect all FIFO underrun errors
* This error may not happened because check reading bytes at seq_read().
* Thus, it is a program error when ERR1 detected.
*/
@ -1888,8 +1887,7 @@ static int seq_fifoinit(struct seq_s *seq, int fifoid, uint16_t fsize)
return -ENOMEM;
}
/**
* FIFO IDs (* is unavailable)
/* FIFO IDs (* is unavailable)
* D = Decimation FIFO
* N = Normal FIFO
*
@ -3165,8 +3163,7 @@ int seq_ioctl(struct seq_s *seq, int fifoid, int cmd, unsigned long arg)
}
break;
/**
* Enable/disable sign conversion feature
/* Enable/disable sign conversion feature
* Arg: unsigned long, 0 = off, other = on
*/
@ -3176,8 +3173,7 @@ int seq_ioctl(struct seq_s *seq, int fifoid, int cmd, unsigned long arg)
}
break;
/**
* Enable offset/gain adjustment preprocessing.
/* Enable offset/gain adjustment preprocessing.
* Arg: Pointer of adjust_xyz_t
* If arg is null, just enable offset/gain (use current setting value).
*/
@ -3201,8 +3197,7 @@ int seq_ioctl(struct seq_s *seq, int fifoid, int cmd, unsigned long arg)
}
break;
/**
* Disable offset/gain adjustment preprocessing.
/* Disable offset/gain adjustment preprocessing.
* Arg: None
*/
@ -3212,8 +3207,7 @@ int seq_ioctl(struct seq_s *seq, int fifoid, int cmd, unsigned long arg)
}
break;
/**
* Set IIR filter position and coefficiencies.
/* Set IIR filter position and coefficiencies.
* Arg: Pointer of struct math_filter_s
*/
@ -3239,8 +3233,7 @@ int seq_ioctl(struct seq_s *seq, int fifoid, int cmd, unsigned long arg)
}
break;
/**
* Set event notifier
/* Set event notifier
* Arg: Pointer of struct scuev_notify_s
*/
@ -3266,8 +3259,7 @@ int seq_ioctl(struct seq_s *seq, int fifoid, int cmd, unsigned long arg)
}
break;
/**
* Set number of elements per sample for mathfunc
/* Set number of elements per sample for mathfunc
* Arg: uint8_t
*/
@ -3277,8 +3269,7 @@ int seq_ioctl(struct seq_s *seq, int fifoid, int cmd, unsigned long arg)
}
break;
/**
* Set decimation parameters
/* Set decimation parameters
* Arg: Pointer of struct decimation_s
*/
@ -3295,8 +3286,7 @@ int seq_ioctl(struct seq_s *seq, int fifoid, int cmd, unsigned long arg)
break;
}
/**
* Now only save decimation parameters because decimation parameter
/* Now only save decimation parameters because decimation parameter
* cannot be set while sequencer running.
*/
@ -3306,8 +3296,7 @@ int seq_ioctl(struct seq_s *seq, int fifoid, int cmd, unsigned long arg)
}
break;
/**
* Set FIFO watermark
/* Set FIFO watermark
* Arg: Pointer of struct scufifo_wm_s
*/
@ -3418,15 +3407,13 @@ void scu_initialize(void)
scufifo_initialize();
/**
* If SCU clock has been already enabled, keep SCU running without loading
/* If SCU clock has been already enabled, keep SCU running without loading
* and reset of SCU firmware.
*/
if (false == cxd56_scuseq_clock_is_enabled())
{
/**
* Enable SCU clock. This process must do before loading firmware
/* Enable SCU clock. This process must do before loading firmware
* because SCU instruction RAM is not accessible.
*/

4
arch/arm/src/efm32/hardware/efm32_acmp.h
View file

@ -8,9 +8,9 @@
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
* claim that you wrote the original software.@n
* claim that you wrote the original software.
* 2. Altered source versions must be plainly marked as such, and must not be
* misrepresented as being the original software.@n
* misrepresented as being the original software.
* 3. This notice may not be removed or altered from any source distribution.
*
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.

4
arch/arm/src/efm32/hardware/efm32_adc.h
View file

@ -8,9 +8,9 @@
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
* claim that you wrote the original software.@n
* claim that you wrote the original software.
* 2. Altered source versions must be plainly marked as such, and must not be
* misrepresented as being the original software.@n
* misrepresented as being the original software.
* 3. This notice may not be removed or altered from any source distribution.
*
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.

4
arch/arm/src/efm32/hardware/efm32_aes.h
View file

@ -8,9 +8,9 @@
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
* claim that you wrote the original software.@n
* claim that you wrote the original software.
* 2. Altered source versions must be plainly marked as such, and must not be
* misrepresented as being the original software.@n
* misrepresented as being the original software.
* 3. This notice may not be removed or altered from any source distribution.
*
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.

4
arch/arm/src/efm32/hardware/efm32_burtc.h
View file

@ -8,9 +8,9 @@
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
* claim that you wrote the original software.@n
* claim that you wrote the original software.
* 2. Altered source versions must be plainly marked as such, and must not be
* misrepresented as being the original software.@n
* misrepresented as being the original software.
* 3. This notice may not be removed or altered from any source distribution.
*
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.

4
arch/arm/src/efm32/hardware/efm32_calibrate.h
View file

@ -8,9 +8,9 @@
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
* claim that you wrote the original software.@n
* claim that you wrote the original software.
* 2. Altered source versions must be plainly marked as such, and must not be
* misrepresented as being the original software.@n
* misrepresented as being the original software.
* 3. This notice may not be removed or altered from any source distribution.
*
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.

4
arch/arm/src/efm32/hardware/efm32_cmu.h
View file

@ -8,9 +8,9 @@
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
* claim that you wrote the original software.@n
* claim that you wrote the original software.
* 2. Altered source versions must be plainly marked as such, and must not be
* misrepresented as being the original software.@n
* misrepresented as being the original software.
* 3. This notice may not be removed or altered from any source distribution.
*
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.

4
arch/arm/src/efm32/hardware/efm32_dac.h
View file

@ -8,9 +8,9 @@
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
* claim that you wrote the original software.@n
* claim that you wrote the original software.
* 2. Altered source versions must be plainly marked as such, and must not be
* misrepresented as being the original software.@n
* misrepresented as being the original software.
* 3. This notice may not be removed or altered from any source distribution.
*
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.

4
arch/arm/src/efm32/hardware/efm32_devinfo.h
View file

@ -8,9 +8,9 @@
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
* claim that you wrote the original software.@n
* claim that you wrote the original software.
* 2. Altered source versions must be plainly marked as such, and must not be
* misrepresented as being the original software.@n
* misrepresented as being the original software.
* 3. This notice may not be removed or altered from any source distribution.
*
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.

4
arch/arm/src/efm32/hardware/efm32_dma.h
View file

@ -8,9 +8,9 @@
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
* claim that you wrote the original software.@n
* claim that you wrote the original software.
* 2. Altered source versions must be plainly marked as such, and must not be
* misrepresented as being the original software.@n
* misrepresented as being the original software.
* 3. This notice may not be removed or altered from any source distribution.
*
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.

4
arch/arm/src/efm32/hardware/efm32_emu.h
View file

@ -8,9 +8,9 @@
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
* claim that you wrote the original software.@n
* claim that you wrote the original software.
* 2. Altered source versions must be plainly marked as such, and must not be
* misrepresented as being the original software.@n
* misrepresented as being the original software.
* 3. This notice may not be removed or altered from any source distribution.
*
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.

4
arch/arm/src/efm32/hardware/efm32_gpio.h
View file

@ -8,9 +8,9 @@
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
* claim that you wrote the original software.@n
* claim that you wrote the original software.
* 2. Altered source versions must be plainly marked as such, and must not be
* misrepresented as being the original software.@n
* misrepresented as being the original software.
* 3. This notice may not be removed or altered from any source distribution.
*
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.

4
arch/arm/src/efm32/hardware/efm32_i2c.h
View file

@ -8,9 +8,9 @@
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
* claim that you wrote the original software.@n
* claim that you wrote the original software.
* 2. Altered source versions must be plainly marked as such, and must not be
* misrepresented as being the original software.@n
* misrepresented as being the original software.
* 3. This notice may not be removed or altered from any source distribution.
*
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.

4
arch/arm/src/efm32/hardware/efm32_lcd.h
View file

@ -8,9 +8,9 @@
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
* claim that you wrote the original software.@n
* claim that you wrote the original software.
* 2. Altered source versions must be plainly marked as such, and must not be
* misrepresented as being the original software.@n
* misrepresented as being the original software.
* 3. This notice may not be removed or altered from any source distribution.
*
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.

4
arch/arm/src/efm32/hardware/efm32_lesense.h
View file

@ -8,9 +8,9 @@
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
* claim that you wrote the original software.@n
* claim that you wrote the original software.
* 2. Altered source versions must be plainly marked as such, and must not be
* misrepresented as being the original software.@n
* misrepresented as being the original software.
* 3. This notice may not be removed or altered from any source distribution.
*
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.

4
arch/arm/src/efm32/hardware/efm32_letimer.h
View file

@ -8,9 +8,9 @@
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
* claim that you wrote the original software.@n
* claim that you wrote the original software.
* 2. Altered source versions must be plainly marked as such, and must not be
* misrepresented as being the original software.@n
* misrepresented as being the original software.
* 3. This notice may not be removed or altered from any source distribution.
*
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.

4
arch/arm/src/efm32/hardware/efm32_leuart.h
View file

@ -8,9 +8,9 @@
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
* claim that you wrote the original software.@n
* claim that you wrote the original software.
* 2. Altered source versions must be plainly marked as such, and must not be
* misrepresented as being the original software.@n
* misrepresented as being the original software.
* 3. This notice may not be removed or altered from any source distribution.
*
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.

4
arch/arm/src/efm32/hardware/efm32_msc.h
View file

@ -8,9 +8,9 @@
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
* claim that you wrote the original software.@n
* claim that you wrote the original software.
* 2. Altered source versions must be plainly marked as such, and must not be
* misrepresented as being the original software.@n
* misrepresented as being the original software.
* 3. This notice may not be removed or altered from any source distribution.
*
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.

4
arch/arm/src/efm32/hardware/efm32_pcnt.h
View file

@ -8,9 +8,9 @@
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
* claim that you wrote the original software.@n
* claim that you wrote the original software.
* 2. Altered source versions must be plainly marked as such, and must not be
* misrepresented as being the original software.@n
* misrepresented as being the original software.
* 3. This notice may not be removed or altered from any source distribution.
*
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.

4
arch/arm/src/efm32/hardware/efm32_prs.h
View file

@ -8,9 +8,9 @@
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
* claim that you wrote the original software.@n
* claim that you wrote the original software.
* 2. Altered source versions must be plainly marked as such, and must not be
* misrepresented as being the original software.@n
* misrepresented as being the original software.
* 3. This notice may not be removed or altered from any source distribution.
*
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.

4
arch/arm/src/efm32/hardware/efm32_rmu.h
View file

@ -8,9 +8,9 @@
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
* claim that you wrote the original software.@n
* claim that you wrote the original software.
* 2. Altered source versions must be plainly marked as such, and must not be
* misrepresented as being the original software.@n
* misrepresented as being the original software.
* 3. This notice may not be removed or altered from any source distribution.
*
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.

4
arch/arm/src/efm32/hardware/efm32_romtable.h
View file

@ -8,9 +8,9 @@
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
* claim that you wrote the original software.@n
* claim that you wrote the original software.
* 2. Altered source versions must be plainly marked as such, and must not be
* misrepresented as being the original software.@n
* misrepresented as being the original software.
* 3. This notice may not be removed or altered from any source distribution.
*
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.

4
arch/arm/src/efm32/hardware/efm32_rtc.h
View file

@ -8,9 +8,9 @@
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
* claim that you wrote the original software.@n
* claim that you wrote the original software.
* 2. Altered source versions must be plainly marked as such, and must not be
* misrepresented as being the original software.@n
* misrepresented as being the original software.
* 3. This notice may not be removed or altered from any source distribution.
*
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.

4
arch/arm/src/efm32/hardware/efm32_timer.h
View file

@ -8,9 +8,9 @@
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
* claim that you wrote the original software.@n
* claim that you wrote the original software.
* 2. Altered source versions must be plainly marked as such, and must not be
* misrepresented as being the original software.@n
* misrepresented as being the original software.
* 3. This notice may not be removed or altered from any source distribution.
*
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.

4
arch/arm/src/efm32/hardware/efm32_usb.h
View file

@ -8,9 +8,9 @@
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
* claim that you wrote the original software.@n
* claim that you wrote the original software.
* 2. Altered source versions must be plainly marked as such, and must not be
* misrepresented as being the original software.@n
* misrepresented as being the original software.
* 3. This notice may not be removed or altered from any source distribution.
*
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.

4
arch/arm/src/efm32/hardware/efm32_vcmp.h
View file

@ -8,9 +8,9 @@
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
* claim that you wrote the original software.@n
* claim that you wrote the original software.
* 2. Altered source versions must be plainly marked as such, and must not be
* misrepresented as being the original software.@n
* misrepresented as being the original software.
* 3. This notice may not be removed or altered from any source distribution.
*
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.

4
arch/arm/src/efm32/hardware/efm32_wdog.h
View file

@ -8,9 +8,9 @@
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
* claim that you wrote the original software.@n
* claim that you wrote the original software.
* 2. Altered source versions must be plainly marked as such, and must not be
* misrepresented as being the original software.@n
* misrepresented as being the original software.
* 3. This notice may not be removed or altered from any source distribution.
*
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.

4
arch/arm/src/efm32/hardware/efm32gg_memorymap.h
View file

@ -8,9 +8,9 @@
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
* claim that you wrote the original software.@n
* claim that you wrote the original software.
* 2. Altered source versions must be plainly marked as such, and must not be
* misrepresented as being the original software.@n
* misrepresented as being the original software.
* 3. This notice may not be removed or altered from any source distribution.
*
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.

4
arch/arm/src/efm32/hardware/efm32tg_memorymap.h
View file

@ -8,9 +8,9 @@
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
* claim that you wrote the original software.@n
* claim that you wrote the original software.
* 2. Altered source versions must be plainly marked as such, and must not be
* misrepresented as being the original software.@n
* misrepresented as being the original software.
* 3. This notice may not be removed or altered from any source distribution.
*
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.

3
arch/arm/src/lpc43xx/spifi/inc/spifilib_dev.h
View file

@ -1,11 +1,9 @@
/****************************************************************************
* arch/arm/src/lpc43xx/spifi/inc/spifilib_dev.h
*
* @note
* Copyright(C) NXP Semiconductors, 2014
* All rights reserved.
*
* @par
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* LPC products. This software is supplied "AS IS" without any warranties
@ -21,7 +19,6 @@
* application will be suitable for the specified use without further testing
* or modification.
*
* @par
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors' and its
* licensor's relevant copyrights in the software, without fee, provided that

2
arch/arm/src/nrf53/nrf53_serial.h
View file

@ -49,4 +49,4 @@
void nrf53_earlyserialinit(void);
#endif
#endif /* __ARCH_ARM_SRC_NRF53_NRF53@_SERIAL_H */
#endif /* __ARCH_ARM_SRC_NRF53_NRF53_SERIAL_H */

2
arch/arm/src/nrf91/nrf91_serial.h
View file

@ -49,4 +49,4 @@
void nrf91_earlyserialinit(void);
#endif
#endif /* __ARCH_ARM_SRC_NRF91_NRF91@_SERIAL_H */
#endif /* __ARCH_ARM_SRC_NRF91_NRF91_SERIAL_H */

13
arch/arm/src/phy62xx/error.h
View file

@ -19,14 +19,11 @@
****************************************************************************/
/****************************************************************************
* @file error.h
* @brief Global error definition
* @version 0.0
* @date 11. Feb. 2018
* @author Eagle.Lao
*
*
*
* error.h
* Global error definition
* 0.0
* 11. Feb. 2018
* Eagle.Lao
****************************************************************************/
/****************************************************************************

10
arch/arm/src/phy62xx/flash.h
View file

@ -19,11 +19,11 @@
****************************************************************************/
/****************************************************************************
* @file flash.h
* @brief Contains all functions support for flash driver
* @version 0.0
* @date 27. Nov. 2017
* @author qing.han
* flash.h
* Contains all functions support for flash driver
* 0.0
* 27. Nov. 2017
* qing.han
****************************************************************************/
/****************************************************************************

8
arch/arm/src/phy62xx/global_config.h
View file

@ -19,12 +19,10 @@
****************************************************************************/
/****************************************************************************
* @file global_config.h
* global_config.h
*
* @brief This file contains the definitions of index of
* global configuration which
* will be configured in APP project.
* This file contains the definitions of index of
* global configuration which will be configured in APP project.
*
* $Rev: $
*

10
arch/arm/src/phy62xx/gpio.h
View file

@ -19,11 +19,11 @@
****************************************************************************/
/****************************************************************************
* @file gpio.h
* @brief Contains all functions support for gpio and iomux driver
* @version 0.0
* @date 19. Oct. 2017
* @author qing.han
* gpio.h
* Contains all functions support for gpio and iomux driver
* 0.0
* 19. Oct. 2017
* qing.han
****************************************************************************/
#ifndef __ARCH_ARM_SRC_PHY62XX_GPIO_H

4
arch/arm/src/phy62xx/jump_function.h
View file

@ -20,9 +20,9 @@
/****************************************************************************
*
* @file jump_fucntion.h
* jump_fucntion.h
*
* @brief This file contains the definitions of the macros and functions
* This file contains the definitions of the macros and functions
* that are architecture dependent. The implementation of those is
* implemented in the appropriate architecture directory.
*

10
arch/arm/src/phy62xx/log.h
View file

@ -19,11 +19,11 @@
****************************************************************************/
/****************************************************************************
* @file log.h
* @brief Contains all functions support for uart driver
* @version 0.0
* @date 31. Jan. 2018
* @author eagle.han
* log.h
* Contains all functions support for uart driver
* 0.0
* 31. Jan. 2018
* eagle.han
****************************************************************************/
#ifndef ENABLE_LOG_ROM

10
arch/arm/src/phy62xx/uart.h
View file

@ -23,11 +23,11 @@
****************************************************************************/
/****************************************************************************
* @file uart.h
* @brief Contains all functions support for uart driver
* @version 0.0
* @date 19. Oct. 2017
* @author qing.han
* uart.h
* Contains all functions support for uart driver
* 0.0
* 19. Oct. 2017
* qing.han
****************************************************************************/
#ifndef __ARCH_ARM_SRC_PHY62XX_UART_H

3
arch/arm/src/rtl8720c/ameba_wdt.c
View file

@ -38,8 +38,7 @@
* Private Types
****************************************************************************/
/**
* This structure provides the private representation of the "lower-half"
/* This structure provides the private representation of the "lower-half"
* driver state structure. This structure must be cast-compatible with the
* well-known watchdog_lowerhalf_s structure.
*/

4
arch/arm/src/sam34/sam4s_nand.c
View file

@ -542,9 +542,7 @@ struct mtd_dev_s *sam_nand_initialize(int cs)
priv->cs = cs;
priv->rb = GPIO_SMC_RB;
/* Initialize the NAND hardware for this CS */
/**
/* Initialize the NAND hardware for this CS
* Note: The initialization is shown for the reference purpose only, and
* for other MCUs, refer to the Package and Pinout chapter of the
* respective data sheet.

4
arch/arm/src/samd5e5/sam_usb.c
View file

@ -392,9 +392,7 @@ enum sam_hoststate_e
USB_HOSTSTATE_CONFIGURED /* A valid configuration has been selected. */
};
/**
* @brief USB HCD pipe states
*/
/* USB HCD pipe states */
enum usb_h_pipe_state
{

7
arch/arm/src/samd5e5/sam_wdt.c
View file

@ -69,9 +69,7 @@
#define WDT_CLK_8192CYCLE 8192
#define WDT_CLK_16384CYCLE 16384
/**
* \brief Macro is used to indicate the rate of second/millisecond
*/
/* Macro is used to indicate the rate of second/millisecond */
#define WDT_PERIOD_RATE 1000
@ -79,8 +77,7 @@
* Private Types
****************************************************************************/
/**
* This structure provides the private representation of the "lower-half"
/* This structure provides the private representation of the "lower-half"
* driver state structure. This structure must be cast-compatible with the
* well-known watchdog_lowerhalf_s structure.
*/

2
arch/arm64/include/a64/chip.h
View file

@ -31,7 +31,7 @@
* Pre-processor Definitions
****************************************************************************/
/* Number of bytes in @p x kibibytes/mebibytes/gibibytes */
/* Number of bytes in x kibibytes/mebibytes/gibibytes */
#define KB(x) ((x) << 10)
#define MB(x) (KB(x) << 10)

2
arch/arm64/include/fvp-v8r/chip.h
View file

@ -31,7 +31,7 @@
* Pre-processor Definitions
****************************************************************************/
/* Number of bytes in @p x kibibytes/mebibytes/gibibytes */
/* Number of bytes in x kibibytes/mebibytes/gibibytes */
#define KB(x) ((x) << 10)
#define MB(x) (KB(x) << 10)

2
arch/arm64/include/goldfish/chip.h
View file

@ -31,7 +31,7 @@
* Pre-processor Definitions
****************************************************************************/
/* Number of bytes in @p x kibibytes/mebibytes/gibibytes */
/* Number of bytes in x kibibytes/mebibytes/gibibytes */
#define KB(x) ((x) << 10)
#define MB(x) (KB(x) << 10)

2
arch/arm64/include/imx8/chip.h
View file

@ -31,7 +31,7 @@
* Pre-processor Definitions
****************************************************************************/
/* Number of bytes in @p x kibibytes/mebibytes/gibibytes */
/* Number of bytes in x kibibytes/mebibytes/gibibytes */
#define KB(x) ((x) << 10)
#define MB(x) (KB(x) << 10)

2
arch/arm64/include/qemu/chip.h
View file

@ -31,7 +31,7 @@
* Pre-processor Definitions
****************************************************************************/
/* Number of bytes in @p x kibibytes/mebibytes/gibibytes */
/* Number of bytes in x kibibytes/mebibytes/gibibytes */
#define KB(x) ((x) << 10)
#define MB(x) (KB(x) << 10)

2
arch/arm64/include/rk3399/chip.h
View file

@ -31,7 +31,7 @@
* Pre-processor Definitions
****************************************************************************/
/* Number of bytes in @p x kibibytes/mebibytes/gibibytes */
/* Number of bytes in x kibibytes/mebibytes/gibibytes */
#define KB(x) ((x) << 10)
#define MB(x) (KB(x) << 10)

6
arch/arm64/src/common/arm64_fatal.h
View file

@ -21,11 +21,7 @@
#ifndef __ARCH_ARM64_SRC_COMMON_ARM64_FATAL_H
#define __ARCH_ARM64_SRC_COMMON_ARM64_FATAL_H
/**
* @defgroup fatal_apis Fatal error APIs
* @ingroup kernel_apis
* @{
*/
/* Fatal error APIs */
#define K_ERR_CPU_EXCEPTION (0)
#define K_ERR_CPU_MODE32 (1)

8
arch/arm64/src/common/arm64_mpu.c
View file

@ -90,9 +90,7 @@ static inline uint8_t get_num_regions(void)
/* ARM Core MPU Driver API Implementation for ARM MPU */
/**
* @brief enable the MPU
*/
/* Enable the MPU */
void arm64_core_mpu_enable(void)
{
@ -109,9 +107,7 @@ void arm64_core_mpu_enable(void)
ARM64_ISB();
}
/**
* @brief disable the MPU
*/
/* Disable the MPU */
void arm64_core_mpu_disable(void)
{

3
arch/risc-v/src/common/riscv_cpuidlestack.c
View file

@ -45,8 +45,7 @@
* Private Data
****************************************************************************/
/**
* Note:
/* Note:
* 1. QEMU-RV supports up to 8 cores currently.
* 2. RISC-V requires a 16-byte stack alignment.
*/

3
arch/risc-v/src/esp32c3/esp32c3_ble_adapter.c
View file

@ -1107,8 +1107,7 @@ static int32_t esp_queue_send_generic(void *queue, void *item,
if (ticks == OSI_FUNCS_TIME_BLOCKING || ticks == 0)
{
/**
* BLE interrupt function will call this adapter function to send
/* BLE interrupt function will call this adapter function to send
* message to message queue, so here we should call kernel API
* instead of application API
*/

16
arch/risc-v/src/esp32c3/esp32c3_partition.c
View file

@ -81,17 +81,15 @@ enum ota_img_ctrl_e
enum ota_img_state_e
{
/**
* Monitor the first boot. In bootloader of esp-idf this state is changed
* to ESP_OTA_IMG_PENDING_VERIFY if this bootloader enable app rollback.
/* Monitor the first boot. In bootloader of esp-idf this state is changed
* to ESP_OTA_IMG_PENDING_VERIFY if this bootloader enable app rollback.
*
* So this driver doesn't use this state currently.
* So this driver doesn't use this state currently.
*/
OTA_IMG_NEW = 0x0,
/**
* First boot for this app was. If while the second boot this state is then
/* First boot for this app was. If while the second boot this state is then
* it will be changed to ABORTED if this bootloader enable app rollback.
*
* So this driver doesn't use this state currently.
@ -107,8 +105,7 @@ enum ota_img_state_e
OTA_IMG_INVALID = 0x3,
/**
* App could not confirm the workable or non-workable. In bootloader
/* App could not confirm the workable or non-workable. In bootloader
* IMG_PENDING_VERIFY state will be changed to IMG_ABORTED. This app will
* not selected to boot at all if this bootloader enable app rollback.
*
@ -117,8 +114,7 @@ enum ota_img_state_e
OTA_IMG_ABORTED = 0x4,
/**
* Undefined. App can boot and work without limits in esp-idf.
/* Undefined. App can boot and work without limits in esp-idf.
*
* This state is not used.
*/

4
arch/risc-v/src/esp32c3/esp32c3_rsa.h
View file

@ -73,9 +73,7 @@ extern "C"
* Public Types
****************************************************************************/
/**
* \brief - The RSA context structure.
*/
/* The RSA context structure. */
struct esp32c3_rsa_context_s
{

3
arch/risc-v/src/esp32c3/esp32c3_rt_timer.c
View file

@ -433,8 +433,7 @@ static int rt_timer_isr(int irq, void *context, void *arg)
if (!list_is_empty(&priv->runlist))
{
/**
* When stop/delete timer, in the same time the hardware timer
/* When stop/delete timer, in the same time the hardware timer
* interrupt triggers, function "stop/delete" remove the timer
* from running list, so the 1st timer is not which triggers.
*/

12
arch/risc-v/src/esp32c3/esp32c3_rt_timer.h
View file

@ -42,9 +42,7 @@
* Public Types
****************************************************************************/
/**
* RT timer state
*/
/* RT timer state */
enum rt_timer_state_e
{
@ -54,9 +52,7 @@ enum rt_timer_state_e
RT_TIMER_DELETE /* Timer is to be delete */
};
/**
* RT timer data structure
*/
/* RT timer data structure */
struct rt_timer_s
{
@ -69,9 +65,7 @@ struct rt_timer_s
struct list_node list; /* Working list */
};
/**
* RT timer creation arguments data structure
*/
/* RT timer creation arguments data structure */
struct rt_timer_args_s
{

5
arch/risc-v/src/esp32c3/esp32c3_wdt.h
View file

@ -73,10 +73,9 @@ enum esp32c3_wdt_stage_e
ESP32C3_WDT_STAGE3 = 3 /* Stage 3 */
};
/**
* Behavior of the WDT stage if it times out.
/* Behavior of the WDT stage if it times out.
*
* @note These enum values should be compatible with the
* Note: These enum values should be compatible with the
* corresponding register field values.
*/

6
arch/risc-v/src/esp32c3/hardware/esp32c3_syscon.h
View file

@ -216,8 +216,7 @@
#define SYSTEM_WIFI_CLK_EN_V 0x00FB9FCF
#define SYSTEM_WIFI_CLK_EN_S 0
/**
* Mask for all Wifi clock bits - 0, 1, 2, 3, 6, 7, 8, 9, 10, 15, 19, 20, 21
/* Mask for all Wifi clock bits - 0, 1, 2, 3, 6, 7, 8, 9, 10, 15, 19, 20, 21
* Bit15 not included here because of the bit now can't be cleared
*/
@ -233,8 +232,7 @@
#define SYSTEM_WIFI_CLK_BT_EN_V 0x0
#define SYSTEM_WIFI_CLK_BT_EN_S 0
/**
* Mask for clock bits used by both WIFI and Bluetooth,
/* Mask for clock bits used by both WIFI and Bluetooth,
* bit 0, 3, 6, 7, 8, 9
*/

3
arch/risc-v/src/esp32c3/hardware/regi2c_saradc.h
View file

@ -25,8 +25,7 @@
* Pre-processor Definitions
****************************************************************************/
/**
* Register definitions for analog to calibrate initial code for getting a
/* Register definitions for analog to calibrate initial code for getting a
* more precise voltage of SAR ADC.
*/

9
arch/risc-v/src/esp32c3/rom/esp32c3_spiflash.h
View file

@ -143,9 +143,7 @@ typedef struct
uint16_t data;
} esp_rom_spiflash_common_cmd_t;
/**
* Global ROM spiflash data, as used by legacy SPI flash functions
*/
/* Global ROM spiflash data, as used by legacy SPI flash functions */
struct spiflash_legacy_data_s
{
@ -154,8 +152,7 @@ struct spiflash_legacy_data_s
uint8_t sig_matrix;
};
/**
* Structure holding SPI flash access critical sections management functions.
/* Structure holding SPI flash access critical sections management functions.
*
* Flash API uses two types of functions for flash access management:
* 1) Functions which prepare/restore flash cache and interrupts before
@ -186,7 +183,7 @@ struct spiflash_legacy_data_s
* use OS primitives or even does not need them (multithreaded access is
* not possible).
*
* @note Structure and corresponding guard functions should not reside
* Note: Structure and corresponding guard functions should not reside
* in flash. For example structure can be placed in DRAM and functions
* in IRAM sections.
*/

8
arch/risc-v/src/hpm6750/hpm6750_clockconfig.h
View file

@ -35,9 +35,7 @@
* Public Types
****************************************************************************/
/**
* @brief Clock nodes
*/
/* Clock nodes */
typedef enum
{
@ -120,9 +118,7 @@ typedef enum
clock_node_end,
} clock_node_t;
/**
* @brief General clock sources
*/
/* General clock sources */
typedef enum
{

24
arch/sparc/include/sparc_v8/irq.h
View file

@ -476,7 +476,7 @@ struct xcptcontext
****************************************************************************/
/* Macro to set the PSR.
* This macro sets the PSR register to the value in @a _psr.
* This macro sets the PSR register to the value in _psr.
*/
#define sparc_set_psr( _psr ) \
do { \
@ -487,7 +487,7 @@ struct xcptcontext
} while ( 0 )
/* Macro to obtain the PSR.
* This macro returns the current contents of the PSR register in @a _psr.
* This macro returns the current contents of the PSR register in _psr.
*/
#define sparc_get_psr( _psr ) \
do { \
@ -503,7 +503,7 @@ struct xcptcontext
} while ( 0 )
/* Macro to obtain the TBR.
* This macro returns the current contents of the TBR register in @a _tbr.
* This macro returns the current contents of the TBR register in _tbr.
*/
#define sparc_get_tbr( _tbr ) \
do { \
@ -512,7 +512,7 @@ struct xcptcontext
} while ( 0 )
/* Macro to set the TBR.
* This macro sets the TBR register to the value in @a _tbr.
* This macro sets the TBR register to the value in _tbr.
*/
#define sparc_set_tbr( _tbr ) \
do { \
@ -520,7 +520,7 @@ struct xcptcontext
} while ( 0 )
/* Macro to obtain the WIM.
* This macro returns the current contents of the WIM field in @a _wim.
* This macro returns the current contents of the WIM field in _wim.
*/
#define sparc_get_wim( _wim ) \
do { \
@ -528,7 +528,7 @@ struct xcptcontext
} while ( 0 )
/* Macro to set the WIM.
* This macro sets the WIM field to the value in @a _wim.
* This macro sets the WIM field to the value in _wim.
*/
#define sparc_set_wim( _wim ) \
do { \
@ -539,7 +539,7 @@ struct xcptcontext
} while ( 0 )
/* Macro to obtain the Y register.
* This macro returns the current contents of the Y register in @a _y.
* This macro returns the current contents of the Y register in _y.
*/
#define sparc_get_y( _y ) \
do { \
@ -547,7 +547,7 @@ struct xcptcontext
} while ( 0 )
/* Macro to set the Y register.
* This macro sets the Y register to the value in @a _y.
* This macro sets the Y register to the value in _y.
*/
#define sparc_set_y( _y ) \
do { \
@ -565,7 +565,7 @@ struct xcptcontext
/* SPARC disable processor interrupts.
* This method is invoked to disable all maskable interrupts.
* @return This method returns the entire PSR contents.
* This method returns the entire PSR contents.
*/
static inline uint32_t sparc_disable_interrupts(void)
@ -577,7 +577,7 @@ static inline uint32_t sparc_disable_interrupts(void)
/* SPARC enable processor interrupts.
* This method is invoked to enable all maskable interrupts.
* @param[in] psr is the PSR returned by @ref sparc_disable_interrupts.
* psr is the PSR returned by sparc_disable_interrupts.
*/
static inline void sparc_enable_interrupts(uint32_t psr)
@ -595,7 +595,7 @@ static inline void sparc_enable_interrupts(uint32_t psr)
/* SPARC flash processor interrupts.
* This method is invoked to temporarily enable all maskable interrupts.
* @param[in] _psr is the PSR returned by @ref sparc_disable_interrupts.
* _psr is the PSR returned by sparc_disable_interrupts.
*/
#define sparc_flash_interrupts( _psr ) \
@ -606,7 +606,7 @@ static inline void sparc_enable_interrupts(uint32_t psr)
/* SPARC obtain interrupt level.
* This method is invoked to obtain the current interrupt disable level.
* @param[in] _level is the PSR returned by @ref sparc_disable_interrupts.
* _level is the PSR returned by sparc_disable_interrupts.
*/
#define sparc_get_interrupt_level( _level ) \

3
arch/xtensa/src/esp32/esp32_ble_adapter.c
View file

@ -1565,8 +1565,7 @@ static IRAM_ATTR int32_t esp_queue_send_generic(void *queue, void *item,
if (ticks == OSI_FUNCS_TIME_BLOCKING || ticks == 0)
{
/**
* BLE interrupt function will call this adapter function to send
/* BLE interrupt function will call this adapter function to send
* message to message queue, so here we should call kernel API
* instead of application API
*/

12
arch/xtensa/src/esp32/esp32_emac.c
View file

@ -606,8 +606,7 @@ static int emac_config(void)
return -ETIMEDOUT;
}
/**
* Enable transmission options:
/* Enable transmission options:
*
* - 100M
* - Full duplex
@ -620,8 +619,7 @@ static int emac_config(void)
emac_set_reg(EMAC_FFR_OFFSET, EMAC_PMF_E);
/**
* Enable flow control options:
/* Enable flow control options:
*
* - PT-28 Time slot
* - RX flow control
@ -634,8 +632,7 @@ static int emac_config(void)
(EMAC_PAUSE_TIME << EMAC_CFPT_S);
emac_set_reg(EMAC_FCR_OFFSET, regval);
/**
* Enable DMA options:
/* Enable DMA options:
*
* - Drop error frame
* - Send frame when filled into FiFO
@ -645,8 +642,7 @@ static int emac_config(void)
regval = EMAC_FSF_E | EMAC_FTF_E | EMAC_OSF_E;
emac_set_reg(EMAC_DMA_OMR_OFFSET, regval);
/**
* Enable DMA bus options:
/* Enable DMA bus options:
*
* - Mixed burst mode
* - Address align beast

22
arch/xtensa/src/esp32/esp32_partition.c
View file

@ -102,17 +102,15 @@ enum ota_img_ctrl
enum ota_img_state
{
/**
* Monitor the first boot. In bootloader of esp-idf this state is changed
* to ESP_OTA_IMG_PENDING_VERIFY if this bootloader enable app rollback.
/* Monitor the first boot. In bootloader of esp-idf this state is changed
* to ESP_OTA_IMG_PENDING_VERIFY if this bootloader enable app rollback.
*
* So this driver doesn't use this state currently.
* So this driver doesn't use this state currently.
*/
OTA_IMG_NEW = 0x0,
/**
* First boot for this app was. If while the second boot this state is then
/* First boot for this app was. If while the second boot this state is then
* it will be changed to ABORTED if this bootloader enable app rollback.
*
* So this driver doesn't use this state currently.
@ -128,8 +126,7 @@ enum ota_img_state
OTA_IMG_INVALID = 0x3,
/**
* App could not confirm the workable or non-workable. In bootloader
/* App could not confirm the workable or non-workable. In bootloader
* IMG_PENDING_VERIFY state will be changed to IMG_ABORTED. This app will
* not selected to boot at all if this bootloader enable app rollback.
*
@ -138,8 +135,7 @@ enum ota_img_state
OTA_IMG_ABORTED = 0x4,
/**
* Undefined. App can boot and work without limits in esp-idf.
/* Undefined. App can boot and work without limits in esp-idf.
*
* This state is not used.
*/
@ -674,8 +670,7 @@ static int partition_create_dev(const struct partition_info_priv *info,
snprintf(path, PARTITION_MOUNTPTR_LEN_MAX, "%s/%s",
g_path_base, info->label);
/**
* If SPI Flash encryption is enable, "APP", "OTA data" and "NVS keys" are
/* If SPI Flash encryption is enable, "APP", "OTA data" and "NVS keys" are
* force to set as encryption partition.
*/
@ -877,8 +872,7 @@ int esp32_partition_init(void)
return -ENOMEM;
}
/**
* Even without SPI Flash encryption, we can also use encrypted
/* Even without SPI Flash encryption, we can also use encrypted
* MTD to read no-encrypted data.
*/

3
arch/xtensa/src/esp32/esp32_rt_timer.c
View file

@ -411,8 +411,7 @@ static int rt_timer_isr(int irq, void *context, void *arg)
if (!list_is_empty(&priv->runlist))
{
/**
* When stop/delete timer, in the same time the hardware timer
/* When stop/delete timer, in the same time the hardware timer
* interrupt triggers, function "stop/delete" remove the timer
* from running list, so the 1st timer is not which triggers.
*/

12
arch/xtensa/src/esp32/esp32_rt_timer.h
View file

@ -42,9 +42,7 @@
* Public Types
****************************************************************************/
/**
* RT timer state
*/
/* RT timer state */
enum rt_timer_state_e
{
@ -54,9 +52,7 @@ enum rt_timer_state_e
RT_TIMER_DELETE /* Timer is to be delete */
};
/**
* RT timer data structure
*/
/* RT timer data structure */
struct rt_timer_s
{
@ -69,9 +65,7 @@ struct rt_timer_s
struct list_node list; /* Working list */
};
/**
* RT timer creation arguments data structure
*/
/* RT timer creation arguments data structure */
struct rt_timer_args_s
{

3
arch/xtensa/src/esp32/esp32_serial.c
View file

@ -643,8 +643,7 @@ static void esp32_dmasend(struct uart_dev_s *dev)
uint8_t *alloctp = NULL;
#endif
/**
* If the buffer comes from PSRAM, allocate a new one from
/* If the buffer comes from PSRAM, allocate a new one from
* Internal SRAM.
*/

3
arch/xtensa/src/esp32/esp32_wlan.c
View file

@ -887,8 +887,7 @@ static void wlan_rxpoll(void *arg)
}
#ifdef WLAN_RX_THRESHOLD
/**
* If received total bytes is larger than receive threshold,
/* If received total bytes is larger than receive threshold,
* then do "unlock" to try to active applicantion to receive
* data from low-level buffer of IP stack.
*/

3
arch/xtensa/src/esp32/hardware/esp32_pinmap.h
View file

@ -29,8 +29,7 @@
* Pre-processor Definitions
****************************************************************************/
/**
* Peripheral' fixed mapped pins by IOMUX, these GPIO pins can have better
/* Peripheral' fixed mapped pins by IOMUX, these GPIO pins can have better
* speed performance.
*/

3
arch/xtensa/src/esp32/rom/esp32_libc_stubs.h
View file

@ -44,8 +44,7 @@
struct _reent;
/**
* @brief ESP32 ROM code contains implementations of some of C
/* ESP32 ROM code contains implementations of some of C
* library functions.
* Whenever a function in ROM needs to use a syscall, it calls a
* pointer to the corresponding syscall implementation defined in

3
arch/xtensa/src/esp32s2/esp32s2_rt_timer.c
View file

@ -444,8 +444,7 @@ static int rt_timer_isr(int irq, void *context, void *arg)
if (!list_is_empty(&priv->runlist))
{
/**
* When stop/delete timer, in the same time the hardware timer
/* When stop/delete timer, in the same time the hardware timer
* interrupt triggers, function "stop/delete" remove the timer
* from running list, so the 1st timer is not which triggers.
*/

12
arch/xtensa/src/esp32s2/esp32s2_rt_timer.h
View file

@ -42,9 +42,7 @@
* Public Types
****************************************************************************/
/**
* RT timer state
*/
/* RT timer state */
enum rt_timer_state_e
{
@ -54,9 +52,7 @@ enum rt_timer_state_e
RT_TIMER_DELETE /* Timer is to be delete */
};
/**
* RT timer data structure
*/
/* RT timer data structure */
struct rt_timer_s
{
@ -69,9 +65,7 @@ struct rt_timer_s
struct list_node list; /* Working list */
};
/**
* RT timer creation arguments data structure
*/
/* RT timer creation arguments data structure */
struct rt_timer_args_s
{

7
arch/xtensa/src/esp32s2/esp32s2_spiram.c
View file

@ -360,11 +360,10 @@ void IRAM_ATTR esp_spiram_writeback_cache(void)
cache_writeback_all();
}
/**
* @brief If SPI RAM(PSRAM) has been initialized
/* If SPI RAM(PSRAM) has been initialized
*
* @return true SPI RAM has been initialized successfully
* @return false SPI RAM hasn't been initialized or initialized failed
* Return true SPI RAM has been initialized successfully
* Return false SPI RAM hasn't been initialized or initialized failed
*/
bool esp_spiram_is_initialized(void)

84
arch/xtensa/src/esp32s2/esp32s2_spiram.h
View file

@ -34,57 +34,51 @@ extern "C"
{
#endif
/* @brief Initialize spiram interface/hardware. Normally called from
/* Initialize spiram interface/hardware. Normally called from
* cpu_start.c.
*
* @return ESP_OK on success
* Return ESP_OK on success
*/
int esp_spiram_init(void);
/**
* @brief Configure Cache/MMU for access to external SPI RAM.
/* Configure Cache/MMU for access to external SPI RAM.
*
* Normally this function is called from cpu_start, if
* CONFIG_SPIRAM_BOOT_INIT option is enabled. Applications which need to
* enable SPI RAM at run time can disable CONFIG_SPIRAM_BOOT_INIT, and
* call this function later.
*
* @attention this function must be called with flash cache disabled.
* Attention: this function must be called with flash cache disabled.
*/
void esp_spiram_init_cache(void);
/**
* @brief Memory test for SPI RAM. Should be called after SPI RAM is
/* Memory test for SPI RAM. Should be called after SPI RAM is
* initialized and (in case of a dual-core system) the app CPU is online.
* This test overwrites the memory with crap, so do not call after e.g. the
* heap allocator has stored important stuff in SPI RAM.
*
* @return true on success, false on failed memory test
* Return true on success, false on failed memory test
*/
bool esp_spiram_test(void);
/**
* @brief Add the initialized SPI RAM to the heap allocator.
*/
/* Add the initialized SPI RAM to the heap allocator. */
int esp_spiram_add_to_heapalloc(void);
/**
* @brief Get the available physical size of the attached SPI RAM chip
/* Get the available physical size of the attached SPI RAM chip
*
* @note If ECC is enabled, the available physical size would be smaller
* Note If ECC is enabled, the available physical size would be smaller
* than the physical size. See `CONFIG_SPIRAM_ECC_ENABLE`
*
* @return Size in bytes, or 0 if no external RAM chip support compiled in.
* Return size in bytes, or 0 if no external RAM chip support compiled in.
*/
size_t esp_spiram_get_size(void);
/**
* @brief Force a writeback of the data in the SPI RAM cache. This is to be
/* Force a writeback of the data in the SPI RAM cache. This is to be
* called whenever cache is disabled, because disabling cache on the ESP32
* discards the data in the SPI RAM cache.
*
@ -93,46 +87,42 @@ size_t esp_spiram_get_size(void);
void esp_spiram_writeback_cache(void);
/**
* @brief If SPI RAM(PSRAM) has been initialized
/* If SPI RAM(PSRAM) has been initialized
*
* @return
* Return
* - true SPI RAM has been initialized successfully
* - false SPI RAM hasn't been initialized or initialized failed
*/
bool esp_spiram_is_initialized(void);
/**
* @brief get psram CS IO
/* get psram CS IO
*
* This interface should be called after PSRAM is enabled, otherwise it will
* return an invalid value -1/0xff.
*
* @return psram CS IO or -1/0xff if psram not enabled
* Return psram CS IO or -1/0xff if psram not enabled
*/
uint8_t esp_spiram_get_cs_io(void);
/**
* @brief Reserve a pool of internal memory for specific DMA/internal
/* Reserve a pool of internal memory for specific DMA/internal
* allocations
*
* @param size Size of reserved pool in bytes
* size Size of reserved pool in bytes
*
* @return
* Return
* - ESP_OK on success
* - ESP_ERR_NO_MEM when no memory available for pool
*/
int esp_spiram_reserve_dma_pool(size_t size);
/**
* @brief If SPI RAM(PSRAM) has been initialized
/* If SPI RAM(PSRAM) has been initialized
*
* @return
* - true SPI RAM has been initialized successfully
* - false SPI RAM hasn't been initialized or initialized failed
* Return
* - true SPI RAM has been initialized successfully
* - false SPI RAM hasn't been initialized or initialized failed
*/
bool esp_spiram_is_initialized(void);
@ -142,26 +132,23 @@ bool esp_spiram_is_initialized(void);
extern int _instruction_reserved_start;
extern int _instruction_reserved_end;
/**
* @brief Get the start page number of the instruction in SPI flash
/* Get the start page number of the instruction in SPI flash
*
* @return start page number
* Return start page number
*/
uint32_t instruction_flash_start_page_get(void);
/**
* @brief Get the end page number of the instruction in SPI flash
/* Get the end page number of the instruction in SPI flash
*
* @return end page number
* Return end page number
*/
uint32_t instruction_flash_end_page_get(void);
/**
* @brief Get the offset of instruction from SPI flash to SPI RAM
/* Get the offset of instruction from SPI flash to SPI RAM
*
* @return instruction offset
* Return instruction offset
*/
int instruction_flash2spiram_offset(void);
@ -173,26 +160,23 @@ int instruction_flash2spiram_offset(void);
extern uint8_t _rodata_reserved_start[];
extern uint8_t _rodata_reserved_end[];
/**
* @brief Get the start page number of the rodata in SPI flash
/* Get the start page number of the rodata in SPI flash
*
* @return start page number
* Return start page number
*/
uint32_t rodata_flash_start_page_get(void);
/**
* @brief Get the end page number of the rodata in SPI flash
/* Get the end page number of the rodata in SPI flash
*
* @return end page number
* Return end page number
*/
uint32_t rodata_flash_end_page_get(void);
/**
* @brief Get the offset number of rodata from SPI flash to SPI RAM
/* Get the offset number of rodata from SPI flash to SPI RAM
*
* @return rodata offset
* Return rodata offset
*/
int rodata_flash2spiram_offset(void);

5
arch/xtensa/src/esp32s2/esp32s2_wdt.h
View file

@ -74,10 +74,9 @@ enum esp32s2_wdt_stage_e
ESP32S2_WDT_STAGE3 = 3 /* Stage 3 */
};
/**
* Behavior of the WDT stage if it times out.
/* Behavior of the WDT stage if it times out.
*
* @note These enum values should be compatible with the
* Note: These enum values should be compatible with the
* corresponding register field values.
*/

3
arch/xtensa/src/esp32s2/hardware/esp32s2_i2cbbpll.h
View file

@ -21,8 +21,7 @@
#ifndef __ARCH_XTENSA_SRC_ESP32S2_HARDWARE_ESP32S2_I2CBBPLL_H
#define __ARCH_XTENSA_SRC_ESP32S2_HARDWARE_ESP32S2_I2CBBPLL_H
/**
* Register definitions for digital PLL (BBPLL)
/* Register definitions for digital PLL (BBPLL)
*
* This file lists register fields of BBPLL, located on an internal
* configuration bus. These definitions are used via macros defined in

3
arch/xtensa/src/esp32s2/hardware/esp32s2_pinmap.h
View file

@ -29,8 +29,7 @@
* Pre-processor Definitions
****************************************************************************/
/**
* Peripheral' fixed mapped pins by IOMUX, these GPIO pins can have better
/* Peripheral' fixed mapped pins by IOMUX, these GPIO pins can have better
* speed performance.
*/

5
arch/xtensa/src/esp32s2/hardware/regi2c_bbpll.h
View file

@ -21,9 +21,8 @@
#ifndef __ARCH_XTENSA_SRC_ESP32S2_HARDWARE_REGI2C_BBPLL_H
#define __ARCH_XTENSA_SRC_ESP32S2_HARDWARE_REGI2C_BBPLL_H
/**
* @file regi2c_bbpll.h
* @brief Register definitions for digital PLL (BBPLL)
/* regi2c_bbpll.h
* Register definitions for digital PLL (BBPLL)
*
* This file lists register fields of BBPLL, located on an internal
* configuration bus. These definitions are used via macros defined

3
arch/xtensa/src/esp32s2/rom/esp32s2_libc_stubs.h
View file

@ -44,8 +44,7 @@
struct _reent;
/**
* @brief ESP32-S2 ROM code contains implementations of some of C
/* ESP32-S2 ROM code contains implementations of some of C
* library functions.
* Whenever a function in ROM needs to use a syscall, it calls a
* pointer to the corresponding syscall implementation defined in

202
arch/xtensa/src/esp32s2/rom/esp32s2_opi_flash.h
View file

@ -138,53 +138,46 @@ typedef struct
/* spi user mode command config */
/**
* @brief Config the spi user command
* @param spi_num spi port
* @param pcmd pointer to accept the spi command struct
/* Config the spi user command
* spi_num spi port
* pcmd pointer to accept the spi command struct
*/
void esp_rom_spi_cmd_config(int spi_num, esp_rom_spi_cmd_t *pcmd);
/**
* @brief Start a spi user command sequence
* @param spi_num spi port
* @param rx_buf buffer pointer to receive data
* @param rx_len receive data length in byte
* @param cs_en_mask decide which cs to use, 0 for cs0, 1 for cs1
* @param is_write_erase to indicate whether this is a write or erase
/* Start a spi user command sequence
* spi_num spi port
* rx_buf buffer pointer to receive data
* rx_len receive data length in byte
* cs_en_mask decide which cs to use, 0 for cs0, 1 for cs1
* is_write_erase to indicate whether this is a write or erase
* operation, since the CPU would check permission
*/
void esp_rom_spi_cmd_start(int spi_num, uint8_t *rx_buf, uint16_t rx_len,
uint8_t cs_en_mask, bool is_write_erase);
/**
* @brief Config opi flash pads according to efuse settings.
*/
/* Config opi flash pads according to efuse settings. */
void esp_rom_opiflash_pin_config(void);
/**
* @brief Set SPI operation mode
* @param spi_num spi port
* @param mode Flash Read Mode
/* Set SPI operation mode
* spi_num spi port
* mode Flash Read Mode
*/
void esp_rom_spi_set_op_mode(int spi_num, esp_rom_spiflash_read_mode_t mode);
/**
* @brief Set data swap mode in DTR(DDR) mode
* @param spi_num spi port
* @param wr_swap to decide whether to swap fifo data in dtr write operation
* @param rd_swap to decide whether to swap fifo data in dtr read operation
/* Set data swap mode in DTR(DDR) mode
* spi_num spi port
* wr_swap to decide whether to swap fifo data in dtr write operation
* rd_swap to decide whether to swap fifo data in dtr read operation
*/
void esp_rom_spi_set_dtr_swap_mode(int spi, bool wr_swap, bool rd_swap);
/**
* @brief to send reset command in spi/opi-str/opi-dtr mode(for MX25UM25645G)
* @param spi_num spi port
/* To send reset command in spi/opi-str/opi-dtr mode(for MX25UM25645G)
* spi_num spi port
*/
void esp_rom_opiflash_mode_reset(int spi_num);
@ -193,21 +186,20 @@ void esp_rom_opiflash_mode_reset(int spi_num);
/* MX25UM25645G opi flash interface */
/**
* @brief To execute a flash operation command
* @param spi_num spi port
* @param mode Flash Read Mode
* @param cmd data to send in command field
* @param cmd_bit_len bit length of command field
* @param addr data to send in address field
* @param addr_bit_len bit length of address field
* @param dummy_bits bit length of dummy field
* @param mosi_data data buffer to be sent in mosi field
* @param mosi_bit_len bit length of data buffer to be sent in mosi field
* @param miso_data data buffer to accept data in miso field
* @param miso_bit_len bit length of data buffer to accept data in miso field
* @param cs_mark decide which cs pin to use. 0: cs0, 1: cs1
* @param is_write_erase_operation to indicate whether this a write or erase
/* To execute a flash operation command
* spi_num spi port
* mode Flash Read Mode
* cmd data to send in command field
* cmd_bit_len bit length of command field
* addr data to send in address field
* addr_bit_len bit length of address field
* dummy_bits bit length of dummy field
* mosi_data data buffer to be sent in mosi field
* mosi_bit_len bit length of data buffer to be sent in mosi field
* miso_data data buffer to accept data in miso field
* miso_bit_len bit length of data buffer to accept data in miso field
* cs_mark decide which cs pin to use. 0: cs0, 1: cs1
* is_write_erase_operation to indicate whether this a write or erase
* flash operation
*/
@ -220,98 +212,89 @@ void esp_rom_opiflash_exec_cmd(int spi_num, esp_rom_spiflash_read_mode_t mode,
uint32_t cs_mask,
bool is_write_erase_operation);
/**
* @brief send reset command to opi flash
* @param spi_num spi port
* @param mode Flash Operation Mode
/* end reset command to opi flash
* spi_num spi port
* mode Flash Operation Mode
*/
void esp_rom_opiflash_soft_reset(int spi_num,
esp_rom_spiflash_read_mode_t mode);
/**
* @brief to read opi flash ID
* @note command format would be defined in initialization
* @param[out] out_id buffer to accept id
* @return flash operation result
/* To read opi flash ID
* Note command format would be defined in initialization
* out_id buffer to accept id
* Return flash operation result
*/
uint32_t esp_rom_opiflash_read_id(int spi_num,
esp_rom_spiflash_read_mode_t mode);
/**
* @brief to read opi flash status register(for MX25UM25645G)
* @param spi_num spi port
* @param mode Flash Operation Mode
* @return opi flash status value
/* To read opi flash status register(for MX25UM25645G)
* spi_num spi port
* mode Flash Operation Mode
* Return opi flash status value
*/
uint8_t esp_rom_opiflash_rdsr(int spi_num, esp_rom_spiflash_read_mode_t mode);
/**
* @brief wait opi flash status register to be idle
* @param spi_num spi port
* @param mode Flash Operation Mode
/* Wait opi flash status register to be idle
* spi_num spi port
* mode Flash Operation Mode
*/
void esp_rom_opiflash_wait_idle(int spi_num,
esp_rom_spiflash_read_mode_t mode);
/**
* @brief to read the config register2(for MX25UM25645G)
* @param spi_num spi port
* @param mode Flash Operation Mode
* @param addr the address of configure register
* @return value of config register2
/* To read the config register2(for MX25UM25645G)
* spi_num spi port
* mode Flash Operation Mode
* addr the address of configure register
* Return value of config register2
*/
uint8_t esp_rom_opiflash_rdcr2(int spi_num,
esp_rom_spiflash_read_mode_t mode,
uint32_t addr);
/**
* @brief to write the config register2(for MX25UM25645G)
* @param spi_num spi port
* @param mode Flash Operation Mode
* @param addr the address of config register
* @param val the value to write
/* To write the config register2(for MX25UM25645G)
* spi_num spi port
* mode Flash Operation Mode
* addr the address of config register
* val the value to write
*/
void esp_rom_opiflash_wrcr2(int spi_num, esp_rom_spiflash_read_mode_t mode,
uint32_t addr, uint8_t val);
/**
* @brief to erase flash sector(for MX25UM25645G)
* @param spi_num spi port
* @param address the sector address to be erased
* @param mode Flash operation mode
* @return flash operation result
/* To erase flash sector(for MX25UM25645G)
* spi_num spi port
* address the sector address to be erased
* mode Flash operation mode
* Return flash operation result
*/
esp_rom_spiflash_result_t
esp_rom_opiflash_erase_sector(int spi_num, uint32_t address,
esp_rom_spiflash_read_mode_t mode);
/**
* @brief to erase flash block(for MX25UM25645G)
* @param spi_num spi port
* @param address the block address to be erased
* @param mode Flash operation mode
* @return flash operation result
/* To erase flash block(for MX25UM25645G)
* spi_num spi port
* address the block address to be erased
* mode Flash operation mode
* Return flash operation result
*/
esp_rom_spiflash_result_t
esp_rom_opiflash_erase_block_64k(int spi_num, uint32_t address,
esp_rom_spiflash_read_mode_t mode);
/**
* @brief to erase a flash area define by start address and length
/* To erase a flash area define by start address and length
* (for MX25UM25645G)
* @param spi_num spi port
* @param start_addr the start address to be erased
* @param area_len the erea length to be erased
* @param mode flash operation mode
* @return flash operation result
* spi_num spi port
* start_addr the start address to be erased
* area_len the erea length to be erased
* mode flash operation mode
* Return flash operation result
*/
esp_rom_spiflash_result_t
@ -319,28 +302,26 @@ esp_rom_opiflash_erase_area(int spi_num, uint32_t start_addr,
uint32_t area_len,
esp_rom_spiflash_read_mode_t mode);
/**
* @brief to read data from opi flash(for MX25UM25645G)
* @param spi_num spi port
* @param mode flash operation mode
* @param flash_addr flash address to read data from
* @param data_addr data buffer to accept the data
* @param len data length to be read
* @return flash operation result
/* T read data from opi flash(for MX25UM25645G)
* spi_num spi port
* mode flash operation mode
* flash_addr flash address to read data from
* data_addr data buffer to accept the data
* len data length to be read
* Return flash operation result
*/
esp_rom_spiflash_result_t
esp_rom_opiflash_read(int spi_num, esp_rom_spiflash_read_mode_t mode,
uint32_t flash_addr, uint8_t *data_addr, int len);
/**
* @brief to write data to opi flash(for MX25UM25645G)
* @param spi_num spi port
* @param mode flash operation mode
* @param flash_addr flash address to write data to
* @param data_addr data buffer to write to flash
* @param len data length to write
* @return flash operation result
/* To write data to opi flash(for MX25UM25645G)
* spi_num spi port
* mode flash operation mode
* flash_addr flash address to write data to
* data_addr data buffer to write to flash
* len data length to write
* Return flash operation result
*/
esp_rom_spiflash_result_t
@ -348,11 +329,10 @@ esp_rom_opiflash_write(int spi_num, esp_rom_spiflash_read_mode_t mode,
uint32_t flash_addr, uint8_t *data_addr,
uint32_t len);
/**
* @brief to set opi flash operation mode(for MX25UM25645G)
* @param spi_num spi port
* @param cur_mode current operation mode
* @param target the target operation mode to be set
/* To set opi flash operation mode(for MX25UM25645G)
* spi_num spi port
* cur_mode current operation mode
* target the target operation mode to be set
*/
void esp_rom_opiflash_set_mode(int spi_num,

5
arch/xtensa/src/esp32s2/rom/esp32s2_spiflash.h
View file

@ -143,8 +143,7 @@ typedef struct
uint16_t data;
} esp_rom_spiflash_common_cmd_t;
/**
* Structure holding SPI flash access critical sections management functions.
/* Structure holding SPI flash access critical sections management functions.
*
* Flash API uses two types of functions for flash access management:
* 1) Functions which prepare/restore flash cache and interrupts before
@ -175,7 +174,7 @@ typedef struct
* use OS primitives or even does not need them (multithreaded access is
* not possible).
*
* @note Structure and corresponding guard functions should not reside
* Note: Structure and corresponding guard functions should not reside
* in flash. For example structure can be placed in DRAM and functions
* in IRAM sections.
*/

3
arch/xtensa/src/esp32s3/esp32s3_ble_adapter.c
View file

@ -1245,8 +1245,7 @@ static IRAM_ATTR int32_t esp_queue_send_generic(void *queue, void *item,
if (ticks == OSI_FUNCS_TIME_BLOCKING || ticks == 0)
{
/**
* BLE interrupt function will call this adapter function to send
/* BLE interrupt function will call this adapter function to send
* message to message queue, so here we should call kernel API
* instead of application API
*/

6
arch/xtensa/src/esp32s3/esp32s3_lcd.c
View file

@ -773,8 +773,7 @@ static void esp32s3_lcd_config(void)
regval |= LCD_CAM_LCD_VSYNC_INT_ENA_M;
esp32s3_lcd_putreg(LCD_CAM_LC_DMA_INT_ENA_REG, regval);
/**
* Set LCD screem parameters:
/* Set LCD screem parameters:
* 1. RGB mode, ouput VSYNC/HSYNC/DE signal
* 2. VT height
* 3. VA height
@ -805,8 +804,7 @@ static void esp32s3_lcd_config(void)
LCD_CAM_LCD_VSYNC_IDLE_POL_M;
esp32s3_lcd_putreg(LCD_CAM_LCD_CTRL2_REG, regval);
/**
* Configure output mode:
/* Configure output mode:
* 1. always output
* 2. 16-bit word
* 3. LCD mode

3
arch/xtensa/src/esp32s3/esp32s3_otg_device.c
View file

@ -5594,8 +5594,7 @@ void xtensa_usbinitialize(void)
esp32s3_configgpio(USB_IOMUX_DM, DRIVE_3);
esp32s3_configgpio(USB_IOMUX_DP, DRIVE_3);
/**
* USB_OTG_IDDIG_IN_IDX: connected connector is mini-B side
/* USB_OTG_IDDIG_IN_IDX: connected connector is mini-B side
* USB_SRP_BVALID_IN_IDX: HIGH to force USB device mode
* USB_OTG_VBUSVALID_IN_IDX: receiving a valid Vbus from device
* USB_OTG_AVALID_IN_IDX: HIGH to force USB host mode

16
arch/xtensa/src/esp32s3/esp32s3_partition.c
View file

@ -86,17 +86,15 @@ enum ota_img_ctrl_e
enum ota_img_state_e
{
/**
* Monitor the first boot. In bootloader of esp-idf this state is changed
* to ESP_OTA_IMG_PENDING_VERIFY if this bootloader enable app rollback.
/* Monitor the first boot. In bootloader of esp-idf this state is changed
* to ESP_OTA_IMG_PENDING_VERIFY if this bootloader enable app rollback.
*
* So this driver doesn't use this state currently.
* So this driver doesn't use this state currently.
*/
OTA_IMG_NEW = 0x0,
/**
* First boot for this app was. If while the second boot this state is then
/* First boot for this app was. If while the second boot this state is then
* it will be changed to ABORTED if this bootloader enable app rollback.
*
* So this driver doesn't use this state currently.
@ -112,8 +110,7 @@ enum ota_img_state_e
OTA_IMG_INVALID = 0x3,
/**
* App could not confirm the workable or non-workable. In bootloader
/* App could not confirm the workable or non-workable. In bootloader
* IMG_PENDING_VERIFY state will be changed to IMG_ABORTED. This app will
* not selected to boot at all if this bootloader enable app rollback.
*
@ -122,8 +119,7 @@ enum ota_img_state_e
OTA_IMG_ABORTED = 0x4,
/**
* Undefined. App can boot and work without limits in esp-idf.
/* Undefined. App can boot and work without limits in esp-idf.
*
* This state is not used.
*/

5
arch/xtensa/src/esp32s3/esp32s3_reset_reasons.h
View file

@ -59,9 +59,8 @@ extern "C"
*+-------------------------------------------------------------------------+
*/
/**
* @brief Naming conventions: RESET_REASON_{reset level}_{reset reason}
* @note refer to TRM: <Reset and Clock> chapter
/* Naming conventions: RESET_REASON_{reset level}_{reset reason}
* Note refer to TRM: <Reset and Clock> chapter
*/
typedef enum

12
arch/xtensa/src/esp32s3/esp32s3_rt_timer.h
View file

@ -43,9 +43,7 @@
* Public Types
****************************************************************************/
/**
* RT timer state
*/
/* RT timer state */
enum rt_timer_state_e
{
@ -55,9 +53,7 @@ enum rt_timer_state_e
RT_TIMER_DELETE /* Timer is to be delete */
};
/**
* RT timer data structure
*/
/* RT timer data structure */
struct rt_timer_s
{
@ -70,9 +66,7 @@ struct rt_timer_s
struct list_node list; /* Working list */
};
/**
* RT timer creation arguments data structure
*/
/* RT timer creation arguments data structure */
struct rt_timer_args_s
{

3
arch/xtensa/src/esp32s3/esp32s3_spi_timing.c
View file

@ -1440,8 +1440,7 @@ void IRAM_ATTR esp32s3_spi_timing_set_mspi_high_speed(bool spi1)
void IRAM_ATTR esp32s3_spi_timing_set_mspi_low_speed(bool spi1)
{
/**
* Here we are going to set the SPI1 frequency to be 20MHz,
/* Here we are going to set the SPI1 frequency to be 20MHz,
* so we need to set SPI1 din_num and din_mode regs.
*
* Because SPI0 and SPI1 share the din_num and din_mode regs,

17
arch/xtensa/src/esp32s3/esp32s3_spiram.c
View file

@ -451,11 +451,10 @@ void IRAM_ATTR esp_spiram_writeback_cache(void)
cache_writeback_all();
}
/**
* @brief If SPI RAM(PSRAM) has been initialized
/* If SPI RAM(PSRAM) has been initialized
*
* @return true SPI RAM has been initialized successfully
* @return false SPI RAM hasn't been initialized or initialized failed
* Return true SPI RAM has been initialized successfully
* Return false SPI RAM hasn't been initialized or initialized failed
*/
bool esp_spiram_is_initialized(void)
@ -468,10 +467,9 @@ uint8_t esp_spiram_get_cs_io(void)
return psram_get_cs_io();
}
/**
* @brief Get allocable virtual start address
/* Get allocable virtual start address
*
* @return Allocable virtual start address
* Return Allocable virtual start address
*/
uint32_t esp_spiram_allocable_vaddr_start(void)
@ -479,10 +477,9 @@ uint32_t esp_spiram_allocable_vaddr_start(void)
return g_allocable_vaddr_start;
}
/**
* @brief Get allocable virtual end address
/* Get allocable virtual end address
*
* @return Allocable virtual end address
* Return Allocable virtual end address
*/
uint32_t esp_spiram_allocable_vaddr_end(void)

90
arch/xtensa/src/esp32s3/esp32s3_spiram.h
View file

@ -34,57 +34,51 @@ extern "C"
{
#endif
/* @brief Initialize spiram interface/hardware. Normally called from
/* Initialize spiram interface/hardware. Normally called from
* cpu_start.c.
*
* @return ESP_OK on success
* Return ESP_OK on success
*/
int esp_spiram_init(void);
/**
* @brief Configure Cache/MMU for access to external SPI RAM.
/* Configure Cache/MMU for access to external SPI RAM.
*
* Normally this function is called from cpu_start, if
* CONFIG_SPIRAM_BOOT_INIT option is enabled. Applications which need to
* enable SPI RAM at run time can disable CONFIG_SPIRAM_BOOT_INIT, and
* call this function later.
*
* @attention this function must be called with flash cache disabled.
* Attention this function must be called with flash cache disabled.
*/
void esp_spiram_init_cache(void);
/**
* @brief Memory test for SPI RAM. Should be called after SPI RAM is
/* Memory test for SPI RAM. Should be called after SPI RAM is
* initialized and (in case of a dual-core system) the app CPU is online.
* This test overwrites the memory with crap, so do not call after e.g. the
* heap allocator has stored important stuff in SPI RAM.
*
* @return true on success, false on failed memory test
* Return true on success, false on failed memory test
*/
bool esp_spiram_test(void);
/**
* @brief Add the initialized SPI RAM to the heap allocator.
*/
/* Add the initialized SPI RAM to the heap allocator. */
int esp_spiram_add_to_heapalloc(void);
/**
* @brief Get the available physical size of the attached SPI RAM chip
/* Get the available physical size of the attached SPI RAM chip
*
* @note If ECC is enabled, the available physical size would be smaller
* Note if ECC is enabled, the available physical size would be smaller
* than the physical size. See `CONFIG_ESP32S3_SPIRAM_ECC_ENABLE`
*
* @return Size in bytes, or 0 if no external RAM chip support compiled in.
* Return Size in bytes, or 0 if no external RAM chip support compiled in.
*/
size_t esp_spiram_get_size(void);
/**
* @brief Force a writeback of the data in the SPI RAM cache. This is to be
/* Force a writeback of the data in the SPI RAM cache. This is to be
* called whenever cache is disabled, because disabling cache on the ESP32
* discards the data in the SPI RAM cache.
*
@ -93,44 +87,40 @@ size_t esp_spiram_get_size(void);
void esp_spiram_writeback_cache(void);
/**
* @brief If SPI RAM(PSRAM) has been initialized
/* If SPI RAM(PSRAM) has been initialized
*
* @return
* Return
* - true SPI RAM has been initialized successfully
* - false SPI RAM hasn't been initialized or initialized failed
*/
bool esp_spiram_is_initialized(void);
/**
* @brief get psram CS IO
/* Get psram CS IO
*
* This interface should be called after PSRAM is enabled, otherwise it will
* return an invalid value -1/0xff.
*
* @return psram CS IO or -1/0xff if psram not enabled
* Return psram CS IO or -1/0xff if psram not enabled
*/
uint8_t esp_spiram_get_cs_io(void);
/**
* @brief Reserve a pool of internal memory for specific DMA/internal
/* Reserve a pool of internal memory for specific DMA/internal
* allocations
*
* @param size Size of reserved pool in bytes
* size Size of reserved pool in bytes
*
* @return
* Return
* - ESP_OK on success
* - ESP_ERR_NO_MEM when no memory available for pool
*/
int esp_spiram_reserve_dma_pool(size_t size);
/**
* @brief If SPI RAM(PSRAM) has been initialized
/* If SPI RAM(PSRAM) has been initialized
*
* @return
* Return
* - true SPI RAM has been initialized successfully
* - false SPI RAM hasn't been initialized or initialized failed
*/
@ -142,26 +132,23 @@ bool esp_spiram_is_initialized(void);
extern uint8_t _instruction_reserved_start[];
extern uint8_t _instruction_reserved_end[];
/**
* @brief Get the start page number of the instruction in SPI flash
/* Get the start page number of the instruction in SPI flash
*
* @return start page number
* Return start page number
*/
uint32_t instruction_flash_start_page_get(void);
/**
* @brief Get the end page number of the instruction in SPI flash
/* Get the end page number of the instruction in SPI flash
*
* @return end page number
* Return end page number
*/
uint32_t instruction_flash_end_page_get(void);
/**
* @brief Get the offset of instruction from SPI flash to SPI RAM
/* Get the offset of instruction from SPI flash to SPI RAM
*
* @return instruction offset
* Return instruction offset
*/
int instruction_flash2spiram_offset(void);
@ -173,44 +160,39 @@ int instruction_flash2spiram_offset(void);
extern uint8_t _rodata_reserved_start[];
extern uint8_t _rodata_reserved_end[];
/**
* @brief Get the start page number of the rodata in SPI flash
/* Get the start page number of the rodata in SPI flash
*
* @return start page number
* Return start page number
*/
uint32_t rodata_flash_start_page_get(void);
/**
* @brief Get the end page number of the rodata in SPI flash
/* Get the end page number of the rodata in SPI flash
*
* @return end page number
* Return end page number
*/
uint32_t rodata_flash_end_page_get(void);
/**
* @brief Get the offset number of rodata from SPI flash to SPI RAM
/* Get the offset number of rodata from SPI flash to SPI RAM
*
* @return rodata offset
* Return rodata offset
*/
int rodata_flash2spiram_offset(void);
#endif
/**
* @brief Get allocable virtual start address
/* Get allocable virtual start address
*
* @return Allocable virtual start address
* Return Allocable virtual start address
*/
uint32_t esp_spiram_allocable_vaddr_start(void);
/**
* @brief Get allocable virtual end address
/* Get allocable virtual end address
*
* @return Allocable virtual end address
* Return Allocable virtual end address
*/
uint32_t esp_spiram_allocable_vaddr_end(void);

5
arch/xtensa/src/esp32s3/esp32s3_wdt.h
View file

@ -95,10 +95,9 @@ enum esp32s3_wdt_stage_e
ESP32S3_WDT_STAGE3 = 3 /* Stage 3 */
};
/**
* Behavior of the WDT stage if it times out.
/* Behavior of the WDT stage if it times out.
*
* @note These enum values should be compatible with the
* Note: These enum values should be compatible with the
* corresponding register field values.
*/

3
arch/xtensa/src/esp32s3/hardware/esp32s3_pinmap.h
View file

@ -29,8 +29,7 @@
* Pre-processor Definitions
****************************************************************************/
/**
* Peripheral' fixed mapped pins by IOMUX, these GPIO pins can have better
/* Peripheral' fixed mapped pins by IOMUX, these GPIO pins can have better
* speed performance.
*/

5
arch/xtensa/src/esp32s3/hardware/regi2c_bbpll.h
View file

@ -21,9 +21,8 @@
#ifndef __ARCH_XTENSA_SRC_ESP32S3_HARDWARE_REGI2C_BBPLL_H
#define __ARCH_XTENSA_SRC_ESP32S3_HARDWARE_REGI2C_BBPLL_H
/**
* @file regi2c_bbpll.h
* @brief Register definitions for digital PLL (BBPLL)
/* regi2c_bbpll.h
* Register definitions for digital PLL (BBPLL)
*
* This file lists register fields of BBPLL, located on an internal
* configuration bus. These definitions are used via macros defined

3
arch/xtensa/src/esp32s3/rom/esp32s3_libc_stubs.h
View file

@ -44,8 +44,7 @@
struct _reent;
/**
* @brief ESP32-S3 ROM code contains implementations of some of C
/* ESP32-S3 ROM code contains implementations of some of C
* library functions.
* Whenever a function in ROM needs to use a syscall, it calls a
* pointer to the corresponding syscall implementation defined in

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