Urgent data preceded "normal" data in the TCP payload. If the urgent data is larger than the size of the TCP payload, this indicates that the entire payload is urgent data and that urgent data continues in the next packet.
This case was handled correctly for the case where urgent data was present but was not being handled correctly in the case where the urgent data was NOT present.
Summary:
- Brennan reported the script does not work with nucleo-h743zi:otg_fs_host
- Actually, the config uses FPU but the script did not detect it
- The script assumed that the nuttx contains fpuconfig symbol
- However, this assumption was incorrect
- This commit fixes this issue by detecting FPU with tcb->xcp.regs
Impact:
- Cortex-M targets
Testing:
- Tested with lm3s6965-ek:discover (Cortex-M3)
- Tested with spresense:wifi_smp (Cortex-M4F)
- Tested with sim:smp (x86_64)
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
This reverts commit 97be116a39.
This commit broke nxffs. This leaves the first block as empty which
then exposes another bug where when the pack is called because we
have reached the end of flash and need to look for deleted inodes
we search the first block find no inode and assume that there
are no more inodes. This then results in corrupting the filesystem
by writing over existing inodes.
This can be seen by runing the sim:nxffs configuration.
Prior to this commit the first pass of writing files would look like
this:
NXFFS Dump:
BLOCK:OFFS TYPE STATE LENGTH
0:5 INODE OK 2680
0:78 DATA OK 424
1:5 DATA OK 497
2:5 DATA OK 497
3:5 DATA OK 497
4:5 DATA OK 497
5:5 DATA OK 268
5:283 INODE OK 7410
5:425 DATA OK 77
6:5 DATA OK 497
With this commit:
NXFFS Dump:
BLOCK:OFFS TYPE STATE LENGTH
0:0 BLOCK ERASED 512
1:5 INODE OK 6394
1:39 DATA OK 463
2:5 DATA OK 497
3:5 DATA OK 497
Signed-off-by: Brennan Ashton <bashton@brennanashton.com>
Summary:
- Apply the same logic added to cxd56_cpupause.c
Impact:
- SMP only
Testing:
- Tested with esp32-core:smp (QEMU)
- Run smp and ostest
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
Summary:
- Apply the same logic added to cxd56_cpupause.c
Impact:
- SMP only
Testing:
- Tested with maix-bit:smp (QEMU)
- Run smp and ostest
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
Summary:
- Apply the same logic added to cxd56_cpupause.c
Impact:
- SMP only
Testing:
- Tested with lc823450-xgevk:rndis
- Run smp and ostest
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
Summary:
- Apply the same logic added to cxd56_cpupause.c
Impact:
- SMP only
Testing:
- Tested with sabre-6quad:smp (QEMU and dev board)
- Run smp and ostest
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
Summary:
- I noticed that sched_add_readytorun() runs on multiple CPUs simultaneously
- Finally, I found the root cause which was described in TODO
- Actually, the task newly scheduled on remote CPU did not acquire g_cpu_irqlock
- This commit fixes this issue by adding a critical section to the pause handler
- Which will acquire g_cpu_irqlock on the remote CPU explicitly
Impact:
- SMP only
Testing:
- Tested with spresense:wifi_smp (NCPUS=2 and 4)
- Run smp, ostest, nxplayer
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
Summary:
- Remove comments on up_idle() which is old information
- Add L2CC info with QEMU
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
Summary:
- I noticed that Cortex-A SGI can be masked
- We thought the SGI is not maskable
- Although I can not remember how I tested it before
- It actually works as expected now
- Also, fixed the number of remaining bugs in TODO
Impact:
- No impact
Testing:
- Tested with sabre-6quad:smp (QEMU and dev board)
- Add the following code in up_idle() before calling asm("WFI");
+ if (0 != up_cpu_index())
+ {
+ up_irq_save();
+ }
- Run the hello app, you can see "Hello, World!!"
- But nsh will freeze soon because arm_pause_handler is not called.
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
Summary:
- Remove unnecessary d-cache operation to make boot fast
Impact:
- armv7-a SMP only
Testing:
- Tested with sabre-6quad:smp (QEMU and dev board)
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
Summary:
- This commit adds L2CC to smp/defconfig
- Also adds CLOCK_MONOTONIC
Impact:
- sabre-6quad:smp only
Testing:
- Tested with both QEMU and dev board
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
Summary:
- This commit adds L2CC to nsh/defconfig
- Also adds EXAMPLES_HELLO, TESTING_GETPRIME and TESTING_OSTEST
Impact:
- sabre-6quad:nsh only
Testing:
- Tested with both QEMU and dev board
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
It seems that part of the patch
stm32l4: correct build of stm32l4_can.c to respect L4 variant
has been lost on its way to mainline.
Signed-off-by: Pavel Pisa <ppisa@pikron.com>
Summary:
- I found a deadlock during Wi-Fi audio streaming test plus stress test
- The testing environment was spresense:wifi_smp (NCPUS=4)
- The deadlock happened because two CPUs called up_cpu_pause() almost simultaneously
- This situation should not happen, because up_cpu_pause() is called in a critical section
- Actually, the latter call was from nxsem_post() in an IRQ handler
- And when enter_critical_section() was called, irq_waitlock() detected a deadlock
- Then it called up_cpu_paused() to break the deadlock
- However, this resulted in setting g_cpu_irqset on the CPU
- Even though another CPU had held a g_cpu_irqlock
- This situation violates the critical section and should be avoided
- To avoid the situation, if a CPU sets g_cpu_irqset after calling up_cpu_paused()
- The CPU must release g_cpu_irqlock first
- Then retry irq_waitlock() to acquire g_cpu_irqlock
Impact:
- Affect SMP
Testing:
- Tested with spresense:wifi_smp (NCPUS=2 and 4)
- Tested with spresense:smp
- Tested with sim:smp
- Tested with sabre-6quad:smp (QEMU)
- Tested with maix-bit:smp (QEMU)
- Tested with esp32-core:smp (QEMU)
- Tested with lc823450-xgevk:rndis
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
Summary:
- This commit fixes kernel stack dump information
Impact:
- Affects armv7-a with kernel build
Testing:
- Built with sama5d4-ek:knsh
- Not tested
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
Summary:
- Apply the same logic for armv7-m
- NOTE: stack pointer alignment is 4-byte
Impact:
- Affects armv6-m with interrupt stack enabled
Testing:
- Built with freedom-kl25z:nsh (CONFIG_ARCH_INTERRUPTSTACK=2048)
- Not tested but should work
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
Summary:
- Apply the same logic for armv7-m
- NOTE: stack pointer alignment is 8-byte
Impact:
- Affects armv8-m with interrupt stack enabled
Testing:
- Not tested but should work
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
Summary:
- Apply the same logic for armv7-a
- NOTE: stack pointer alignment is 8-byte
Impact:
- Affects armv7-r with interrupt stack enabled
Testing:
- Not tested but should work
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
Summary:
- Apply the same logic for armv7-a
- NOTE: stack pointer alignment is 4-byte
Impact:
- Affects arm (arm7/9) and c5471 with interrupt stack enabled
Testing:
- Built with c5471evm.nsh (CONFIG_ARCH_INTERRUPTSTACK=2048)
- Built with ea3131:nsh (CONFIG_ARCH_INTERRUPTSTACK=2048)
- Not tested but should work
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
Summary:
- Remove -4/-8 offset coding in imx_irq.c and arm_vectors.S
- Instead, add SP adjustment after calling setirqstack/setfiqstack
- Fix off-by-one irq/fiq stack allocation in 8-byte aligned arch
- Fix comments on the user stack pointer in arm_vectors.S
- Also, fix up_dumpstate() to extract the user stack pointer
- NOTE: stack pointer alignment is 8-byte
Impact:
- Affects armv7-a with interrupt stack enabled
Testing:
- Tested with sabre-6quad:smp with QEMU
- Tested with sabre-6quad:nsh with QEMU
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
Summary:
- This commit fixes CPUx IDLE stack top for SMP
- Also removes SMP_STACK_TOP from smp.h
Impact:
- Affects armv7-a SMP only
Testing:
- Tested with sabre-6quad:smp (QEMU)
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
Summary:
- Modify arm_intstack_base() to return "top" of the IRQ stack for the current CPU
- This change fixes IRQ stack dump information for ARM SMP
- Add arm_intstack_alloc() to return "bottom" of the IRQ stack for the current CPU
- Also, these functions are now implemented in xxx_irq.c (imx/cxd56/lc823450)
- up_color_intstack() and up_check_intstack() now call arm_intstack_alloc()
- These semantics are now consistent with non-SMP case
- up_color_intstack() now initializes whole IRQ stack region for SMP
- Adjust IRQ stack top address for each CPU (e.g. -8)
- Fix setintstack to handle in case of NCPUS=1 (cxd56, lc823450)
- Adjust INTSTACK_SIZE to 8 bytes alignment (cxd56, lc823450)
- Refactor setintstack for lc823450
- Remove old IRQ stack coloring code from up_irqinitialize() (lc823450)
- Introduce g_cpu_intstack_top for lc823450
- Refactor header files
Impact:
- Affects imx6/cxd56xx/lc823450 SMP with interrupt stack enabled
Testing:
- Tested with sabre-6quad:smp (with QEMU, NCPUS=1 and 4)
- Tested with spresense:wifi_smp (NCPUS=1 and 2)
- Tested with lc823450-xgevk:rndis (NCPUS=1 and 2)
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
