Add an option to use HSE on the Nucleo-H563ZI with board modification. This is enabled through board Kconfig.
It supplies the same PLL output frequencies using the HSE instead of HSI, for significantly more precise clocks.
Adds ADC support with minimal feature set (no DMA or Timers etc). A new nucleo-h563zi configuration was added to
provide easy testing with the adc example NSH addon.
Fix Kconfig spacing to tabs
The PLL clock configuration was simplified on the assumption the clocks are correctly set in the board.h file. Instead of seperate conditions
for register components, assume the relevant PLL registers are fully defined in board.h. This should result in easier to understand defines in board.h
and simpler code flow in the standard clock configuration function.
Changes were mad in the board file alongside changing the arch files. Changes to board/stm32h5:
- PLL1 has been configured to use integer instead of fractional mode to reach the 250 MHz target. PLL2 and PLL3 configurations were
removed since they are currently unused in the H5 configuration.
- PLL1 output was verified by testing for changes in serial baud rate.
Most tools used for compliance and SBOM generation use SPDX identifiers
This change brings us a step closer to an easy SBOM generation.
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
This commit adds files in preperation of adding ethernet drivers for the STM32H563 and Nucleo-H563ZI board.
It also modifies the pinmap to include ethernet pins (and cleaned up leftover comments from L5 file), as well as
add those pins to the board.h for the nucleo-h563zi.
Files added:
- arch/arm/src/stm32h5/hardware/stm32_ethernet.h
- arch/arm/src/stm32h5/hardware/stm32_sbs.h
- Not fully implemented, just register necessary for ethernet driver.
PLL1FRACN was being set improperly. stm32h5xxx_rcc.c does not shift the value provided by board.h. So it was being set wrong. The defintions in stm32h5xxx_rcc.h shift the FRACN value and are now used by board.h. Also, board.h was not setting PLL1P properly. PLL1P can not have odd divisors. Therefore a value of 0 was invalid. Set it to a value of 1 (divide by 2), then adjust PLL1N to 31 and PLL1FRAC1 to 2048 to actually set SYSCLK to 250MHz.
Made fixes to issues from CI. Nxstyle and defconfig syntax.
This is a combination of 6 commits.
Adding STM32H5 arch files. With comments addressed.
Created stm32h5 directory to add support for the H5 chip, and used a Nucleo-H563ZI dev board during development. The goal was to get a working nutshell through the STLink connector on the board.
Remove board/docs changes for PR update.
Squash commits into one for PR guideline conformity.
trying to fix build issues
Fix format from review
Nucleo-H563ZI support for NSH.
Created stm32h5 directory to add support for the H5 chip, and used a Nucleo-H563ZI dev board during development. The goal was to get a working nutshell through the STLink connector on the board.
Fix switch default case placement.
NXstyle fixes
Renaming files
rename stm32h5_gpio.x files
rename h5 hsi48 files
Rename h5 idle file
rename stm32h5_irq.c
Rename some rcc functions and stm32h5_rcc.c
rename stm32h5_rcc.h
Rename stm32h5_pwr.x
lowputc renames
timerisr renames
uart renamed
rename serial file
rename start
Turn off the defines that enable DMA on serial
remove DMA Kconfig options
Remove H5 documentation. Will add in a future PR.
Fix styling and defconfig improper syntax.
