Add support for memory partitioning for OTA updates.
This feature is targeted at the integration of ESP32 boards with RISC-V architecture in conjunction with MCUboot
Signed-off-by: davidiogos <davi.silva@agrosystem.com.br>
riscv_internal.h is used literally everywhere, while the SBI definitions
are needed only by whomever needs the services.
Having the SBI definitions:
a) Copied from OpenSBI (why has this been done? even the names are same)
b) Presented publicly to 99% of risc-v modules
creates a build error when building with OpenSBI, due to duplicate
definitions of the SBI service identifiers:
In file included from /nuttx/arch/risc-v/src/common/riscv_internal.h:40,
from /nuttx/arch/risc-v/src/chip/chip.h:32,
from board/mpfs_domain.c:30:
/nuttx/arch/risc-v/src/common/riscv_sbi.h:36: error: "SBI_EXT_BASE" redefined [-Werror]
36 | #define SBI_EXT_BASE 0x00000010
and so forth...
Fix this by removing riscv_sbi.h i.e. not exposing the ABI publicly.
Since the size of the shadow area will change during the script merging of global variables, it will lead to unpredictable number of links. After fixing, only three links are required.
Signed-off-by: wangmingrong1 <wangmingrong1@xiaomi.com>
Provides two implementations:
- CSR_CYCLE: Cores which implement hardware performance monitoring.
- CSR_TIME: Uses the machine time registers.
Using the up_perf_xx bindings directory is more efficient than performing a nanosecond conversion on every gettime event.
This commit ensures that RTC data is properly allocated in the RTC
segment in the linker. This fixes the reported problem about using
the legacy bootloader and RTC.
Update internal reference to get the most updated Espressif's
libraries. Those libraries are based on branch `release/v5.1` of
the ESP-IDF and include `v5.1.4` version of it.
(1) Keep the `.init_array` and `.ctors` symbols and sort them according to their initialization priority.
(2) Exclude symbols ending with crtend.* and crtbegin.* to support c++
application.if we not exclude crtend.* crtbegin.* frame_dummy will be
added when enable any c++ application with global variables, this symbol
execution is problematic, removing it does not affect the application.
Signed-off-by: cuiziwei <cuiziwei@xiaomi.com>
This renames a few RV32 configs to follow the convention that names w/o
numbers are for RV32, so that to be in line with majority RV32 configs.
As a result, we have: `nsh` vs `nsh64`, `knsh` vs `knsh64`, `pnsh`
vs `pnsh64`,`flats` vs `flats64`, `nsbi` vs `nsbi64`, `libcxx` vs
`libcxx64` etc. This helps us pick the right config name w/o checking
file contents.
Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
This PR adds a new Build Config `rv-virt:leds64_rust` that builds the Rust App `leds_rust` for QEMU RISC-V 64-bit. The build requires the [Rust Target `riscv64gc-unknown-none-elf`](https://github.com/apache/nuttx/pull/12858):
```bash
rustup target add riscv64gc-unknown-none-elf
```
New Files:
`boards/risc-v/qemu-rv/rv-virt/configs/leds64_rust/defconfig`: Add new Build Config `rv-virt:leds64_rust`
Updated Docs:
`applications/examples/leds_rust/index.rst`: Add `leds_rust` example app
`platforms/risc-v/qemu-rv/boards/rv-virt/index.rst`: Add `rv-virt:leds64_rust` config
This revises PROTECTED build for qemu-rv mainly to avoid hard-coded
addresses in linker scripts. It also added rv32 support, cleaned up
config `pnsh64` and added config `pnsh`.
Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
This adds NuttSBI support for rv-virt device so that to enable CI
checks for NuttSBI later. It allows using `-bios nuttx` option to
run NuttX with QEMU v6.2 w/o OpenSBI.
Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
This change implements a driver for the two watchdog timers on the BL808, and enables it as part of the timer config. The driver is based on the GP timer driver.
This revises FLAT build ld.script so that to use CONFIG_RAM_START
instead of hard coded address to increase flexibility.
Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
This allows virtio devices to be probed upon board_early_init, thus
making virito-serial ready earlier for console use.
Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
- This PR adds the LED Driver for QEMU RISC-V 32-bit and 64-bit (User LEDs and Auto LEDs)
- QEMU RISC-V LED Driver will be used by the Rust Blinky App for Google Summer of Code
- Blinking the LED is probably the most common Embedded Demo, and now it's supported by QEMU RISC-V
- We added NuttX Configs `rv-virt:leds` and `rv-virt:leds64` to support User LEDs for 32-bit and 64-bit RISC-V
- Turning on/off a Simulated User LED will print a log message: "LED 1 set to 1"
- The code is derived from NuttX PinePhone LED Driver
This adjusts canmv230 `master` and `remote` configs to support both
k230 and k230d devices and drop unused items.
Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
This revises canm230:pnsh in a few ways:
- adjusting linker scripts structure,
- asserting PMP setting results,
- adjusting configs for both k230d and k230 devices.
Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
This commit implements a character driver for the general purpose ADC of the BL808, based on the hardware scanning functionality. The driver supports setting different conversion resolutions and the order of channels to be scanned via menuconfig.
- This PR adds the LED Driver for Ox64 Board (User LEDs and Auto LEDs)
- Ox64 LED Driver will be used by the Rust Blinky App for Google Summer of Code
- User LED 1 is configured for GPIO 29. Other User LEDs and Auto LEDs shall be configured by the NuttX Dev.
- The code is derived from NuttX PinePhone LED Driver
This revises ld-nuttsbi.script for easier use. It also adjusts
canmv230/nsbi to fit both k230d and k230 devices.
Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
This commit modifies the existing serial driver to add support for the remaining UARTs on the BL808. It also introduces support for setting baud rate, character length, stop bits, parity, flow control and which serial port acts as the console.
This change implements a system for allowing the D0 core (which runs NuttX) to receive forwarded interrupts from the M0 core. This makes it possible for drivers that rely on interrupts to work with peripherals attached to the M0 core.
This PR adds support for Milk-V Duo S 64-bit RISC-V SBC, based on SOPHGO SG2000 SoC (T-Head C906 Core). Most of the code is derived from NuttX for Ox64 BL808. The source files are explained in the articles here: https://github.com/lupyuen/nuttx-sg2000
Modified Files:
`boards/Kconfig`: Added Milk-V Duo S board
`arch/risc-v/src/sg2000/sg2000_timerisr.c`: Fixed MTIMER_FREQ for sleep() to work correctly
New Files in boards/risc-v/sg2000/milkv_duos:
`src/sg2000_appinit.c`: Startup Code
`include/board.h`: Milk-V Duo S Definitions
`include/board_memorymap.h`: Memory Map
`src/etc/init.d/rc.sysinit`, `rcS`: Startup Script
`src/.gitignore`: Ignore the tmp filesystem
`scripts/ld.script`: Linker Script
`scripts/Make.defs`: Milk-V Duo S Makefile
`src/Makefile`: Milk-V Duo S Makefile
`Kconfig`: Milk-V Duo S Config
`configs/nsh/defconfig`: Build Config for `milkv_duos:nsh`
Updated Documentation:
`platforms/risc-v/sg2000/index.rst`: New page for SOPHGO SG2000 SoC
`platforms/risc-v/sg2000/boards/milkv_duos/index.rst`: Building and booting NuttX for Milk-V Duo S
There is no need to use kernel build for S-mode all the time. As cpu
scratch is supported for non kernel mode build, it is possible to use
flat build for S-mode.
Add flat build support for risc-v S mode.
Signed-off-by: Inochi Amaoto <inochiama@outlook.com>
This provides an alternate tickless scheduling method, which uses the riscv
mtimer as a timebase, allowing the time and timeh registers to used
throughout an application.
The exiting tickless method, using Litex's timer0 has been left in place, as
it is a more performant option, but currently has the potential issue
identified in #11189.
rv-virt support different size of ksram and pgmem region, but the
fixed value in the link script limits this function. As nuttx supports
preprocessing the link script. It is better to use the config value
to compute the memory layout. This also make all kernel build use the
same script.
Signed-off-by: Inochi Amaoto <inochiama@outlook.com>
Add partition parsing logic to emmcsd and support for configuring either CDCACM alone or
both CDCACM and USBMCS for composite mode.
Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
The original names are confusing; the symbols' addresses point to the start and end of the
sbi executable ram area. This may also reside in l2lim and not in ddr, depending on the
configuration, and this is defined in the linker script.
Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
