mirror of
https://github.com/apache/nuttx.git
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1cfab89e65
Register addresses are defined. Bit defintions are still needed. Bitmaps for OCTOSPI peripheral register Incremental updates to qspi files Redefined QSPI/OCTOSPI registers for STM32H5 Fixed register definitions for the STM32H5. However, more work still needs to be done. Some bits that shared registers on the STM32H7 have different register locations on the H5. This still needs to be accounted for. Fixed more differences vs STM32H7 qspi Added ifdef for including stm32_dma.h in stm32_qspi.c. Added stm32_qspi.c to Make.defs. Register fixes. SPI activity but not able to format device yet. Fixed DCYC mask Set HCLK frequency to correct value. Undid ccrconfig debug. Tested Interrupt Mode (single SPI). Added alternate bytes to meminfo and cmdinfo structures. Updated Kconfig variables for STM32H5. Fixed base register in hardware/stm32_qspi.h. Updated qspi_dumpregs. The base register was previously set to STM32_QUADSPI_BASE, changed to the correctly named STM32_OCTOSPI1_BASE. However, these defines for the OCTOSPI registers are not even used. Instead qspi_putreg and qspi_getreg utilize the priv->base value to access OCTOSPI registers. Removed altbytes code, left as before. Moved QSPI clock selection to stm32h5xx_rcc.c Changed STM32H5_QUADSPI to STM32H5_QSPI1 Added hook to define QSPI_CLK_FREQUENCY as STM32_QSPI_FREQUENCY from board.h Removed changes to nuttx qspi.h style fixes |
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| arm | ||
| arm64 | ||
| avr | ||
| ceva | ||
| dummy | ||
| hc | ||
| mips | ||
| misoc | ||
| or1k | ||
| renesas | ||
| risc-v | ||
| sim | ||
| sparc | ||
| tricore | ||
| x86 | ||
| x86_64 | ||
| xtensa | ||
| z16 | ||
| z80 | ||
| CMakeLists.txt | ||
| Kconfig | ||