knsh_romfs - for QEMU and legacy serial port
knsh_romfs_pci - for bare-metal Intel hardware and PCI serial port
Steps to build kernel image with user-space apps in romfs:
$ ./tools/configure.sh qemu-intel64/knsh_romfs
$ make -j
$ make export -j
$ pushd ../apps
$ ./tools/mkimport.sh -z -x ../nuttx/nuttx-export-*.tar.gz
$ make import -j
$ ./tools/mkromfsimg.sh
$ mv boot_romfsimg.h ../nuttx/arch/x86_64/src/board/romfs_boot.c
$ popd
$ make -j
Signed-off-by: p-szafonimateusz <p-szafonimateusz@xiaomi.com>
Add lvgl and fb examples for qemu-intel64.
NOTE: multiboot framebufer doesn't work with -kernel argument in QEMU,
NuttX image must be loaded with -cdrom argument.
QEMU command to run examples:
qemu-system-x86_64 -m 2G -cpu host -enable-kvm -cdrom disk.iso -serial mon:stdio
Signed-off-by: p-szafonimateusz <p-szafonimateusz@xiaomi.com>
Most tools used for compliance and SBOM generation use SPDX identifiers
This change brings us a step closer to an easy SBOM generation.
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
The segment of the Xen PVH boot protocol was not specified during linking and was placed before .loader.text, causing the boot to fail
Signed-off-by: liwenxiang1 <liwenxiang1@xiaomi.com>
This commit reimplemented the NuttX32 multiboot1 wrapper:
1. Fixed the issue of SMP AP booting.
2. Reduced memory copy overhead. We only need to copy .realmode section
now.
3. Move the multiboot1 header to intel64_head.S.
Signed-off-by: ouyangxiangzhen <ouyangxiangzhen@xiaomi.com>
add configs with PCI serial console for qemu-intel64 so we can run NuttX on bare
metal Intel HW with serial port card
Signed-off-by: p-szafonimateusz <p-szafonimateusz@xiaomi.com>
move MCR_OUT2 configuration from qemu-intel64/src/qemu_boot.c to common code
also leave this option disabled for qemu-intel64 as it's not required
Signed-off-by: p-szafonimateusz <p-szafonimateusz@xiaomi.com>
Some of PCI drivers require OS interfaces that can't be executed in the INIT context.
In that case we have to postpone PCI drivers probing and call it for example
in board initialization logic.
Signed-off-by: p-szafonimateusz <p-szafonimateusz@xiaomi.com>
enable debug messages for PCI configuration in qemu-intel64
so we know exactly what happen during execution
Signed-off-by: p-szafonimateusz <p-szafonimateusz@xiaomi.com>
HPET can be used as system clock for x86_64
to set HPET as system clock you have to enable:
CONFIG_ONESHOT=y
CONFIG_ALARM_ARCH=y
CONFIG_INTEL64_ONESHOT=y
CONFIG_ARCH_INTEL64_HPET_ALARM=y
Signed-off-by: p-szafonimateusz <p-szafonimateusz@xiaomi.com>
this partly revert 4123615621 which works OK for PCI serial and network cards
but breaks QEMU EDU due to usage of sem and usleep in IDLE thread context.
Another solution will be provided later.
Signed-off-by: p-szafonimateusz <p-szafonimateusz@xiaomi.com>
DEBUG_FULLOPT enables many x86 related optimizations which can
be broken in many ways (eg. not aligned stack).
With this change it's easier to catch changes that breaks x86_64.
Signed-off-by: p-szafonimateusz <p-szafonimateusz@xiaomi.com>
Align _ebss to 16, otherwise g_idle_topstack is not correctly aligned.
For some reason the previous alignment worked with make buit but in case
of cmake with optimization enabled, the IDLE stack was misaligned which
caused vector instruction misalignment exception.
Signed-off-by: p-szafonimateusz <p-szafonimateusz@xiaomi.com>
This adds support for creating an early frame buffer and primatives for
writing to this frame buffer as a console. This does require the font
infrastructure as well as multiboot2.
Additionally this can now be used with a UEFI bootloader long as it
boots NuttX via Multiboot2. There does seem to be a PCI interrupt
issue when running in UEFI mode.
I was able to boot my laptop using this and see PCI devices enumerate.
Signed-off-by: Brennan Ashton <bashton@brennanashton.com>
x86_64: Add conditionals around the multiboot framebuffer
Squashed commits:
1. Porting prior PCI work in place of jailhouse code
At this point the PCI enumeration works for x86_64 including over
pci-pci bridges.
Running QEMU with this configuration we see the bridge and the
device on the bridge. It also detected the qemu test device
qemu-system-x86_64 \
-cpu host,+pcid,+x2apic,+tsc-deadline,+xsave,+rdrand \
--enable-kvm -smp 1 -m 2G -cdrom boot.iso --nographic -no-reboot \
-device pci-testdev \
-device pci-bridge,id=bridge0,chassis_nr=2 \
-device e1000,bus=bridge0,addr=0x3
qemu_pci_init: Initializing PCI Bus
pci_probe_device: [00:00.0] Found 8086:1237, class/revision 06000002
pci_probe_device: [00:01.1] Found 8086:7010, class/revision 01018000
pci_probe_device: [00:01.2] Found ffff:ffff, class/revision ffffffff
pci_probe_device: [00:01.3] Found 8086:7113, class/revision 06800003
pci_probe_device: [00:01.4] Found ffff:ffff, class/revision ffffffff
pci_probe_device: [00:01.5] Found ffff:ffff, class/revision ffffffff
pci_probe_device: [00:01.6] Found ffff:ffff, class/revision ffffffff
pci_probe_device: [00:01.7] Found ffff:ffff, class/revision ffffffff
pci_probe_device: [00:02.0] Found 1234:1111, class/revision 03000002
pci_probe_device: [00:03.0] Found 8086:100e, class/revision 02000003
pci_probe_device: [00:04.0] Found 1b36:0005, class/revision 00ff0000
pci_probe_device: [00:04.0] Probing
pci_check_pci_bridge: [00:05.0] Found Bridge
pci_probe_device: [01:03.0] Found 8086:100e, class/revision 02000003
pci_probe_device: [00:05.0] Found 1b36:0001, class/revision 06040000
2. Remove unused CONFIG_PCI_MAX_BDF option
3. Add a workaround for Jailhouse pci scanning
4. Extend BAR parsing and handle PIO and MMIO for pci-testdev
Signed-off-by: Brennan Ashton <bashton@brennanashton.com>
5. PCI: Add initial support for QEMU 'edu' test device
Signed-off-by: Brennan Ashton <bashton@brennanashton.com>
6. Bring up PCI later in boot process
Signed-off-by: Brennan Ashton <bashton@brennanashton.com>
7. Add ISR and DMA support to QEMU edu test pci device
Signed-off-by: Brennan Ashton <bashton@brennanashton.com>
8. Fix bad function prototype definition in qemu_edu
9. intel64: Add a pci test configuration and instructions
Signed-off-by: Brennan Ashton <bashton@brennanashton.com>
10. PCI: Fix issue in identification of 64bit bar
Signed-off-by: Brennan Ashton <bashton@brennanashton.com>
Squashed commits:
1. x86_64: qemu: implement pci-e functions and enumerate pci-e devices on boot
2. virt: add qemu pci-testdev driver
3. pcie: types array should be null terminated
4. pcie: enable don't take flags, hardcoded enabling flags
5. pcie: checking bar > 4 for 64bit bars are sufficient
6. pcie: qemu: remove not used header
7. pcie: qemu: return -EINVAL if buffer argument is NULL
8. pcie: make pcie enumerate routine as common instead of architecture dependent
9. pcie: cosmetic changes to fit check tools
10. pcie: create MSI/MSIX related marcos and simplify the msi/msix routines
- migrated /README are removed from /boards
- there are a lot of READMEs that should be further converted to rst.
At the moment they are moved to Documentation/platforms and included in rst files
