Summary
add memory map for DDR region
fix arm-v7a/knsh boot dataabort on arm_addrenv_utils.c first time memset
after arm_pgvaddr.
Signed-off-by: qinwei1 <qinwei1@xiaomi.com>
Return 0 for CPU ID for any hart ID, and return the current Hart ID for
any CPU ID. At least these values are somewhat usable / meaningful in
non-SMP configurations.
MPFS implements external interrupt control on a per-hart basis i.e. there
are PLIC control registers for each hart separately. This means we need
a procedure to initialize such registers for each hart individually,
instead of only for the boot hart like it is now.
Fix this by implementing mpfs_plic_init_hart which can be called by each
hart as needed.
Note: it is not a good idea to initialize all harts from the boot hart,
as the boot hart may not know which harts are used by NuttX in AMP
configuration. It is better that the hart initializes itself.
Note: The hartid must be provided as explicit parameter, as it cannot
be queried via riscv_mhartid() yet; the per-cpu structure is initialized
later on which means riscv_mhartid() would return 0 for all harts except
the boot hart.
that pr requires chip turn on CONFIG_DRIVERS_BLUETOOTH to use bluetooth,
but not all defconig enable this option, so let's map bt_driver_register
to bt_netdev_register in header file in this case, and revert the unnessary
change in the related chip and board folders.
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
When sig dispatch do up_schedule_sigaction, need to make a new frame to
run arm_sigdeliver. But the exception_direct cannot handle xcp.regs as
we are using c-function exception handler.
Need to use exception_common to handle SMP call.
Signed-off-by: buxiasen <buxiasen@xiaomi.com>
Implement hartid<->cpuid mapping for RISC-V. This is necessary for some
platforms which cannot use 1:1 mapping between logical and physical CPU /
core IDs. One example is MPFS where hart0 cannot be used for NuttX SMP as
it is a less capable "monitor" core (E51) compared to the application
cores hart1...3 (E54).
Why not just use a generic offset then? We also need the physical hart ID
for many things:
- Communication between harts (IPI)
- External interrupt acknowledgment (interrupt claim for specific CPU)
- Communication to SBI
Thus, create procedures that can do this translation:
- The default mapping is still logical=physical.
- Another flavor is to use the existing CONFIG_ARCH_RV_HARTID_BASE config
variable, which is just a simple offset
- The final flavor is to overload hartid<->cpuid on a per chip basis (no
example for this is provided yet)
This implements empty hooks to the arch/chip layer, which can implement
an optional translation between logical<->physical CPU/core id.
The default mapping is 1:1 i.e. logical=physical.
The function is supposed to return the physical hart ID. It is needed
for e.g. external interrupt acknowledgment (see mpfs_plic.c).
This offset is moved initially to up_cpu_index (which is also wrong, but
less wrong than the current implementation). Finally, a translation
between physical <-> logical shall be provided.
this_task obtains the CPU ID through the GS register, so the initial value of GS needs to be configured in x86_64_cpu_priv_set
Signed-off-by: liwenxiang1 <liwenxiang1@xiaomi.com>
x86_64/intel64: fix SMP compilation warnings
Signed-off-by: p-szafonimateusz <p-szafonimateusz@xiaomi.com>
Implement PIC loading in armv8-m qemu,
for example: load address-independent AP ELF in the bootloader,
and the text segment in AP ELF is XIP,
no need to apply for memory and modify it.
Two config:
bootloader abbreviation bl:
use romfs to load ap elf, use the boot command to parse and jump to ap
application abbreviation ap:
run os test
We need to compile ap first, then compile bl.
compile step:
./tools/configure.sh mps3-an547:ap
make -j20
mkdir -p pic
cp boot pic/.
genromfs -a 128 -f ../romfs.img -d pic
make distclean -j20
./tools/configure.sh mps3-an547:bl
make -j20
run qemu:
qemu-system-arm -M mps3-an547 -m 2G -nographic -kernel nuttx.bin \
-gdb tcp::1127 -device loader,file=../romfs.img,addr=0x60000000
nsh> boot /etc/boot
ap> ostest
Signed-off-by: anjiahao <anjiahao@xiaomi.com>
Need to start up a new to setup special registers use
`arm_pic_setupxcp`.
Note that CONFIG_BUILD_PIC compiles the entire NuttX image
as position-independent(PIC), enable CONFIG_PIC to load PIC
application code.
Signed-off-by: anjiahao <anjiahao@xiaomi.com>
The default heap management in nuttx returns a valid memory address when malloc(0).
In sim_heap, malloc(0) returns NULL, aligning the behavior of sim_heap with mm_heap
The man manual describes malloc as follows:
https://man7.org/linux/man-pages/man3/malloc.3.html
The malloc() function allocates size bytes and returns a pointer
to the allocated memory. The memory is not initialized. If size
is 0, then malloc() returns a unique pointer value that can later
be successfully passed to free(). (See "Nonportable behavior"
for portability issues.)
Signed-off-by: yinshengkai <yinshengkai@xiaomi.com>
This commit addresses the issue of unauthorized writes to cntfrq_el0 during boot when not in EL3 mode.
Signed-off-by: ouyangxiangzhen <ouyangxiangzhen@xiaomi.com>
The segment of the Xen PVH boot protocol was not specified during linking and was placed before .loader.text, causing the boot to fail
Signed-off-by: liwenxiang1 <liwenxiang1@xiaomi.com>
Added a flash driver for the STM32G4 series. The primary change here is
the addition of stm32g4xxx_flash.c. This file uses the STM32L4 flash
driver as a template. The primary difference is the accounting for dual
banks with different page sizes.
Fixed error while building b-g474e-dpow1/buckboost. It was possible (technically) to have page be used uninitialzied. Changing the if statement to default to using a flash_page_size == 2048 fixes this issue.
In armv8m the FPSCR[18:16] LTPSIZE field must be set to 0b100 for
"Tail predication not applied" as it's reset value.
Signed-off-by: zhangyuan29 <zhangyuan29@xiaomi.com>
Summary:
1. Support armv7-a armv7-r armv8-r
2. The NSACR is read-only in Non-secure PL1 and PL2 modes.
3. The NSACR is read/write in Secure PL1 modes.
4. When the NSACR.{CP11,CP10} bit is set to 1,
Non-secure access to coprocessor 11,10 enable
Signed-off-by: wangming9 <wangming9@xiaomi.com>
Signed-off-by: lipengfei28 <lipengfei28@xiaomi.com>
Summary:
Add the default CPU frequency configuration.
Signed-off-by: wangming9 <wangming9@xiaomi.com>
Signed-off-by: lipengfei28 <lipengfei28@xiaomi.com>
toolchain file variable is global scope
dont need set parent scope
clear warning:
CMake Warning (dev) at /github/workspace/sources/nuttx/arch/arm/src/cmake/gcc.cmake:69 (set):
Cannot set "GCCVER": current scope has no parent.
Call Stack (most recent call first):
/github/workspace/sources/nuttx/arch/arm/src/cmake/Toolchain.cmake:56 (include)
/github/workspace/sources/nuttx/build/CMakeFiles/3.26.0/CMakeSystem.cmake:6 (include)
/github/workspace/sources/nuttx/build/CMakeFiles/CMakeScratch/TryCompile-ZJVOZO/CMakeLists.txt:5 (project)
This warning is for project developers. Use -Wno-dev to suppress it.
Signed-off-by: xuxin19 <xuxin19@xiaomi.com>
Add _dl_find_object() function, because when cxx_exception configuration is enabled, a link error occurs and that function cannot be found.
ld: /usr/lib/gcc/x86_64-linux-gnu/13/libgcc_eh.a(unwind-dw2-fde-dip.o): in function `_Unwind_Find_FDE':
(.text+0x250c): undefined reference to `_dl_find_object'
Signed-off-by: cuiziwei <cuiziwei@xiaomi.com>
common/arm64_mpu.c:355:13: error: format '%llX' expects argument of type 'long long unsigned int', but argument 4 has type 'long unsigned int' [-Werror=format=]
355 | _info("MPU-%d, 0x%08llX-0x%08llX SH=%llX AP=%llX XN=%llX\n", i,
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
common/arm64_mpu.c:355:29: note: format string is defined here
355 | _info("MPU-%d, 0x%08llX-0x%08llX SH=%llX AP=%llX XN=%llX\n", i,
| ~~~~~^
| |
| long long unsigned int
| %08lX
common/arm64_mpu.c:355:13: error: format '%llX' expects argument of type 'long long unsigned int', but argument 5 has type 'long unsigned int' [-Werror=format=]
355 | _info("MPU-%d, 0x%08llX-0x%08llX SH=%llX AP=%llX XN=%llX\n", i,
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
common/arm64_mpu.c:355:38: note: format string is defined here
355 | _info("MPU-%d, 0x%08llX-0x%08llX SH=%llX AP=%llX XN=%llX\n", i,
Signed-off-by: xuxingliang <xuxingliang@xiaomi.com>
We save interrupted TCB state on tcb->xcp.regs not interrupt stack now
which allows us to remove x86_64_savestate() from up_switch_context()
and other places.
Signed-off-by: p-szafonimateusz <p-szafonimateusz@xiaomi.com>
Signed-off-by: hujun5 <hujun5@xiaomi.com>
1. The -c parameter should not be added during the link phase, otherwise the link will fail.
2. If it is the clang compiler, its toolchain library should use --print-file-name to find it, otherwise an error will occur
Signed-off-by: wangmingrong1 <wangmingrong1@xiaomi.com>
When neon is enabled, compiler may optimize 64bits access to vstr, that
will cause data aborts.
Split 64bits access to double 32bits access for GIC_IROUTER/GICR_TYPER,
just like linux.
Signed-off-by: Jinliang Li <lijinliang1@lixiang.com>
Signed-off-by: chao an <anchao@lixiang.com>
Need to save the regs firstly in case syslog triggers another crash.
Otherwise we may loose the register contents for the first exception.
Signed-off-by: xuxingliang <xuxingliang@xiaomi.com>
1. Add config CONFIG_ARMV7A_GICv2_DUMP to control gic dump,
because irqinfo introduce too much other log;
2. Change the log api from irqinfo() to syslog(), syslog not
append the function name in the log, so the gic dump format
will not be destoried.
Signed-off-by: Bowen Wang <wangbowen6@xiaomi.com>
1. add IS_ALIGNED() definitions for NuttX;
2. replace all the ALIGN_UP() and ALIGN_DOWN() to use common
align implementation;
Signed-off-by: Bowen Wang <wangbowen6@xiaomi.com>
With aggresive optimization enabled (-O3), ostest FPU test will fail.This is because the compiler will generate additional vector instructions between subsequent up_fpucmp() calls (loop vectorization somewhere in usleep() call), which will consequently overwrite the expected FPU context (XMM registers).The compilation option -fno-tree-vectorize can avoid this issue.
Signed-off-by: liwenxiang1 <liwenxiang1@xiaomi.com>
When using alarm_arch implementation, 64-bit time can be returned. Using unsign long will cause precision loss.
Signed-off-by: yinshengkai <yinshengkai@xiaomi.com>
use correct macro for cpu_set_t busy variable and remove obsolote check
also remove not needed #include <sched.h> and "Public data"
Signed-off-by: p-szafonimateusz <p-szafonimateusz@xiaomi.com>
gprof can analyze code hot spots based on scheduled sampling.
After adding the "-pg" parameter when compiling, you can view the code call graph.
Signed-off-by: yinshengkai <yinshengkai@xiaomi.com>
Summary:
- GICv2 cannot be detected on the golsfish platform
- Golsfish uses version 2.12.0 of qemu with a GICC_IIDR value of 0,
read ICPIDR2 to determine the GIC version
Signed-off-by: wangming9 <wangming9@xiaomi.com>
Summary:
1、cntfrq_el0 is used to store the timer frequency, which may
be different from the CPU frequency.
2、Do not use up_perf interface for SMP.
Signed-off-by: wangming9 <wangming9@xiaomi.com>
Correct the alert message in `esp_setup_irq()` if
irq number allocation fails, the parameter number is not
matched with format specifier.
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
Some app with same code runs on different cores in AMP mode,
need the physical core on which the function is called.
Signed-off-by: hujun5 <hujun5@xiaomi.com>
Signed-off-by: fangxinyong <fangxinyong@xiaomi.com>
This PR support Nested interrupt in armv6/7/8m:
There are two types of nested interrupt model:
Zero latency nested interrupt
Interrupt Priority Note
Data abort Highest
SVC 0x50
High irq1 0x60 ISR can't access system API
irq_save() 0x70
High irq2 0x80 ISR can't access system API
normal irq3 0xB0
We have already support this mode before this PR
Nested interrupt which interrupt level lower than up_irq_save()
Interrupt Priority Note
Data abort Highest
SVC 0x70
irq_save() 0x80
High irq1 0x90 ISR can access system API
High irq2 0xA0 ISR can access system API
normal irq3 0xB0
Now, this PR can support this mode
Signed-off-by: ligd <liguiding1@xiaomi.com>
riscv_internal.h is used literally everywhere, while the SBI definitions
are needed only by whomever needs the services.
Having the SBI definitions:
a) Copied from OpenSBI (why has this been done? even the names are same)
b) Presented publicly to 99% of risc-v modules
creates a build error when building with OpenSBI, due to duplicate
definitions of the SBI service identifiers:
In file included from /nuttx/arch/risc-v/src/common/riscv_internal.h:40,
from /nuttx/arch/risc-v/src/chip/chip.h:32,
from board/mpfs_domain.c:30:
/nuttx/arch/risc-v/src/common/riscv_sbi.h:36: error: "SBI_EXT_BASE" redefined [-Werror]
36 | #define SBI_EXT_BASE 0x00000010
and so forth...
Fix this by removing riscv_sbi.h i.e. not exposing the ABI publicly.
