Commit graph

23129 commits

Author SHA1 Message Date
Xiang Xiao
24cb8c25ab bluetooth: Fix the incompatibility made by https://github.com/apache/nuttx/pull/14224
that pr requires chip turn on CONFIG_DRIVERS_BLUETOOTH to use bluetooth,
but not all defconig enable this option, so let's map bt_driver_register
to bt_netdev_register in header file in this case, and revert the unnessary
change in the related chip and board folders.

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2024-10-18 09:05:54 +08:00
buxiasen
bc019cb913 arm/lc823450: use custom vectors to make smp_call work with exception_common
Signed-off-by: buxiasen <buxiasen@xiaomi.com>
2024-10-17 22:57:14 +08:00
buxiasen
15804c340a arm/sam4cm: use custom vectors to make smp_call work with exception_common
Signed-off-by: buxiasen <buxiasen@xiaomi.com>
2024-10-17 22:57:14 +08:00
buxiasen
d410eedfde arm/rp2040: use custom vectors to make smp_call work with exception_common
Signed-off-by: buxiasen <buxiasen@xiaomi.com>
2024-10-17 22:57:14 +08:00
buxiasen
9a73b28973 arm/cxd56: use chip specific vectors to allow smpcall update regs
When sig dispatch do up_schedule_sigaction, need to make a new frame to
run arm_sigdeliver. But the exception_direct cannot handle xcp.regs as
we are using c-function exception handler.
Need to use exception_common to handle SMP call.

Signed-off-by: buxiasen <buxiasen@xiaomi.com>
2024-10-17 22:57:14 +08:00
buxiasen
4e2b77cb04 arch/arm: add support for chip to replace the default vector table
Signed-off-by: buxiasen <buxiasen@xiaomi.com>
2024-10-17 22:57:14 +08:00
Ville Juven
25b33f202e riscv_cpuindex.c: Fix usage of CONFIG_ARCH_RV_HARTID_BASE
The offset was supposed to assume hartid > cpuid, so when converting from
hartid we must subtract the offset to get the cpuid and vice versa.
2024-10-17 22:54:06 +08:00
chengkai
6aeb2e2996 Add space before error, bt_driver_register_internal not trigger error, add defconfig DRIVERS_BLUETOOTH.
Signed-off-by: chengkai <chengkai@xiaomi.com>
2024-10-17 18:09:32 +08:00
chengkai
31605b6335 bluetooth: call bt_driver_register common interface
Signed-off-by: chengkai <chengkai@xiaomi.com>
2024-10-17 18:09:32 +08:00
chengkai
113b660aa6 bluetooth: fix dev->rxlen is considered to have possibly overflowed
rootcause: fix the expression dev->rxlen is considered to
have possibly overflowed.

Signed-off-by: chengkai <chengkai@xiaomi.com>
2024-10-17 18:09:32 +08:00
chengkai
933841d985 bluetooth:support read imcompleted hci data from blueooth socket
hci data from bluetooth socket maybe imcompleted hci data.

Signed-off-by: chengkai <chengkai@xiaomi.com>
2024-10-17 18:09:32 +08:00
Ville Juven
8811eee0f4 riscv_cpustart.c: Fix reading of interrupt status
Let's read the interrupt status correctly, by checking for the interrupt
source bit instead of assuming no other status bit is set.
2024-10-17 18:08:10 +08:00
Ville Juven
8fe3ab3e39 arch/arm64: Remove arm64_copystate.c
The file is not referenced from anywhere and is obsolete / dead code anyway
-> remove it from the index.
2024-10-17 18:07:54 +08:00
Ville Juven
737dc4fcdd arch/riscv: Implement cpuid mapping
Implement hartid<->cpuid mapping for RISC-V. This is necessary for some
platforms which cannot use 1:1 mapping between logical and physical CPU /
core IDs. One example is MPFS where hart0 cannot be used for NuttX SMP as
it is a less capable "monitor" core (E51) compared to the application
cores hart1...3 (E54).

Why not just use a generic offset then? We also need the physical hart ID
for many things:
- Communication between harts (IPI)
- External interrupt acknowledgment (interrupt claim for specific CPU)
- Communication to SBI

Thus, create procedures that can do this translation:
- The default mapping is still logical=physical.
- Another flavor is to use the existing CONFIG_ARCH_RV_HARTID_BASE config
  variable, which is just a simple offset
- The final flavor is to overload hartid<->cpuid on a per chip basis (no
  example for this is provided yet)
2024-10-17 13:43:06 +08:00
Ville Juven
2195b47655 smp: Implement empty macro for obtaining logical CPU index
This implements empty hooks to the arch/chip layer, which can implement
an optional translation between logical<->physical CPU/core id.

The default mapping is 1:1 i.e. logical=physical.
2024-10-17 13:43:06 +08:00
Ville Juven
f47c0a1953 arch/riscv: Remove CONFIG_ARCH_RV_HARTID_BASE offset from riscv_mhartid
The function is supposed to return the physical hart ID. It is needed
for e.g. external interrupt acknowledgment (see mpfs_plic.c).

This offset is moved initially to up_cpu_index (which is also wrong, but
less wrong than the current implementation). Finally, a translation
between physical <-> logical shall be provided.
2024-10-17 13:43:06 +08:00
lipengfei28
ef350afd28 Revert "arch/arm64: add CONFIG_ARCH_VMA_MAPPING"
This reverts commit e7326cfa62.
2024-10-17 12:28:58 +08:00
Petro Karashchenko
2048715134 serial: remove 'TIOCSLINID'
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
2024-10-17 09:08:58 +08:00
Petro Karashchenko
919242d8b9 arch/arm/samv7: fix warnings in rswdt
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
2024-10-17 09:08:01 +08:00
Petro Karashchenko
beda2abe3b arch/arm/samv7: fix preprocessor logic for ethernet
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
2024-10-17 09:08:01 +08:00
Jukka Laitinen
d6c795dda3 imx9/flexcan: Make self reception disable to be configurable
Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
2024-10-17 09:02:17 +08:00
Xiang Xiao
c6aed84638 tools: Rename apps-or-nuttx-Make.defs to Make.defs
follow the same pattern as other Make.defs files

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2024-10-17 07:55:02 +08:00
yangsong8
8c13b8df1d syslog: convert \n to \r\n in syslog framework layer
Signed-off-by: yangsong8 <yangsong8@xiaomi.com>
2024-10-17 02:29:51 +08:00
Ville Juven
526ba1ab34 riscv/cpustart: Ensure we receive Soft IRQ / IPI before booting CPU
Some spurious interrupt might wake WFI, ensure we got woken by IPI before
continuing CPU boot.
2024-10-16 23:19:33 +08:00
liwenxiang1
eb27ebba8a arch/x86_64: The AP retrieves this_task after storing the CPU private data
this_task obtains the CPU ID through the GS register, so the initial value of GS needs to be configured in x86_64_cpu_priv_set

Signed-off-by: liwenxiang1 <liwenxiang1@xiaomi.com>

x86_64/intel64: fix SMP compilation warnings

Signed-off-by: p-szafonimateusz <p-szafonimateusz@xiaomi.com>
2024-10-16 22:09:00 +08:00
yaojingwei
aaace108fb sim_camera: modify sim camera init videosize using imgsensor extend params.
Signed-off-by: yaojingwei <yaojingwei@xiaomi.com>
2024-10-16 19:50:19 +08:00
nuttxs
1a621bcb37 xtensa/esp32s3: Inspect if the MTD partition (factory/ota_0/ota_1)
is mapped as text.
Relocate the enum ota_img_ctrl_e and ota_img_bootseq_e to
a directory visible to the application.
2024-10-16 18:43:58 +08:00
anjiahao
15fa55f234 mps3-an547:let ap build with pic,and use bootloader boot it
Implement PIC loading in armv8-m qemu,
for example: load address-independent AP ELF in the bootloader,
and the text segment in AP ELF is XIP,
no need to apply for memory and modify it.

Two config:

bootloader abbreviation bl:
  use romfs to load ap elf, use the boot command to parse and jump to ap

application abbreviation ap:
  run os test

We need to compile ap first, then compile bl.

compile step:
  ./tools/configure.sh mps3-an547:ap
  make -j20
  mkdir -p pic
  cp boot pic/.
  genromfs -a 128 -f ../romfs.img -d pic
  make distclean -j20
  ./tools/configure.sh mps3-an547:bl
  make -j20

run qemu:
  qemu-system-arm -M mps3-an547 -m 2G -nographic -kernel nuttx.bin \
    -gdb tcp::1127 -device loader,file=../romfs.img,addr=0x60000000

  nsh> boot /etc/boot
  ap> ostest

Signed-off-by: anjiahao <anjiahao@xiaomi.com>
2024-10-16 18:40:06 +08:00
anjiahao
c11a2fa450 arm-m:let vectors address align
According to the ARM architecture manual,
the address of vectors need alignment

Signed-off-by: anjiahao <anjiahao@xiaomi.com>
2024-10-16 18:40:06 +08:00
anjiahao
b81b16ba97 arm7/8-m:support all nuttx iamge build with pic
Need to start up a new to setup special registers use
`arm_pic_setupxcp`.

Note that CONFIG_BUILD_PIC compiles the entire NuttX image
as position-independent(PIC), enable CONFIG_PIC to load PIC
application code.

Signed-off-by: anjiahao <anjiahao@xiaomi.com>
2024-10-16 18:40:06 +08:00
anjiahao
112b6fd9a5 modlib:support modlib can load PIC elf
Signed-off-by: anjiahao <anjiahao@xiaomi.com>
2024-10-16 18:40:06 +08:00
fanjiangang
b6a4e91ef0 armv8-r/cp15: fix the problem of op1 operand confusion in ICC_SGI1R
Reference:

https://developer.arm.com/documentation/100026/0103/Generic-Interrupt-Controller/GIC-programmers-model/CPU-Interface-Registers

              CRn   Op1    CRm    Op2
    ICC_SGI0R  -     2     c12     -
    ICC_SGI1R  -     0     c12     -

Signed-off-by: fanjiangang <fanjiangang@lixiang.com>
Signed-off-by: chao an <anchao@lixiang.com>
2024-10-16 17:17:30 +08:00
yinshengkai
d01bbaecc1 sim/heap: malloc returns a valid pointer when allocating 0 bytes.
The default heap management in nuttx returns a valid memory address when malloc(0).
In sim_heap, malloc(0) returns NULL, aligning the behavior of sim_heap with mm_heap

The man manual describes malloc as follows:
https://man7.org/linux/man-pages/man3/malloc.3.html

The malloc() function allocates size bytes and returns a pointer
to the allocated memory.  The memory is not initialized.  If size
is 0, then malloc() returns a unique pointer value that can later
be successfully passed to free().  (See "Nonportable behavior"
for portability issues.)

Signed-off-by: yinshengkai <yinshengkai@xiaomi.com>
2024-10-16 17:03:40 +08:00
Jukka Laitinen
6a5b395459 arch/arm64/src/imx9: Add initial version of canbus driver
Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
2024-10-16 15:43:19 +08:00
Jukka Laitinen
bcfdb58686 arch/arm64/src/common/arm64_initialize.c: Add initializing of socket can interface
Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
2024-10-16 15:43:19 +08:00
wurui3
de2920605d sim_offload: add MONO channel encode method and set samplerate before encode.
According to different pcm data format, set real sample rate and encode separately.

Signed-off-by: wurui3 <wurui3@xiaomi.com>
2024-10-16 15:40:35 +08:00
wangmingrong1
bf70cd2bce bug/fix: Makefile expression error caused
expr: syntax error: unexpected argument "12"
expr: syntax error: unexpected argument "12"

Signed-off-by: wangmingrong1 <wangmingrong1@xiaomi.com>
2024-10-16 15:35:04 +08:00
Peter Bee
8f77e3cfc4 select ARM_HAVE_MVE and ARCH_HAVE_FPU for mps platform
Signed-off-by: Peter Bee <bijunda1@xiaomi.com>
2024-10-16 13:55:30 +08:00
ouyangxiangzhen
a45f903650 imx8qm-mek: Resolve boot issue for non-EL3 environments.
This commit addresses the issue of unauthorized writes to cntfrq_el0 during boot when not in EL3 mode.

Signed-off-by: ouyangxiangzhen <ouyangxiangzhen@xiaomi.com>
2024-10-16 13:54:44 +08:00
liwenxiang1
8a1743d0a6 arch/x86_64: Resolving NUC Boot Failure Issue
The segment of the Xen PVH boot protocol was not specified during linking and was placed before .loader.text, causing the boot to fail

Signed-off-by: liwenxiang1 <liwenxiang1@xiaomi.com>
2024-10-16 13:53:11 +08:00
wangming9
d9558a3583 arm/armv7-r: Correctly use CONFIG_ARMV7R_ASSOCIATIVITY_16WAY
Signed-off-by: wangming9 <wangming9@xiaomi.com>
Signed-off-by: lipengfei28 <lipengfei28@xiaomi.com>
2024-10-16 12:27:10 +08:00
qiaohaijiao1
54e128367d sim/alsa: clear AUDIO_APB_FINAL flag before DEQUEUE
Signed-off-by: qiaohaijiao1 <qiaohaijiao1@xiaomi.com>
2024-10-16 12:23:17 +08:00
qiaohaijiao1
eba292f4b9 sim/alsa: add ptr check in _stop
Signed-off-by: qiaohaijiao1 <qiaohaijiao1@xiaomi.com>
2024-10-16 12:21:19 +08:00
qiaohaijiao1
09afb4d7d0 sim/alsa: fix runtime warning.
sim/posix/sim_offload.c:369:18: runtime error: left shift of 255 by 24 places cannot be represented in type 'int'
    #0 0x3a146c2  (/home/qiaohj/disk1/work/vela/nuttx/nuttx+0x3a146c2)
    #1 0x3a0ecb0  (/home/qiaohj/disk1/work/vela/nuttx/nuttx+0x3a0ecb0)
    #2 0x3a1193a  (/home/qiaohj/disk1/work/vela/nuttx/nuttx+0x3a1193a)
    #3 0x3a13141  (/home/qiaohj/disk1/work/vela/nuttx/nuttx+0x3a13141)
    #4 0x39fc3ef  (/home/qiaohj/disk1/work/vela/nuttx/nuttx+0x39fc3ef)
    #5 0x38ca7f2  (/home/qiaohj/disk1/work/vela/nuttx/nuttx+0x38ca7f2)
    #6 0x39fc6cf  (/home/qiaohj/disk1/work/vela/nuttx/nuttx+0x39fc6cf)

Signed-off-by: qiaohaijiao1 <qiaohaijiao1@xiaomi.com>
2024-10-16 12:17:35 +08:00
Gao Jiawei
d5c44de14c add missing source file
Signed-off-by: Gao Jiawei <gaojiawei@xiaomi.com>
2024-10-16 08:04:13 +08:00
Kyle Wilson
df47241a2b STM32G4 Flash Driver
Added a flash driver for the STM32G4 series. The primary change here is
the addition of stm32g4xxx_flash.c. This file uses the STM32L4 flash
driver as a template. The primary difference is the accounting for dual
banks with different page sizes.

Fixed error while building b-g474e-dpow1/buckboost. It was possible (technically) to have page be used uninitialzied. Changing the if statement to default to using a flash_page_size == 2048 fixes this issue.
2024-10-15 18:11:38 -03:00
cuiziwei
9d9857acd2 Change the judgment of GCCVER version to greater equal.
Signed-off-by: cuiziwei <cuiziwei@xiaomi.com>
2024-10-15 23:32:13 +08:00
Tim Hardisty
bb7dce11a2 SAMA5 fix compiler warning in sam_adc.c 2024-10-15 11:37:54 -03:00
zhangyuan29
57650d841e armv8-m: set fpscr when do exception_direct
In armv8m the FPSCR[18:16] LTPSIZE field must be set to 0b100 for
"Tail predication not applied" as it's reset value.

Signed-off-by: zhangyuan29 <zhangyuan29@xiaomi.com>
2024-10-15 22:16:09 +08:00
anjiahao
ef9640c696 armv7-a:adjust gdb register order
Signed-off-by: anjiahao <anjiahao@xiaomi.com>
2024-10-15 21:46:41 +08:00
wangming9
5b14fb75bc arm/fpu: FPU is supported when the TEE is enabled
Summary:
1. Support armv7-a armv7-r armv8-r
2. The NSACR is read-only in Non-secure PL1 and PL2 modes.
3. The NSACR is read/write in Secure PL1 modes.
4. When the NSACR.{CP11,CP10} bit is set to 1,
   Non-secure access to coprocessor 11,10 enable

Signed-off-by: wangming9 <wangming9@xiaomi.com>
Signed-off-by: lipengfei28 <lipengfei28@xiaomi.com>
2024-10-15 21:11:15 +08:00
wangming9
f465443f37 cpuinfo: Decouple the fetch cpuinfo from up_perf_getfreq
Summary:
Add the default CPU frequency configuration.

Signed-off-by: wangming9 <wangming9@xiaomi.com>
Signed-off-by: lipengfei28 <lipengfei28@xiaomi.com>
2024-10-15 21:11:15 +08:00
wangming9
6ee747a1e6 arm/goldfish: add memory map for DDR region
Signed-off-by: wangming9 <wangming9@xiaomi.com>
Signed-off-by: lipengfei28 <lipengfei28@xiaomi.com>
2024-10-15 21:01:47 +08:00
hujun5
49b9aa0f33 arm/riscv: remove redundant judgment
Signed-off-by: hujun5 <hujun5@xiaomi.com>
2024-10-15 15:32:40 +08:00
hujun5
aa0346610b arm64: we need to initialize the percpu register storing the current task more earlier.
A call stack looks like the following:
sched_idletask
syslog_write
nx_vsyslog
syslog
getreg64
gic_validate_redist_version
arm64_gic_init
arm64_gic_secondary_init
arm64_boot_secondary_c_routine

Signed-off-by: hujun5 <hujun5@xiaomi.com>
2024-10-15 15:25:55 +08:00
hujun5
948ac9b4cc arm64: add up_this_task and up_change_task macro impl
Signed-off-by: hujun5 <hujun5@xiaomi.com>
2024-10-15 15:25:55 +08:00
xuxin19
696e1a3f70 cmake(fix warning):toolchain do not have parent scope
toolchain file variable is global scope
dont need set parent scope

clear warning:
CMake Warning (dev) at /github/workspace/sources/nuttx/arch/arm/src/cmake/gcc.cmake:69 (set):
  Cannot set "GCCVER": current scope has no parent.
Call Stack (most recent call first):
  /github/workspace/sources/nuttx/arch/arm/src/cmake/Toolchain.cmake:56 (include)
  /github/workspace/sources/nuttx/build/CMakeFiles/3.26.0/CMakeSystem.cmake:6 (include)
  /github/workspace/sources/nuttx/build/CMakeFiles/CMakeScratch/TryCompile-ZJVOZO/CMakeLists.txt:5 (project)
This warning is for project developers.  Use -Wno-dev to suppress it.

Signed-off-by: xuxin19 <xuxin19@xiaomi.com>
2024-10-15 12:38:14 +08:00
cuiziwei
036a0674db nuttx/libc:Add _dl_find_object and dl_iterate_phdr function.
Add _dl_find_object() function, because when cxx_exception configuration is enabled, a link error occurs and that function cannot be found.

ld: /usr/lib/gcc/x86_64-linux-gnu/13/libgcc_eh.a(unwind-dw2-fde-dip.o): in function `_Unwind_Find_FDE':
(.text+0x250c): undefined reference to `_dl_find_object'

Signed-off-by: cuiziwei <cuiziwei@xiaomi.com>
2024-10-15 12:35:54 +08:00
wanggang26
aef584a804 shm:fix build error
nuttx/arch/arm/src/armv7-a/arm_addrenv_shm.c:77:(.text.up_shmat+0x2e):
undefined reference to `shminfo'

Signed-off-by: wanggang26 <wanggang26@xiaomi.com>
2024-10-15 11:40:34 +08:00
wanggang26
7e5fb8450f coredump: add architecture-specific registers dump, including NVIC and MPU
Signed-off-by: wanggang26 <wanggang26@xiaomi.com>
2024-10-15 11:40:05 +08:00
cuiziwei
6f62ef0b6f nuttx/sim:Remove asan check in up_irq_save().
Signed-off-by: cuiziwei <cuiziwei@xiaomi.com>
2024-10-15 03:36:55 +08:00
hujun5
d77cb8af70 sched: fix nxsched_process_delivered did not call hook
Signed-off-by: hujun5 <hujun5@xiaomi.com>
2024-10-15 01:50:06 +08:00
hujun5
10659a8bc2 irq: irq_attach_wqueue replace irq_attach_thread
reason:
using a shared same priority queue can reduce memory consumption.

Signed-off-by: hujun5 <hujun5@xiaomi.com>
2024-10-15 01:12:14 +08:00
wanggang26
3fad764804 arch/armv7:fix a typo
Signed-off-by: wanggang26 <wanggang26@xiaomi.com>
2024-10-15 01:06:59 +08:00
Xu Xingliang
632feb2b51 arch/arm64: remove struct regs_context
Signed-off-by: Xu Xingliang <xuxingliang@xiaomi.com>
Signed-off-by: lipengfei28 <lipengfei28@xiaomi.com>
2024-10-14 23:05:56 +08:00
cuiziwei
a08df48774 arch/x86_64:Add CXX configuration for enabling x86_64 support for C++ applications.
Signed-off-by: cuiziwei <cuiziwei@xiaomi.com>
2024-10-14 19:03:30 +08:00
xuxingliang
f031dc39a6 arch/arm64: fix build warnings
common/arm64_mpu.c:355:13: error: format '%llX' expects argument of type 'long long unsigned int', but argument 4 has type 'long unsigned int' [-Werror=format=]
  355 |       _info("MPU-%d, 0x%08llX-0x%08llX SH=%llX AP=%llX XN=%llX\n", i,
      |             ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
common/arm64_mpu.c:355:29: note: format string is defined here
  355 |       _info("MPU-%d, 0x%08llX-0x%08llX SH=%llX AP=%llX XN=%llX\n", i,
      |                        ~~~~~^
      |                             |
      |                             long long unsigned int
      |                        %08lX
common/arm64_mpu.c:355:13: error: format '%llX' expects argument of type 'long long unsigned int', but argument 5 has type 'long unsigned int' [-Werror=format=]
  355 |       _info("MPU-%d, 0x%08llX-0x%08llX SH=%llX AP=%llX XN=%llX\n", i,
      |             ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
common/arm64_mpu.c:355:38: note: format string is defined here
  355 |       _info("MPU-%d, 0x%08llX-0x%08llX SH=%llX AP=%llX XN=%llX\n", i,

Signed-off-by: xuxingliang <xuxingliang@xiaomi.com>
2024-10-14 17:59:56 +08:00
chao an
7288a8d000 arch/arm64: add support to config SPI interrupt affinity routing to CPU0 by default
Signed-off-by: chao an <anchao@lixiang.com>
2024-10-14 17:58:13 +08:00
chao an
83c483c1b4 arch/armv8-a: new config to set SPIs Configuration to edge-triggered
Configure all SPIs(Shared Peripheral Interrupts) as edge-triggered by default

Signed-off-by: chao an <anchao@lixiang.com>
2024-10-14 17:58:13 +08:00
liwenxiang1
3e2e2132ca arch/x86_64:Adjust the position of the nm command to execute it after NuttX is generated
Signed-off-by: liwenxiang1 <liwenxiang1@xiaomi.com>
2024-10-14 17:55:59 +08:00
p-szafonimateusz
c18f722185 arch/intel64: optimise context switch
We save interrupted TCB state on tcb->xcp.regs not interrupt stack now
which allows us to remove x86_64_savestate() from up_switch_context()
and other places.

Signed-off-by: p-szafonimateusz <p-szafonimateusz@xiaomi.com>
Signed-off-by: hujun5 <hujun5@xiaomi.com>
2024-10-14 17:54:06 +08:00
xuxingliang
d655569a7c cmake: add newly added sources to cmake
These newly added files are missing from cmake.

Signed-off-by: xuxingliang <xuxingliang@xiaomi.com>
2024-10-14 17:19:45 +08:00
nuttxs
9308675686 xtensa/esp32s3: add wapi support for getting country code
commands on ESP32-S3
2024-10-14 13:42:37 +08:00
cuiziwei
7246533aeb Unify the definition of GCCVER and remove duplicate code.
Signed-off-by: cuiziwei <cuiziwei@xiaomi.com>
2024-10-13 11:41:22 +08:00
Marco Casaroli
c17ab3beb5 feat(esp32s3): add openeth ethernet driver for qemu
We add the config for esp32s3, then move the esp32 specifics to
esp32/chip.h, then add the esp32s3 specifics to esp32s3/chip.h.
2024-10-13 11:19:51 +08:00
Marco Casaroli
d5b32f0335 feat(esp32_openeth): move to common/espressif
Since this will be used for esp32s3 also, we can have this in
common/espressif.
2024-10-13 11:19:51 +08:00
xuxin19
57bfd02cef build ci:add msvc windows native ci workflow
Signed-off-by: xuxin19 <xuxin19@xiaomi.com>
2024-10-13 10:25:19 +08:00
chenzhijia
505adfa277 nuttx:move "#define STRINGIFY(x)" to nuttx/macro.h
Franklin requirement, "#define STRINGIFY(x)" conflicts with https://github.com/mborgerding/kissfft define

Signed-off-by: chenzhijia <chenzhijia@xiaomi.com>
Signed-off-by: lipengfei28 <lipengfei28@xiaomi.com>
2024-10-13 03:16:25 +08:00
Bowen Wang
143466baed drivers/pci: fix pci framework warning in 32bit chip
In file included from pci/pci.c:30:
pci/pci.c: In function 'pci_setup_device':
pci/pci.c:449:66: warning: right shift count >= width of type [-Wshift-count-overflow]
  449 |           pci_write_config_dword(dev, base_address_1, res->start >> 32);
      |                                                                  ^~
pci/pci.c: In function 'pci_presetup_bridge':
pci/pci.c:541:51: warning: right shift count >= width of type [-Wshift-count-overflow]
  541 |                              ctrl->mem_pref.start >> 32);
      |                                                   ^~
pci/pci.c: In function 'pci_postsetup_bridge':
pci/pci.c:604:57: warning: right shift count >= width of type [-Wshift-count-overflow]
  604 |                              (ctrl->mem_pref.start - 1) >> 32);
      |                                                         ^~
CC:  pthread/pthread_release.c pci/pci_ecam.c:71:12: warning: initialization of 'int (*)(struct pci_bus_s *, unsigned int,  int,  int,  uint32_t *)' {aka 'int (*)(struct pci_bus_s *, unsigned int,  int,  int,  long unsigned int *)'} from incompatible pointer type 'int (*)(struct pci_bus_s *, uint32_t,  int,  int,  uint32_t *)' {aka 'int (*)(struct pci_bus_s *, long unsigned int,  int,  int,  long unsigned int *)'} [-Wincompatible-pointer-types]
   71 |   .read  = pci_ecam_read_config,
      |            ^~~~~~~~~~~~~~~~~~~~
pci/pci_ecam.c:71:12: note: (near initialization for 'g_pci_ecam_ops.read')
pci/pci_ecam.c:72:12: warning: initialization of 'int (*)(struct pci_bus_s *, unsigned int,  int,  int,  uint32_t)' {aka 'int (*)(struct pci_bus_s *, unsigned int,  int,  int,  long unsigned int)'} from incompatible pointer type 'int (*)(struct pci_bus_s *, uint32_t,  int,  int,  uint32_t)' {aka 'int (*)(struct pci_bus_s *, long unsigned int,  int,  int,  long unsigned int)'} [-Wincompatible-pointer-types]
   72 |   .write = pci_ecam_write_config,

Signed-off-by: Bowen Wang <wangbowen6@xiaomi.com>
2024-10-13 02:28:32 +08:00
xuxin19
7def0983f6 cmake:sync arm sub arch CMake scripts missing sources
Signed-off-by: xuxin19 <xuxin19@xiaomi.com>
2024-10-13 02:25:06 +08:00
lipengfei28
e7326cfa62 arch/arm64: add CONFIG_ARCH_VMA_MAPPING
Signed-off-by: lipengfei28 <lipengfei28@xiaomi.com>
2024-10-13 02:09:38 +08:00
xuxin19
7b807a3947 cmake:fix x86_64 cmake configured warning
Signed-off-by: xuxin19 <xuxin19@xiaomi.com>
2024-10-13 02:08:38 +08:00
yangguangcai
80f2890c17 systick:when isr_handle is NULL will be crash.
Signed-off-by: yangguangcai <yangguangcai@xiaomi.com>
2024-10-13 00:32:55 +08:00
wangmingrong1
b12bf1ef33 arm/cmake: fix cmake compile error
1. The -c parameter should not be added during the link phase, otherwise the link will fail.
2. If it is the clang compiler, its toolchain library should use --print-file-name to find it, otherwise an error will occur

Signed-off-by: wangmingrong1 <wangmingrong1@xiaomi.com>
2024-10-12 20:37:43 +08:00
ska
3b273b1e3e Revert "nuttx/arch: Enabling ARCH_MATH_H is required when compiling sim with …"
This reverts commit 57e901e5ea.
2024-10-12 19:45:25 +08:00
Jinliang Li
36c63705db armv8-r/gicv3: disable 64bits access gic 64bits registers
When neon is enabled, compiler may optimize 64bits access to vstr, that
will cause data aborts.
Split 64bits access to double 32bits access for GIC_IROUTER/GICR_TYPER,
just like linux.

Signed-off-by: Jinliang Li <lijinliang1@lixiang.com>
Signed-off-by: chao an <anchao@lixiang.com>
2024-10-12 18:11:00 +08:00
xuxingliang
38858b6cc3 arch: set current regs firstly in undefinedinsn
Need to save the regs firstly in case syslog triggers another crash.
Otherwise we may loose the register contents for the first exception.

Signed-off-by: xuxingliang <xuxingliang@xiaomi.com>
2024-10-12 14:19:36 +08:00
fanjiangang
d8b042126e arch/arm: fix the bug of armv8-r macro GET_MPIDR
should be core not cpu

Signed-off-by: fanjiangang <fanjiangang@lixiang.com>
Signed-off-by: chao an <anchao@lixiang.com>
2024-10-12 14:00:32 +08:00
fanjiangang
044ee68e80 arm/armv8-r: add implements of arm_get_mpid()
Signed-off-by: fanjiangang <fanjiangang@lixiang.com>
Signed-off-by: chao an <anchao@lixiang.com>
2024-10-12 14:00:32 +08:00
hujun5
1ff49872a7 arch: There is no need to use sched_[un]lock
Signed-off-by: hujun5 <hujun5@xiaomi.com>
2024-10-12 13:28:23 +08:00
hujun5
ef8d8ee627 rtc: There is no need to use sched_[un]lock
Signed-off-by: hujun5 <hujun5@xiaomi.com>
2024-10-12 13:28:23 +08:00
anjiahao
e5f9b42ea0 binfmt/libelf:Remove libelf implementation [2/2]
this commit is part two, all logic move to modlib, so we can remove it.
and change all use defconfig

Signed-off-by: anjiahao <anjiahao@xiaomi.com>
2024-10-12 12:29:06 +08:00
cuiziwei
57e901e5ea nuttx/arch: Enabling ARCH_MATH_H is required when compiling sim with the 13.2 version of the toolchain.
Signed-off-by: cuiziwei <cuiziwei@xiaomi.com>
2024-10-12 12:05:05 +08:00
zhanghongyu
6f9543daec sim: fix crash caused by function recursion.
114 up_interrupt_context () at /home/zhhyu/source/vela/dev/nuttx/include/arch/irq.h:163
115 stack_monitor_enter (this_fn=0x400145dc <up_current_regs>, call_site=0x4002d5c7 <__cyg_profile_func_enter+120>, arg=0x0) at instrument/stack_monitor.c:63
116 0x000000004002d5c7 in __cyg_profile_func_enter (this_fn=0x400145dc <up_current_regs>, call_site=0x4002d5c7 <__cyg_profile_func_enter+120>) at misc/lib_instrument.c:68
117 0x00000000400156c7 in up_current_regs () at instrument/stack_monitor.c:62
118 up_interrupt_context () at /home/zhhyu/source/vela/dev/nuttx/include/arch/irq.h:163
119 stack_monitor_enter (this_fn=0x400145dc <up_current_regs>, call_site=0x4002d5c7 <__cyg_profile_func_enter+120>, arg=0x0) at instrument/stack_monitor.c:63
120 0x000000004002d5c7 in __cyg_profile_func_enter (this_fn=0x400145dc <up_current_regs>, call_site=0x4002d5c7 <__cyg_profile_func_enter+120>) at misc/lib_instrument.c:68
121 0x00000000400156c7 in up_current_regs () at instrument/stack_monitor.c:62
...

Signed-off-by: zhanghongyu <zhanghongyu@xiaomi.com>
2024-10-12 11:49:18 +08:00
liwenxiang1
43a8a80c74 arch/x86_64:Code style is consistent
Signed-off-by: liwenxiang1 <liwenxiang1@xiaomi.com>
2024-10-12 11:20:24 +08:00
hujun5
302d2f3b56 x86_64: align some code
Signed-off-by: hujun5 <hujun5@xiaomi.com>
2024-10-12 10:19:48 +08:00
Tim Hardisty
3027be72c3 Update sam_udphs.c 2024-10-12 09:51:19 +08:00
fangxinyong
55d7708fa0 boards/arm/qemu: enable kernel build for armv7a
See Documentation/platforms/arm/qemu/boards/qemu-armv7a/README.txt for details

Signed-off-by: fangxinyong <fangxinyong@xiaomi.com>
2024-10-12 09:28:45 +08:00
yanghuatao
323ee075be nuttx/qemu: Fix funciton up_idle multiple definition
Signed-off-by: yanghuatao <yanghuatao@xiaomi.com>
2024-10-12 09:28:45 +08:00
ligd
994e15710f goldfish: sync with qemu do rpmsg_syslog init at goldfish
Signed-off-by: ligd <liguiding1@xiaomi.com>
2024-10-11 22:42:34 +08:00
Bowen Wang
a1f3800a9d arm_gicv2_dump: optimize gic dump
1. Add config CONFIG_ARMV7A_GICv2_DUMP to control gic dump,
because irqinfo introduce too much other log;
2. Change the log api from irqinfo() to syslog(), syslog not
append the function name in the log, so the gic dump format
will not be destoried.

Signed-off-by: Bowen Wang <wangbowen6@xiaomi.com>
2024-10-11 19:56:41 +08:00
liwenxiang1
9eb7665822 arch/x86_64:Change extern g_intstackalloc to g_isrstackalloc
Signed-off-by: liwenxiang1 <liwenxiang1@xiaomi.com>
2024-10-11 19:55:50 +08:00
wangyongrong
933e066118 common/Toolchain.defs: support CONFIG_DEBUG_NOOPT for x86_64
Signed-off-by: wangyongrong <wangyongrong@xiaomi.com>
2024-10-11 17:21:06 +08:00
Bowen Wang
20db146b64 x86/x86_64: change the build result from nuttx.elf to nuttx
Just sync with other architecture.

Signed-off-by: Bowen Wang <wangbowen6@xiaomi.com>
2024-10-11 17:20:15 +08:00
lipengfei28
631b551727 goldfish add gicv2m support
Signed-off-by: lipengfei28 <lipengfei28@xiaomi.com>
2024-10-11 17:06:16 +08:00
lipengfei28
78a6ba6d5f PFU: do not cause execution of any instructions to be trapped
Signed-off-by: lipengfei28 <lipengfei28@xiaomi.com>
2024-10-11 17:04:28 +08:00
Bowen Wang
313d6df787 include/nuttx.h: replace all the align macros to nuttx version
1. add IS_ALIGNED()  definitions for NuttX;
2. replace all the ALIGN_UP() and ALIGN_DOWN() to use common
   align implementation;

Signed-off-by: Bowen Wang <wangbowen6@xiaomi.com>
2024-10-11 16:55:43 +08:00
ouyangxiangzhen
0936c97d3e arch/x86_64: Fix SMP startup for ACRN Hypervisor
This patch fixed SMP startup for ACRN Hypervisor.

Signed-off-by: ouyangxiangzhen <ouyangxiangzhen@xiaomi.com>
2024-10-11 15:43:01 +08:00
liwenxiang1
9189800760 arch/x86_64:Add configuration to disable vectorization optimization
With aggresive optimization enabled (-O3), ostest FPU test will fail.This is because the compiler will generate additional vector instructions between subsequent up_fpucmp() calls (loop vectorization somewhere in usleep() call), which will consequently overwrite the expected FPU context (XMM registers).The compilation option -fno-tree-vectorize can avoid this issue.

Signed-off-by: liwenxiang1 <liwenxiang1@xiaomi.com>
2024-10-11 15:40:55 +08:00
andi6
19e34b7f6e x64: modify addr limit to support 64 bits addr backtrace
Signed-off-by: andi6 <andi6@xiaomi.com>
2024-10-11 15:32:28 +08:00
cuiziwei
5e96e72cb6 X86_64: Add libcxx availability macros.
Signed-off-by: cuiziwei <cuiziwei@xiaomi.com>
2024-10-11 13:53:10 +08:00
cuiziwei
1816d752af arch/x86_64:Fix build cxx warning.
Signed-off-by: cuiziwei <cuiziwei@xiaomi.com>
2024-10-11 13:46:27 +08:00
lipengfei28
274ca2ea65 arch: arm64: Fix ARM64_CONTEXT_REGS number
This commit fixes the regression in https://github.com/apache/nuttx/pull/14063

Signed-off-by: lipengfei28 <lipengfei28@xiaomi.com>
2024-10-11 13:26:54 +08:00
anjiahao
5076b0c74c risc-v:Unify module compilation options
Signed-off-by: anjiahao <anjiahao@xiaomi.com>
2024-10-11 11:20:45 +08:00
yinshengkai
211a56910a syslog: support syslog redirection to sched_note
Signed-off-by: yinshengkai <yinshengkai@xiaomi.com>
2024-10-11 01:30:11 +08:00
Xu Xingliang
f68d594420 arch/arm64: rename register names to align with arm32
Signed-off-by: Xu Xingliang <xuxingliang@xiaomi.com>
Signed-off-by: lipengfei28 <lipengfei28@xiaomi.com>
2024-10-11 01:17:24 +08:00
wangmingrong1
ec3c27df0d makefile/clang: Compare versions for upward compatibility
Signed-off-by: wangmingrong1 <wangmingrong1@xiaomi.com>
2024-10-11 00:45:39 +08:00
yinshengkai
02eb280302 arch/perf: modify the return value of up_perf_gettime to clock_t
When using alarm_arch implementation, 64-bit time can be returned. Using unsign long will cause precision loss.

Signed-off-by: yinshengkai <yinshengkai@xiaomi.com>
2024-10-10 23:17:14 +08:00
p-szafonimateusz
ed71aa810e arch/x86_64/intel64/intel64_irq.c: fix busy irq logic
use correct macro for cpu_set_t busy variable and remove obsolote check

also remove not needed #include <sched.h> and "Public data"

Signed-off-by: p-szafonimateusz <p-szafonimateusz@xiaomi.com>
2024-10-10 22:57:04 +08:00
yinshengkai
8abbd3cde5 nuttx-names.in: add feof
When running gcov in sim, nuttx feof is called and causes crash

Signed-off-by: yinshengkai <yinshengkai@xiaomi.com>
2024-10-10 22:55:04 +08:00
liwenxiang1
fee7e0ce81 arch/x86_64:Add macros related to CPUID
Signed-off-by: liwenxiang1 <liwenxiang1@xiaomi.com>
2024-10-10 15:07:45 +02:00
ouyangxiangzhen
d0779e0eef arch/x86_64: Fix up_timer compilation error
This commit fix up_timer compilation error.

Signed-off-by: ouyangxiangzhen <ouyangxiangzhen@xiaomi.com>
2024-10-10 15:07:22 +02:00
ouyangxiangzhen
e6548ead20 arch/x86_64: Fix up_timer_start
Fix according to up_alarm_start.

Signed-off-by: ouyangxiangzhen <ouyangxiangzhen@xiaomi.com>
2024-10-10 15:07:22 +02:00
yinshengkai
d375a09c0a libs: add gprof arm64 support
Signed-off-by: yinshengkai <yinshengkai@xiaomi.com>
2024-10-10 18:46:51 +08:00
yinshengkai
eb8449cb0c sched/gprof: add gprof support
gprof can analyze code hot spots based on scheduled sampling.
After adding the "-pg" parameter when compiling, you can view the code call graph.

Signed-off-by: yinshengkai <yinshengkai@xiaomi.com>
2024-10-10 18:46:51 +08:00
Eren Terzioglu
f774afb4d9 esp32[s3|s2]: Add temperature sensor thread support 2024-10-10 18:45:01 +08:00
Eren Terzioglu
7556614732 esp32[c3|c6|h2]: Add temperature sensor thread support 2024-10-10 18:45:01 +08:00
Eren Terzioglu
4060f6ba80 esp32[s2|s3]: Add UORB support for internal temperature sensor 2024-10-10 18:45:01 +08:00
Eren Terzioglu
929f9ccfa2 esp32[c3|c6|h2]: Add UORB support for internal temperature sensor 2024-10-10 18:45:01 +08:00
hujun5
7216d566a6 sim: only POSIX implementation (ARCH_HAVE_MULTICPU) is provided
This commit fixes the regression from https://github.com/apache/nuttx/pull/13886

Signed-off-by: hujun5 <hujun5@xiaomi.com>
2024-10-10 18:38:25 +08:00
liwenxiang1
24f54ba712 arch/x86_64: cache convert all asm() to __asm__()
asm() is not supported by -std=c99, __asm__() is more portable

Signed-off-by: liwenxiang1 <liwenxiang1@xiaomi.com>
2024-10-10 18:36:09 +08:00
andi6
2ed88f8813 x64: add acrn ioapic init support
if we two step to set interrupt trigger and disable interrupt,
acrn will inject #GP exception

Signed-off-by: andi6 <andi6@xiaomi.com>
2024-10-10 17:49:40 +08:00
liwenxiang1
8d2fc5c9ee arch/x86_64:Add nanosecond delay interface to TSC
Signed-off-by: liwenxiang1 <liwenxiang1@xiaomi.com>
2024-10-10 17:13:01 +08:00
cuiziwei
f86644141b x86_64:Fix ld error.
LD: nuttx.elf
ld:in function `std::__1::ios_base::imbue(std::__1::locale const&)':
nuttx/libs/libxx/libcxx/src/ios.cpp:129: undefined reference to `_Unwind_Resume'

Signed-off-by: cuiziwei <cuiziwei@xiaomi.com>
2024-10-10 16:51:38 +08:00
wangming9
1c2856dfcb arch/arm64: Fixed up_getusrsp getting stack Pointers
Signed-off-by: wangming9 <wangming9@xiaomi.com>
Signed-off-by: lipengfei28 <lipengfei28@xiaomi.com>
2024-10-10 15:40:03 +08:00
wangming9
b0ea6840e1 arch/arm64: Use serr to print fatal error messages.
Summary:
sinfo cannot print fatal error messages when CONFIG_DEBUG_SCHED_INFO is turned off.

Signed-off-by: wangming9 <wangming9@xiaomi.com>
2024-10-10 15:40:03 +08:00
wangming9
27d77b1aca arch/arm64: Fixed GIC3 for goldfish platform
Signed-off-by: wangming9 <wangming9@xiaomi.com>
2024-10-10 15:40:03 +08:00
wangming9
b3e640cf3f arch/arm64: GICv2 detection is compatible with different qemu versions
Summary:
- GICv2 cannot be detected on the golsfish platform
- Golsfish uses version 2.12.0 of qemu with a GICC_IIDR value of 0,
  read ICPIDR2 to determine the GIC version

Signed-off-by: wangming9 <wangming9@xiaomi.com>
2024-10-10 15:40:03 +08:00
Bowen Wang
a847ee1675 qmeu_boot: add rpmsg syslog init for arm64 qemu chip
Signed-off-by: Bowen Wang <wangbowen6@xiaomi.com>
2024-10-10 15:40:03 +08:00
wangming9
e48b81ebe9 arch/arm64: Supports cluster PMU
Summary:
Some processors implement cluster PMUs, such as Cortex-R82.

Signed-off-by: wangming9 <wangming9@xiaomi.com>
2024-10-10 15:40:03 +08:00
wangming9
fa96350574 arch/arm64: Modify the method for obtaining the CPU frequency
Summary:
1、cntfrq_el0 is used to store the timer frequency, which may
   be different from the CPU frequency.
2、Do not use up_perf interface for SMP.

Signed-off-by: wangming9 <wangming9@xiaomi.com>
2024-10-10 15:40:03 +08:00
yangguangcai
e9b77833e3 goldfish:config pl031.
Signed-off-by: yangguangcai <yangguangcai@xiaomi.com>
2024-10-10 15:40:03 +08:00
liwenxiang1
f858026819 arch/x86_64:Add allsymbol functionality
Signed-off-by: liwenxiang1 <liwenxiang1@xiaomi.com>
2024-10-10 14:56:08 +08:00
Huang Qi
20cba94a86 risc-v/espressif: Fix alert message in esp_setup_irq()
Correct the alert message in `esp_setup_irq()` if
irq number allocation fails, the parameter number is not
matched with format specifier.

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2024-10-10 13:41:34 +08:00
liwenxiang1
e3b3a6145a arch/x86_64: idle convert all asm() to __asm__()
Signed-off-by: liwenxiang1 <liwenxiang1@xiaomi.com>
2024-10-10 13:40:39 +08:00
liwenxiang1
1af831e139 arch/x86_64: cpuid expect 32 bit variables
Signed-off-by: liwenxiang1 <liwenxiang1@xiaomi.com>
2024-10-10 12:03:27 +08:00
liwenxiang1
2448e8a59e arch/x86_64:Add perf tool
Signed-off-by: liwenxiang1 <liwenxiang1@xiaomi.com>
2024-10-10 12:01:16 +08:00
liwenxiang1
f81c7dbc93 arch/x86_64:Use the checkstack function
Signed-off-by: liwenxiang1 <liwenxiang1@xiaomi.com>
2024-10-10 11:40:15 +08:00
hujun5
e249dd2672 arch: support customized up_cpu_index() in AMP mode
Some app with same code runs on different cores in AMP mode,
need the physical core on which the function is called.

Signed-off-by: hujun5 <hujun5@xiaomi.com>
Signed-off-by: fangxinyong <fangxinyong@xiaomi.com>
2024-10-10 02:38:40 +08:00
ligd
ff99745b22 arm-m: support zero interrupt back to game
Signed-off-by: ligd <liguiding1@xiaomi.com>
2024-10-10 01:01:17 +08:00
ligd
a9da6ab4b5 arm-M: set current regs for crash dump
Signed-off-by: ligd <liguiding1@xiaomi.com>
2024-10-10 01:01:17 +08:00
ligd
780acd7827 armv6/7/8m: use pendsv to handle context switch
This PR support Nested interrupt in armv6/7/8m:

There are two types of nested interrupt model:

Zero latency nested interrupt
Interrupt           Priority            Note
Data abort          Highest
SVC                 0x50
High irq1           0x60             ISR can't access system API
irq_save()          0x70
High irq2           0x80             ISR can't access system API
normal irq3         0xB0
We have already support this mode before this PR

Nested interrupt which interrupt level lower than up_irq_save()
Interrupt           Priority            Note
Data abort          Highest
SVC                 0x70
irq_save()          0x80
High irq1           0x90              ISR can access system API
High irq2           0xA0              ISR can access system API
normal irq3         0xB0
Now, this PR can support this mode

Signed-off-by: ligd <liguiding1@xiaomi.com>
2024-10-10 01:01:17 +08:00
ligd
f221c9ecb4 armv6m: add up_trigger_irq() support
Signed-off-by: ligd <liguiding1@xiaomi.com>
2024-10-10 01:01:17 +08:00
ligd
f20ae064b0 armv7/8m: unmask all the IRQ when thread start
NVIC_SYSH_PRIORITY_MIN not the basepri loweest prio
spec says:
basepri 0 - Disables masking by BASEPRI

Signed-off-by: ligd <liguiding1@xiaomi.com>
2024-10-10 01:01:17 +08:00
liwenxiang1
4c19e75ff5 libs/x86_64:Add the setjmp/longjmp function
Signed-off-by: liwenxiang1 <liwenxiang1@xiaomi.com>
2024-10-09 22:24:03 +08:00
wangmingrong1
47fc3a67f7 sim/kconfig: delete non-existent dependencie
Signed-off-by: wangmingrong1 <wangmingrong1@xiaomi.com>
2024-10-09 21:27:47 +08:00
yinshengkai
034af29aab arch: adjust gcov configuration name
Signed-off-by: yinshengkai <yinshengkai@xiaomi.com>
2024-10-09 21:27:47 +08:00
liwenxiang1
8fe6c0ee8e arch/x86_64: Map the new page table with read-write permissions
Signed-off-by: liwenxiang1 <liwenxiang1@xiaomi.com>
2024-10-09 20:51:58 +08:00
Filipe Cavalcanti
42b7097cc2 xtensa/esp32s3: fix missing peripheral initialization for watchdog timer 2024-10-09 20:49:48 +08:00
liwenxiang1
eb411101c5 arch/x86_64:Configure arch delay using CONFIG_ALARM_ARCH
Signed-off-by: liwenxiang1 <liwenxiang1@xiaomi.com>
2024-10-09 20:49:19 +08:00
ligd
784937a03c arm64: fix backtrace failed
Signed-off-by: ligd <liguiding1@xiaomi.com>
2024-10-09 20:47:43 +08:00
Bowen Wang
f172f222be arm64_checkstack: fix crash, optimize the stack color, sync with arm
Signed-off-by: Bowen Wang <wangbowen6@xiaomi.com>
Signed-off-by: ligd <liguiding1@xiaomi.com>
2024-10-09 20:47:43 +08:00
wangming9
3054b1ad51 arch/arm64: Fixed arm64_cache_get_info obtaining cache.
Summary:
Select icache or dcache by setting register csselr_el1.

Signed-off-by: wangming9 <wangming9@xiaomi.com>
Signed-off-by: ligd <liguiding1@xiaomi.com>
2024-10-09 20:47:43 +08:00
wangming9
cb62c783a9 arch/arm64: Add the interface for icache and dcache.
Summary:
Add up_get_icache_size、up_invalidate_icache、up_get_dcache_size

Signed-off-by: wangming9 <wangming9@xiaomi.com>
Signed-off-by: ligd <liguiding1@xiaomi.com>
2024-10-09 20:47:43 +08:00
wangmingrong1
0866010101 arm64/makefile: No longer using hwasan pile insertion
Signed-off-by: wangmingrong1 <wangmingrong1@xiaomi.com>
2024-10-09 18:15:13 +08:00
ligd
26dc3b297a arm64: exclude mpu from sanitize for SMP mode
CPU0 boot -> mm_init() -> sannitize on -> boot other CPUs
CPU1 boot -> mpu_init -> error

Signed-off-by: ligd <liguiding1@xiaomi.com>
2024-10-09 18:15:13 +08:00
ligd
e9617583bc arm64-r/mpu: add TBI setting to r82 when use SW_TAG
Signed-off-by: ligd <liguiding1@xiaomi.com>
2024-10-09 18:15:13 +08:00
yinshengkai
73d9a1b4a2 sim: disable sim uart output processing
Using the host serial port to send data in sim will convert \r to \r\n

Signed-off-by: yinshengkai <yinshengkai@xiaomi.com>
2024-10-09 18:13:46 +08:00
raiden00pl
e419d2c392 arch/arm/Kconfig: fix copy-paste error
ARCH_CHIP_CSK6 has nothing to do with ST chips:
fix option string and move below ST related options
2024-10-09 18:11:20 +08:00
liwenxiang1
8b86f5de60 arch/x86_64: add support for thread_local
Signed-off-by: liwenxiang1 <liwenxiang1@xiaomi.com>
2024-10-09 17:58:01 +08:00
liwenxiang1
5e15fff58a arch/x68_64: properly align ap boot stack for vector operations
Signed-off-by: liwenxiang1 <liwenxiang1@xiaomi.com>
2024-10-09 17:40:37 +08:00
liwenxiang1
b4c4cbc28b arch/x86_64: Resolve weak symbol compilation relocation errors
Signed-off-by: liwenxiang1 <liwenxiang1@xiaomi.com>
2024-10-09 17:39:42 +08:00
lipengfei28
56495bc9ce The gicv2m spinlock init status should unlocked
Signed-off-by: lipengfei28 <lipengfei28@xiaomi.com>
2024-10-09 15:07:37 +08:00
hujun5
17ca45e8a3 sim: fix sim smp boot regression
This commit fixes the regression from https://github.com/apache/nuttx/pull/13716

Signed-off-by: hujun5 <hujun5@xiaomi.com>
2024-10-09 12:33:21 +08:00
Xiang Xiao
b068e2357a circbuf: Move from mm/circbuf to libs/libc/misc
so that it can be used by userspace program.

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
Signed-off-by: Neo Xu <neo.xu1990@gmail.com>
2024-10-09 08:41:49 +08:00
chenzhijia
a443a37390 drivers/coresight:ETM4 setup
Signed-off-by: chenzhijia <chenzhijia@xiaomi.com>
2024-10-09 08:37:48 +08:00
ligd
6dc08ee681 pci: fix compile failed, fdt_get_reg_base() need 3 args
goldfish: fix compile failed, fdt_get_irq_by_path() need 4 args

Signed-off-by: ligd <liguiding1@xiaomi.com>
2024-10-09 02:18:49 +08:00
liwenxiang1
cd03ec3266 arch/x86_64:Add check stack function
Signed-off-by: liwenxiang1 <liwenxiang1@xiaomi.com>
2024-10-09 01:53:09 +08:00
liwenxiang1
afe1cc59b6 arch/x86_64: Add vfork support
Signed-off-by: liwenxiang1 <liwenxiang1@xiaomi.com>
2024-10-09 01:41:35 +08:00
anjiahao
9ed93c6b1e unify MODULE & ELF flag to Toolchain.defs
Signed-off-by: anjiahao <anjiahao@xiaomi.com>
2024-10-08 19:56:33 +08:00
Ville Juven
e5aef873a2 riscv_internal.h: Remove riscv_sbi.h from the file
riscv_internal.h is used literally everywhere, while the SBI definitions
are needed only by whomever needs the services.

Having the SBI definitions:
a) Copied from OpenSBI (why has this been done? even the names are same)
b) Presented publicly to 99% of risc-v modules

creates a build error when building with OpenSBI, due to duplicate
definitions of the SBI service identifiers:

In file included from /nuttx/arch/risc-v/src/common/riscv_internal.h:40,
                 from /nuttx/arch/risc-v/src/chip/chip.h:32,
                 from board/mpfs_domain.c:30:
/nuttx/arch/risc-v/src/common/riscv_sbi.h:36: error: "SBI_EXT_BASE" redefined [-Werror]
   36 | #define SBI_EXT_BASE            0x00000010

and so forth...

Fix this by removing riscv_sbi.h i.e. not exposing the ABI publicly.
2024-10-08 19:55:53 +08:00
yinshengkai
f26ae83900 arch/irq: add the up_getusrpc macro to get the PC of the interrupted thread in the interrupt
Signed-off-by: yinshengkai <yinshengkai@xiaomi.com>
Signed-off-by: ligd <liguiding1@xiaomi.com>
2024-10-08 19:55:28 +08:00
hujun5
99b364c880 x86_64: fix regression
This commit fixes the regression from https://github.com/apache/nuttx/pull/13768

Signed-off-by: hujun5 <hujun5@xiaomi.com>
2024-10-08 15:27:57 +08:00
buxiasen
a6b12eb29c goldfinsh: fix timer compile issue
Signed-off-by: buxiasen <buxiasen@xiaomi.com>
2024-10-08 15:27:33 +08:00
ligd
e7094ec40a goldfish: use goldfish timer
Signed-off-by: ligd <liguiding1@xiaomi.com>
2024-10-08 15:27:33 +08:00
buxiasen
0b3859521a arch: fix the sched parameter update when exiting
Signed-off-by: buxiasen <buxiasen@xiaomi.com>
2024-10-08 13:53:06 +08:00
xuxingliang
33a8760a14 arch/sim: fix uart could lose log
Need to loop to write untill all data written or error happened

Signed-off-by: xuxingliang <xuxingliang@xiaomi.com>
2024-10-08 08:57:28 +08:00
Xiang Xiao
904bb7a6ea arch/sim: dataheap should disable exec permission
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2024-10-08 08:57:28 +08:00
yinshengkai
bdcc325e1f sim/gcov: Fix conflicts between fprofile-orderate and __asan_default_options
Signed-off-by: yinshengkai <yinshengkai@xiaomi.com>
2024-10-08 08:57:28 +08:00
yinshengkai
acca2430a9 Revert "arch/sim: suppress libasan checks"
This reverts commit 53ddc3ef7f

Signed-off-by: yinshengkai <yinshengkai@xiaomi.com>
Signed-off-by: ligd <liguiding1@xiaomi.com>
2024-10-08 08:57:28 +08:00
ligd
a3568af105 sim: fix context-switch when do wdog callback()
Signed-off-by: ligd <liguiding1@xiaomi.com>
2024-10-08 08:57:28 +08:00
ligd
ba3a55b445 cache: do cache_invalidate_all before enable dcache
Signed-off-by: ligd <liguiding1@xiaomi.com>
2024-10-08 08:15:41 +08:00
raiden00pl
c1c5d8d611 arch/arm/stm32{|f7}/socketcan: fix debugassert for extid frames
fix debugassert for extid frames, we have to remove
CAN_EFF_FLAG bit from the expression
2024-10-08 08:14:07 +08:00
hujun5
31a3cea64a arch: rename xxxx_pause.c to xxxx_smpcall.c
Signed-off-by: hujun5 <hujun5@xiaomi.com>
2024-10-08 08:13:22 +08:00
hujun5
d8cb7759b6 arch: remove up_cpu_pause up_cpu_resume up_cpu_paused up_cpu_pausereq
reason:
  To remove the "sync pause" and decouple the critical section from the dependency on enabling interrupts,
  after that we need to further implement "schedlock + spinlock".
changelist
  1 Modify the implementation of critical sections to no longer involve enabling interrupts or handling synchronous pause events.
  2 GIC_SMP_CPUCALL attach to pause handler to remove arch interface up_cpu_paused_restore up_cpu_paused_save
  3 Completely remove up_cpu_pause, up_cpu_resume, up_cpu_paused, and up_cpu_pausereq
  4 change up_cpu_pause_async to up_send_cpu_sgi

Signed-off-by: hujun5 <hujun5@xiaomi.com>
2024-10-08 08:13:22 +08:00
hujun5
fc22fb8f53 xtensa: Replace the implementation of up_cpu_pause
Signed-off-by: hujun5 <hujun5@xiaomi.com>
2024-10-08 08:13:22 +08:00
ligd
b3727f67be esp32: fix esp32 wifi bug caused scan failed
tools/configure.sh esp32c3-generic:wifi
wapi scan wlan0
has no return result after couple times

rootcause:
mq_timedsend() return failed because the time valid check error.
the ts_nsec is bigger than 1000000000.
esp_update_time() hasn't consider of the ns > 1s after the adding
calculation

Signed-off-by: ligd <liguiding1@xiaomi.com>
2024-10-07 20:21:45 +08:00
SPRESENSE
9bfc426321 arch: cxd56xx: Add SD card 4-bit capability
The mmcsd driver has been updated to require SDIO_CAPS_4BIT to be
explicitly specified for SD card 4-bit support.
2024-10-07 17:35:19 +08:00
xuxingliang
18d5ae20f5 drivers/segger: add heap data plot
Add heap current used to note.
Plot it in segger sysview data plot.

Signed-off-by: xuxingliang <xuxingliang@xiaomi.com>
Signed-off-by: Neo Xu <neo.xu1990@gmail.com>
2024-10-07 17:34:59 +08:00
xuxingliang
eac6a8597f sched/note: add note when mm add new region
Signed-off-by: xuxingliang <xuxingliang@xiaomi.com>
Signed-off-by: Neo Xu <neo.xu1990@gmail.com>
2024-10-07 17:34:59 +08:00
xuxingliang
0663ac1483 sched/note: specify note event for heap instrumentation
1. Add NOTE_HEAP_ prefix for heap note event.
2. Use note type as heap instrumentation parameter.

Signed-off-by: xuxingliang <xuxingliang@xiaomi.com>
Signed-off-by: Neo Xu <neo.xu1990@gmail.com>
2024-10-07 17:34:59 +08:00
yinshengkai
79eab8783f note: add memory tracing event support
Record all memory allocation and release, save to ram, used to analyze memory allocation rate and memory usage
Its absolute value is not trustworthy because the memory will be allocated in thread A and released in thread B

 netinit-5   [0]   0.105984392: tracing_mark_write: C|5|Heap Usage|96|free: heap: 0x606000000020 size:24, address: 0x603000000370
 netinit-5   [0]   0.105996874: tracing_mark_write: C|5|Heap Usage|24|free: heap: 0x606000000020 size:72, address: 0x6070000008e0
nsh_main-4   [0]   3.825169408: tracing_mark_write: C|4|Heap Usage|2177665|free: heap: 0x606000000020 size:424, address: 0x614000000840
nsh_main-4   [0]   3.825228525: tracing_mark_write: C|4|Heap Usage|14977|free: heap: 0x606000000020 size:2162688, address: 0x7f80a639f800
nsh_main-4   [0]   3.825298789: tracing_mark_write: C|4|Heap Usage|15189|malloc: heap: 0x606000000020 size:20, address: 0x6030000003a0

Signed-off-by: yinshengkai <yinshengkai@xiaomi.com>
Signed-off-by: Neo Xu <neo.xu1990@gmail.com>
2024-10-07 17:34:59 +08:00
lijianjun
9762ddee6e add mm_uninitialize empty implementation for sim
Signed-off-by: lijianjun <lijianjun@xiaomi.com>
Signed-off-by: Neo Xu <neo.xu1990@gmail.com>
2024-10-07 17:34:59 +08:00
buxiasen
b444bf2e6a goldfish: fix sched api update missed godlfish_cpuboot
add cmake support

Signed-off-by: buxiasen <buxiasen@xiaomi.com>
2024-10-07 17:33:14 +08:00
buxiasen
5bf7d0e4a7 goldfish: boot add missing header when CONFIG_SCHED_INSTRUMENTATION
Signed-off-by: buxiasen <buxiasen@xiaomi.com>
Signed-off-by: ligd <liguiding1@xiaomi.com>
2024-10-07 17:33:14 +08:00
wangmingrong1
3e66cc30d0 arch/qemu: up_perf_init depends on CONFIG_ARCH_PERF_EVENTS
Signed-off-by: wangmingrong1 <wangmingrong1@xiaomi.com>
Signed-off-by: ligd <liguiding1@xiaomi.com>
2024-10-07 17:33:14 +08:00
hujun5
0ed47c5f7e qemu: fix smp boot not enter idle
Signed-off-by: hujun5 <hujun5@xiaomi.com>
Signed-off-by: ligd <liguiding1@xiaomi.com>
2024-10-07 17:33:14 +08:00
Bowen Wang
a952e9ca78 arm/qemu_boot: fix the rpmsg syslog init warning
chip/qemu_boot.c:84:3: warning: implicit declaration of function 'syslog_rpmsg_init_early' [-Wimplicit-function-declaration]
   84 |   syslog_rpmsg_init_early(g_syslog_rpmsg_buf, sizeof(g_syslog_rpmsg_buf));
      |   ^~~~~~~~~~~~~~~~~~~~~~~

Signed-off-by: Bowen Wang <wangbowen6@xiaomi.com>
Signed-off-by: ligd <liguiding1@xiaomi.com>
2024-10-07 17:33:14 +08:00
Bowen Wang
9e76bc610f arm/qemu_boot: add rpmsg syslog support for qemu armv7a
Signed-off-by: Bowen Wang <wangbowen6@xiaomi.com>
Signed-off-by: ligd <liguiding1@xiaomi.com>
2024-10-07 17:33:14 +08:00
wangming9
00857c7fd9 arm/qemu: The PSCI can be configured with CONFIG_ARM_PSCI
Signed-off-by: wangming9 <wangming9@xiaomi.com>
Signed-off-by: ligd <liguiding1@xiaomi.com>
2024-10-07 17:33:14 +08:00
ligd
4818707870 glodfish: add SMP boot support
Signed-off-by: ligd <liguiding1@xiaomi.com>
2024-10-07 17:33:14 +08:00
ligd
d1bcc1f504 qemu: simply SMP boot
Signed-off-by: ligd <liguiding1@xiaomi.com>
2024-10-07 17:33:14 +08:00
hujun5
f12996c851 sched: replace sync pause with async pause for nxsig_process
Signed-off-by: hujun5 <hujun5@xiaomi.com>
2024-10-07 13:32:57 +08:00
hujun5
f132ed2edb signal: adjust the signal processing logic to remove the judgment
Signed-off-by: hujun5 <hujun5@xiaomi.com>
2024-10-07 13:32:57 +08:00
hujun5
7eea4223ee arch: move sigdeliver to common code
Signed-off-by: hujun5 <hujun5@xiaomi.com>
2024-10-07 13:32:57 +08:00
buxiasen
a569eef6ba arch: cpu pause when sigaction only necessary if tcb running
Signed-off-by: buxiasen <buxiasen@xiaomi.com>
2024-10-07 13:32:57 +08:00
Kyle Wilson
ac15155fc9 Enable LPUART functionality for the STM32G4 series.
1. Kconfig - Removed USART1 config option from STM32_STM32G47XX. Not necessary to adding LPUART functionality. 2. stm32_lowput.c - Added extra check from STM32G4 board because that is the only with LPUART functionality. 2. stm32_serial.c - Removed unneeded function (stm32_serial_get_lpuart). Fixed up_putc return bug. Added configuration for DMAMAP_LPUART RX and TX for STM32G4XXX only. The G4 is the only in this family with LPUART and uses a DMAMUX unlike the others.

1. Removed 1WIRE LPUART refereences in Kconfig and stm32_uart.h. There is no support for LPUART currently in stm32_1wire.c. 2. Removed references to LPUART under DMA_V2 ifdefs. STM32G4 uses DMA_V1, and I saw that none of the chips DMA_V2 (F20, F4) have LPUARTs. AFAIK the only chip in the stm32 folder that has LPUART peripherals is the STM32G4.

Removed unnecessary brackets and empty lines

Added lpuartnsh (LPUART NuttShell) config to the nucleo-g474re board configurations. nsh uses USART3 by default. lpuartnsh uses nsh as a template, changes the serial console to LPUART1, and adds the DMA configs to enable DMA for the LPUART.

Added support for using the lpuart prescaler register. Without prescaling the apbclock, 9600 baud is not supported on the G474RE. By utilizing the prescaler, when necessary, we can support nearly any baud rate (300 baud to 30M Mbaud). lowputc defaults to a prescaler of 16 for the lpuart so standard baud rates (9600 to 115200) are supported early in the boot process. Later in stm32_serial.c the ideal prescaler and BRR values are determined.

Added ifdef statements for LPUART code sections not compatible with other chips.

Changed LPUART BRR calcuation to use 64-bit integers.

Feedback from nuttx pull request. Added brackets around single line if/else statements. Reordered lpuartnsh defconfig file.

Fix lpuart brr calculation after attempting to break the calculation into 2 lines.

Removed TAB
2024-10-07 04:14:59 +08:00
Xiang Xiao
7c839d7a09 rptun: Remove include/nuttx/rptun/openamp.h
and use include/nuttx/rpmsg/rpmsg.h instead

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2024-10-07 00:44:28 +08:00
hujun5
eae57cb0e6 sched: replace sync pause with async pause for nxtask_terminate
reason:
In the kernel, we are planning to remove all occurrences of up_cpu_pause as one of the steps to
simplify the implementation of critical sections. The goal is to enable spin_lock_irqsave to encapsulate critical sections,
thereby facilitating the replacement of critical sections(big lock) with smaller spin_lock_irqsave(small lock)

Signed-off-by: hujun5 <hujun5@xiaomi.com>
2024-10-06 09:26:56 +08:00
raiden00pl
bcf309d80e arch/arm/nrf{52|53|91}: fix max timer timeout
fix prerpocessor value of max timer timeout
2024-10-06 08:39:12 +08:00
raiden00pl
65a3b5f524 arch/arm/nrf{52|53|91}: fix read GPIO state for outputs
when GPIO is configured as output, we have to read output
state instead of input register
2024-10-05 23:40:34 +08:00
cuiziwei
6373931cf1 nuttx/arch: Fix the issue where the compiler cannot recognize min-pagesize=0.
Signed-off-by: cuiziwei <cuiziwei@xiaomi.com>
2024-10-05 08:45:08 +08:00
Ville Juven
0976258299 riscv/kstack: Remove riscv_current_ksp as obsolete
Unwinding the kernel stack did not work previously due to the way the task
startup logic works via nxtask_start and the up_task_start() system call.

After modifying the logic behind those, the kernel stack is in fact fully
unwound when return_from_exception is executed, so calling the original
hack "riscv_current_ksp" is not necessary anymore.
2024-10-04 08:33:34 +08:00
Ville Juven
190a2e306c riscv/syscall: Simplify task/pthread_start logic
This removes 2 reserved system calls and replaces them with an ASM snippet.
The result removes an unnecessary ecall from the process startup logic, as
well as ensures the stacks are FULLY unwound when the user process starts.

The logic is ported from ARM64.
2024-10-04 08:33:34 +08:00
Ville Juven
e9f96105dd risc-v/syscall: Simplify dispatch_syscall for RISC-V
Port the simplification from ARM64, this removes the ugly inline assembly
trampoline "do_syscall" and replaces it with a simple table lookup and
call via function pointer.
2024-10-04 08:33:34 +08:00
chenxiaoyi
56bcbcc6b0 sim: change the type of xcpt_reg_t
Signed-off-by: chenxiaoyi <chenxiaoyi@xiaomi.com>
2024-10-04 08:21:35 +08:00
chenxiaoyi
f6fc4cdded sim/irq: fix windows64 build error
nuttx\vs2022\include\arch\irq.h(144,9): error C2065: 'mov': undeclared identifier

Signed-off-by: chenxiaoyi <chenxiaoyi@xiaomi.com>
2024-10-04 08:21:35 +08:00
chenxiaoyi
43de53c93f sim/types: fix windows64 build error
nuttx\include\sys\types.h(133,22): error C2371: 'size_t': redefinition; different basic types

Signed-off-by: chenxiaoyi <chenxiaoyi@xiaomi.com>
2024-10-04 08:21:35 +08:00
p-szafonimateusz
ce61347ddf arch/x86_64/intel64/intel64_schedulesigaction.c: properly align signal handler stack for vector operations
signal handler stack must be properly aligned, otherwise vector instructions doesn't work in signal handler

Signed-off-by: p-szafonimateusz <p-szafonimateusz@xiaomi.com>
2024-10-03 21:07:19 +08:00
p-szafonimateusz
ed4acb20cc arch/x86_64/intel64/intel64_cpuidlestack.c: stack_alloc should point to stack base not stack top
stack_alloc should point to stack base not stack top

Signed-off-by: p-szafonimateusz <p-szafonimateusz@xiaomi.com>
2024-10-03 21:07:19 +08:00
p-szafonimateusz
6b8d0c6a16 arch/x86_64/intel64/intel64_head.S: move initial RSP for AP cores below regs area
move initial RSP for AP cores below regs area.
otherwise IDLE thread for AP cores can be corrupted

XCP region now match regs allocation in up_initial_state()

Signed-off-by: p-szafonimateusz <p-szafonimateusz@xiaomi.com>
2024-10-03 21:07:19 +08:00
p-szafonimateusz
026e1b4b5e arch/intel64: colorize IDLE stack for AP cores
colorize IDLE stack for AP cores in x86_64

Signed-off-by: p-szafonimateusz <p-szafonimateusz@xiaomi.com>
2024-10-03 21:07:11 +08:00
p-szafonimateusz
4a6e6563cb arch/x86_64/addrenv.h: fix MMU flags for USER region
fix typo in MMU flags for USER region

Signed-off-by: p-szafonimateusz <p-szafonimateusz@xiaomi.com>
2024-10-03 21:06:52 +08:00
p-szafonimateusz
b47839b9c2 arch/intel64: fix IRQ conflict with GOLDFISH
Also move MSI IRQ definition to place where other IRQ definitions are.

Signed-off-by: p-szafonimateusz <p-szafonimateusz@xiaomi.com>
2024-10-03 20:55:19 +08:00
p-szafonimateusz
76bfb994a7 arch/x86_64/src/intel64: use legacy method to map memory <4GB
the new mapping method may not work when we have to map memory at the early boot stage

Signed-off-by: p-szafonimateusz <p-szafonimateusz@xiaomi.com>
2024-10-03 20:54:59 +08:00
SPRESENSE
c38b4494be arch: cxd56xx: update loader and gnssfw version
Update loader and gnssfw to version 2.2.20596
2024-10-03 14:25:09 +08:00
SPRESENSE
cc6306a559 boards: cxd56xx: Fix an issue not to enter cold sleep
Fix an issue not to enter cold sleep by SD Card detection interrupt.
2024-10-03 14:24:55 +08:00
SPRESENSE
fb7c429504 arch: cxd56xx: Fix gnss compile error
Fix a compile error when CONFIG_CXD56_GNSS_CEP_ON_SPIFLASH is enabled.
2024-10-03 14:24:15 +08:00
Yongrong Wang
d0e4c4436e rpmsg_virtio: move rpmsg virtio cmd definition before the resource table
use reserved[2] in struct resource_table as the command, avoid the
resource table format do not follow the standard.

Signed-off-by: Yongrong Wang <wangyongrong@xiaomi.com>
2024-10-03 09:37:24 +08:00
Ville Juven
30aa947b95 arm64_fpu: Remove fpu_regs from the TCB
Since FPU is now always saved into the current process stack location
upon exception entry, there is no need to keep fpu_regs (or saved_fpu_regs)
in the TCB.
2024-10-03 09:08:26 +08:00
Jouni Ukkonen
9ea098558a arch/arm64/src/imx9/imx9_usbdev.c: Clean up cache operations, add DEBUGASSERTS
Correct some of the cache operations:

- EP0 request length was handled incorrectly
- Received data cache invalidate was exceeding the received buffer
- writedtd is also called with no data (EP0 ACK/NACK). Don't touch cache in that case.

Fix trip wire handling to conform with the IMX93 reference manual

Also add DEBUGASSERTS for future to check the validity of pointers and sizes

Co-authored-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
2024-10-03 08:55:13 +08:00
zhaohaiyang1
534114395e char driver CAN: add tx_confirm function in upperCAN driver.
add tx_confirm function in upperCAN driver1

Signed-off-by: zhaohaiyang1 <zhaohaiyang1@xiaomi.com>
2024-10-02 21:22:07 +08:00
Neo Xu
e2e0706009 espressif/spi: fix missing SPI setup
Signed-off-by: Neo Xu <neo.xu1990@gmail.com>
2024-10-02 21:17:38 +08:00
Neo Xu
3636495f39 espressif/spi: fix crash when rx buffer is NULL
Signed-off-by: Neo Xu <neo.xu1990@gmail.com>
2024-10-02 21:17:38 +08:00
guoshichao
415bd57c50 greenhills: fix the pow() function calculate error
Signed-off-by: guoshichao <guoshichao@xiaomi.com>
2024-10-02 21:16:03 +08:00
liaoao
0e2bf8ce2c assert:read content of undefinedinsn address
read content of undefinedinsn address, and compare it with what it is in elf  to check if there is a ram bit flip

Signed-off-by: liaoao <liaoao@xiaomi.com>
2024-10-02 21:15:26 +08:00
W-M-R
eb2f661170 make/kasan: Added cmake toolchain compilation options about kasan for arm64 architecture
Signed-off-by: W-M-R <Mike_0528@163.com>
2024-10-02 21:09:31 +08:00
W-M-R
5febd80efe cmake: add_compile_options recognizes parameter exception
add_compile_options(--param asan-globals=1) is recognized as
--param-lasan-globals=1, which causes compilation exception:

Signed-off-by: W-M-R <Mike_0528@163.com>
2024-10-02 21:09:31 +08:00
Ville Juven
24c931c220 arm64_task/pthread_start: Set sp_el0 upon starting user process
As the handling of sp_el0 was moved from the context switch routine
to exception entry/exit, we must set sp_el0 explicitly when the user
process is first started.
2024-10-02 14:09:22 +08:00
lipengfei28
8e200e69d4 Kernel build: enter exception save sp_sl0,exit exception restroe sp_el0
Signed-off-by: lipengfei28 <lipengfei28@xiaomi.com>
2024-10-02 14:09:22 +08:00
ligd
c3da7c29e8 arm64: simply the vectors
Signed-off-by: ligd <liguiding1@xiaomi.com>
2024-10-02 14:09:22 +08:00
ligd
007399dd75 arm64: save FPU regs every time
Signed-off-by: ligd <liguiding1@xiaomi.com>
2024-10-02 14:09:22 +08:00
xuxin19
18b6b72240 cmake:fix windows build break
-U_WIN32 will cause windows host source such as sim_hostirq.c hearder windows.h exception

Signed-off-by: xuxin19 <xuxin19@xiaomi.com>
2024-10-01 21:34:26 +08:00
xuxin19
b9dc9fb0fc cmake:refine SIM platform CMake Toolchain file
Signed-off-by: xuxin19 <xuxin19@xiaomi.com>
2024-10-01 21:34:26 +08:00
cuiziwei
394a967263 nuttx/arch: Remove GCCVER and add compilation options directly.
Signed-off-by: cuiziwei <cuiziwei@xiaomi.com>
2024-10-01 20:41:02 +08:00
xuxingliang
7044b10c88 task: use get_task_name where possible
Signed-off-by: xuxingliang <xuxingliang@xiaomi.com>
2024-10-01 20:38:06 +08:00
yangguangcai
62d7b3beeb arm-v7m systick:call irq_attach_thread.
Signed-off-by: yangguangcai <yangguangcai@xiaomi.com>
2024-10-01 12:26:07 +08:00
hujun5
c039ea77ba arm64: fix use arch-timer in SMP
reason:
only one timer will be effective at a time.

Signed-off-by: hujun5 <hujun5@xiaomi.com>
2024-10-01 12:10:06 +08:00
hujun5
ea29217442 arm64: fix tickless mode in SMP
Signed-off-by: hujun5 <hujun5@xiaomi.com>
2024-10-01 12:10:06 +08:00
xuxingliang
060ac93f82 arm64: allow to use custom up_timer_initialize
Signed-off-by: xuxingliang <xuxingliang@xiaomi.com>
2024-10-01 12:10:06 +08:00
guoshichao
ff4ad07576 greenhills: add cmake support
1. refactor the ghs/gcc/clang/armclang toolchain management in CMake
2. unify the cmake toolchain naming style
3. support greenhills build procedure with CMake
4. add protect build for greenhills and gnu toolchain with CMake

Signed-off-by: guoshichao <guoshichao@xiaomi.com>
2024-10-01 11:48:09 +08:00
hujun5
17b31d2037 xtensa: add parameters to xtensa_pause_handler
reason:
nxsched_smp_call_handler need these parameters

Signed-off-by: hujun5 <hujun5@xiaomi.com>
2024-10-01 11:45:56 +08:00
hujun5
0e87a475d3 x86_64: we should call x86_64_restorestate/x86_64_savestate
reason:
In x86_64, g_current_regs is still used for context switching.

This commit fixes the regression from https://github.com/apache/nuttx/pull/13616

Signed-off-by: hujun5 <hujun5@xiaomi.com>
2024-10-01 11:47:25 +09:00
Filipe Cavalcanti
8153307da5 espressif: remove static from spiflash operations 2024-09-30 20:42:00 +02:00
Filipe Cavalcanti
b3d0dca84e xtensa/esp32: fix cpuint debug asssertion bit mask 2024-09-30 20:42:00 +02:00
Filipe Cavalcanti
a876f00e2a risc-v/espressif: support marking interrupt as running from IRAM 2024-09-30 20:42:00 +02:00
Kevin Zhou
7acb298f26 xtensa/esp32s3: add setup rx dma after slave receive data 2024-09-30 21:24:55 +08:00
buxiasen
b0e8193b7a qemu/arm64: add pm support
add arm64 qemu pm compatible for demo pm_idle in not smp & smp usage
demo, chip should based on demo to add more operation in pm_idle_handler

Signed-off-by: buxiasen <buxiasen@xiaomi.com>
2024-09-30 20:23:11 +08:00
chenrun1
4b7c36554c mps_allocateheap:Modify the heap logic
Summary:
  Due to the modification of 4244610, the heap_size may be used on SRAM1, which can lead to misconfiguration problems for some mps qemu configurations (e.g.MPS3) that use extern DDR as the heap, refer to the previous issue VELAPLATFO-34555.

Signed-off-by: chenrun1 <chenrun1@xiaomi.com>
Signed-off-by: ligd <liguiding1@xiaomi.com>
2024-09-30 20:06:52 +08:00
ligd
23ad93f430 mps: update the mps3-an547 mps2-an500 defconfig
Fix compile failed when open BASEPRI
Open same feature on mps3

Signed-off-by: ligd <liguiding1@xiaomi.com>
2024-09-30 20:06:52 +08:00
anjiahao
f79ae00a4f mps3-an547:fix sram range error
Signed-off-by: anjiahao <anjiahao@xiaomi.com>
Signed-off-by: ligd <liguiding1@xiaomi.com>
2024-09-30 20:06:52 +08:00
anjiahao
9122c3e44d mps:Supplement the interrupt definition about nvic
Signed-off-by: anjiahao <anjiahao@xiaomi.com>
Signed-off-by: ligd <liguiding1@xiaomi.com>
2024-09-30 20:06:52 +08:00
qinwei1
9f97d9abb0 boards/arm.mps/mps2-an521: add support for mps-521 board
Summary
   MPS-521 support Dual Cortex-M33 and maybe suitable for AMP-like
case which is for AUTO OS, the change
  1. add support for single core at msp-521 with nsh bringup
  2. testing with ostest

TODO:
  Dual core support for flat-build
  Dual CORE support for Protected Build

Signed-off-by: qinwei1 <qinwei1@xiaomi.com>
Signed-off-by: ligd <liguiding1@xiaomi.com>
2024-09-30 20:06:52 +08:00
Gao Jiawei
aaf63d1d85 Enable stack check feature on MPS2-AN500 board
Signed-off-by: Gao Jiawei <gaojiawei@xiaomi.com>
Signed-off-by: ligd <liguiding1@xiaomi.com>
2024-09-30 20:06:52 +08:00
chenrun1
9f1ad1fc4f mps_an547:Adjust the an547 initialization stack allocation
Summary(for an547):
  1. Add maximum external storage expansion (2GB)
  2. Change PRIMARY_RAM_START to MPS_SRAM2_START (4MB)
  3. When REGIONS > 1, use external expansion as Heap

Signed-off-by: chenrun1 <chenrun1@xiaomi.com>
Signed-off-by: ligd <liguiding1@xiaomi.com>
2024-09-30 20:06:52 +08:00
qinwei1
02f1d732a9 arch/arm/src/mps: implement Protected Build for mps2-an500
Summary
 1. add Protected build Support for ARM MPS AN500
 2. refine mps Memory layout configure and enable MPU support
Note
 1. ostest for an547:nsh
 2. ostest for an500:nsh and an500:knsh

Signed-off-by: qinwei1 <qinwei1@xiaomi.com>
Signed-off-by: ligd <liguiding1@xiaomi.com>
2024-09-30 20:06:52 +08:00
Gao Jiawei
e763b0cfe6 add cmake building support for mps board
Signed-off-by: Gao Jiawei <gaojiawei@xiaomi.com>
Signed-off-by: ligd <liguiding1@xiaomi.com>
2024-09-30 20:06:52 +08:00
Jukka Laitinen
429252152a arch/arm64/src/common/arm64_arch_timer.c: Remove clock drift from tick timer
This fixes two issues with the tick timer
1) Each tick was longer than the requested period. This is because setting
   the compare register was done by first reading the current time, and only
   after that setting the compare register. In addition, when handling the
   timer interrupts in arch_alarm.c / oneshot_callback, the current_tick is
   first read, all the tick handling is done and only after that the next tick
   is started. The whole tick processing time was added to the total tick time.

2) When the compare time is not aligned with tick period, and is drifting,
   eventually any call to ONESHOT_TICK_CURRENT would either return the current
   tick, or the next one, depending on the rounding of division by the
   cycle_per_tick. This again leads to oneshot_callback randomly handling
   two ticks at a time, which breaks all wdog based timers, causing them to
   randomly timeout too early.

The issues are fixed as follows:

Align the compare time register to be evenly divisible by cycle_per_tick.
This will lead arm64_tick_current always to return the currently ongoing tick,
fixing 2). Also calculating the next tick's start from the aligned current
count will fix 1), as there is no time drift in the start cycle.

Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
2024-09-30 19:23:01 +08:00
hujun5
5fb56f6d95 sim: add NXSYMBOLS pthread_gettid_np pthread_self
reason:
enable sim:smp can boot

This commit fixes the regression from https://github.com/apache/nuttx/pull/12561

Signed-off-by: hujun5 <hujun5@xiaomi.com>
2024-09-30 18:26:00 +08:00
yezhonghui
85591fc360 pci alloc mis irq support new interface
Signed-off-by: yezhonghui <yezhonghui@xiaomi.com>
2024-09-30 15:41:28 +08:00
ouyangxiangzhen
edd7d718eb arch/x86_64: Reimplement the NuttX32 multiboot1 wrapper.
This commit reimplemented the NuttX32 multiboot1 wrapper:
1. Fixed the issue of SMP AP booting.
2. Reduced memory copy overhead. We only need to copy .realmode section
   now.
3. Move the multiboot1 header to intel64_head.S.

Signed-off-by: ouyangxiangzhen <ouyangxiangzhen@xiaomi.com>
2024-09-30 15:35:41 +08:00
chenxiaoyi
45f4ce84ad xtensa: fix up_saveusercontext in interrupt context
Signed-off-by: chenxiaoyi <chenxiaoyi@xiaomi.com>
2024-09-30 14:59:00 +08:00
ligd
c4b969b5ee armv7/8-m/r: fix build warning
Error: armv7-m/arm_mpu.c:211:13: error: function declaration isn't a prototype [-Werror=strict-prototypes]
  211 | static void mpu_reset_internal()
      |             ^~~~~~~~~~~~~~~~~~
cc1: all warnings being treated as errors
make[1]: *** [Makefile:168: arm_mpu.o] Error 1

Signed-off-by: ligd <liguiding1@xiaomi.com>
2024-09-30 14:09:15 +08:00
Huang Qi
52bb516d37 risc-v: Support customize idle loop
Support customize idle loop by CONFIG_ARCH_IDLE_CUSTOM
as other architectures.

Then user can provide their own `up_idle()` function
with CONFIG_ARCH_IDLE_CUSTOM enabled.

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2024-09-30 14:08:56 +08:00
hujun5
07061d882c fix compile error:
Register: smp
Register: nsh
Register: sh
Register: getprime
Register: ostest
Espressif HAL for 3rd Party Platforms: b4c723a119344b4b71d69819019d55637fb570fd
common/xtensa_cpupause.c: In function 'xtensa_pause_handler':
common/xtensa_cpupause.c:240:3: warning: implicit declaration of function 'xtensa_savestate'; did you mean 'xtensa_setps'? [-Wimplicit-function-declaration]
  240 |   xtensa_savestate(tcb->xcp.regs);
      |   ^~~~~~~~~~~~~~~~
      |   xtensa_setps
common/xtensa_cpupause.c:243:3: warning: implicit declaration of function 'xtensa_restorestate'; did you mean 'xtensa_context_restore'? [-Wimplicit-function-declaration]
  243 |   xtensa_restorestate(tcb->xcp.regs);
      |   ^~~~~~~~~~~~~~~~~~~
      |   xtensa_context_restore

Signed-off-by: hujun5 <hujun5@xiaomi.com>
2024-09-29 16:30:33 +08:00
dongjiuzhu1
1f1d90de1c binfmt/modlib: support loading each sections to different memory for Relocate object
The feature depends on ARCH_USE_SEPARATED_SECTION
the different memory area has different access speed and cache
capability, so the arch can custom allocate them based on
section names to achieve performance optimization

test:
sim:elf
sim:sotest

Signed-off-by: dongjiuzhu1 <dongjiuzhu1@xiaomi.com>
2024-09-29 15:06:54 +08:00
lipengfei28
6e746ed364 arm64 fork: FORK_REG_LR,FORK_REG_SP should save the func local stack
not the last func stack

Signed-off-by: lipengfei28 <lipengfei28@xiaomi.com>
2024-09-29 13:48:24 +08:00
hujun5
d4707646d5 arch: We can use an independent SIG interrupt to handle async pause,
which can save processing time.

Signed-off-by: hujun5 <hujun5@xiaomi.com>
2024-09-29 08:54:51 +08:00
hujun5
9de9f8168d sched: change the SMP scheduling policy from synchronous to asynchronous
reason:
Currently, if we need to schedule a task to another CPU, we have to completely halt the other CPU,
manipulate the scheduling linked list, and then resume the operation of that CPU. This process is both time-consuming and unnecessary.

During this process, both the current CPU and the target CPU are inevitably subjected to busyloop.

The improved strategy is to simply send a cross-core interrupt to the target CPU.
The current CPU continues to run while the target CPU responds to the interrupt, eliminating the certainty of a busyloop occurring.

Signed-off-by: hujun5 <hujun5@xiaomi.com>
2024-09-29 08:54:51 +08:00
hujun5
ba5091d2f7 arm64: remove the operation of clearing interrupts during GIC initialization
To align with the implementation of ARMv7-A, remove the operation of clearing
interrupts during GIC initialization to avoid losing interrupts during asynchronous startup.

Signed-off-by: hujun5 <hujun5@xiaomi.com>
2024-09-29 00:01:44 +08:00
hujun5
8f1a1006ec arm64:add busy wait flag
Signed-off-by: hujun5 <hujun5@xiaomi.com>
2024-09-29 00:01:44 +08:00
hujun5
5e2eadacf7 arm64/smp: changing the startup of arm64 SMP from serial to parallel
Signed-off-by: hujun5 <hujun5@xiaomi.com>
2024-09-29 00:01:44 +08:00
hujun5
64ebb149c6 syscall: Use a more compatible writing style
compile error:
Register: ostest
Register: nsh
Register: sh
Register: hello
Register: getprime
In file included from /home/hujun5/downloads1/vela_sim/nuttx/include/arch/irq.h:35,
                 from /home/hujun5/downloads1/vela_sim/nuttx/include/nuttx/irq.h:37,
                 from /home/hujun5/downloads1/vela_sim/nuttx/include/nuttx/sched.h:40,
                 from /home/hujun5/downloads1/vela_sim/nuttx/include/nuttx/arch.h:87,
                 from common/arm_signal_dispatch.c:26:
common/arm_signal_dispatch.c: In function 'up_signal_dispatch':
common/arm_signal_dispatch.c:72:3: error: 'asm' operand has impossible constraints
   72 |   sys_call4(SYS_signal_handler, (uintptr_t)sighand, (uintptr_t)signo,
      |   ^~~~~~~~~
make[1]: *** [Makefile:168:arm_signal_dispatch.o] error 1

Signed-off-by: hujun5 <hujun5@xiaomi.com>
2024-09-28 19:08:15 +08:00
hujun5
4c69bb8cc7 arch: inline up_switch_context,in arm arm64
reason:
when a context switch occurs, up_switch_context is executed.
In order to reduce the time taken for context switching,
we inline the up_switch_context function.

Signed-off-by: hujun5 <hujun5@xiaomi.com>
2024-09-28 19:08:15 +08:00
yezhonghui
f81c844685 arm64 support gicv2m for pci irq
Signed-off-by: yezhonghui <yezhonghui@xiaomi.com>
2024-09-28 16:09:11 +08:00
chenxiaoyi
b6225676f4 xtensa: hostfs: handle nonblock open for iss
Signed-off-by: chenxiaoyi <chenxiaoyi@xiaomi.com>
2024-09-28 13:53:06 +08:00
Yongrong Wang
fa6d41471f arm_gicv2.c: fix armv7a compile error
/vela/nuttx/drivers/pci/pci_ecam.c:432:(.text.pci_ecam_get_irq+0x16): undefined reference to `up_get_legacy_irq'

Signed-off-by: Yongrong Wang <wangyongrong@xiaomi.com>
2024-09-28 13:34:33 +08:00
lipengfei28
30be81add6 arm64 pci legacy irq do not support yet
Signed-off-by: lipengfei28 <lipengfei28@xiaomi.com>
2024-09-28 13:34:33 +08:00
lipengfei28
39ec3291ee armv7a pci irq support
Signed-off-by: lipengfei28 <lipengfei28@xiaomi.com>
2024-09-28 13:34:33 +08:00
hujun5
f49d5f4451 armv7a/r: fix use arch-timer in SMP
reason:
Only one timer will be effective at a time.In the current
implementation of NuttX's timer handling, only a single global timer is necessary.
Having an excessive number of timers can lead to additional performance
overhead and logical errors, especially when operating in SMP
(Symmetric Multi-Processing) tickless mode.

Signed-off-by: hujun5 <hujun5@xiaomi.com>
2024-09-28 11:52:09 +08:00
nuttxs
c0403ed768 1.xtensa/esp32s3: configure the number of universal management
(IEEE) MAC addresses when there are multipleinterfaces.
2.Optimize Lan9250 to adapt to ESP32S3 universalMAC address.
2024-09-28 11:47:24 +08:00
Filipe Cavalcanti
a64171f059 arch/xtensa/esp32s3: fix timer initialization 2024-09-28 10:43:49 +08:00
dulibo1
14f278ab89 sim:fix oneshot sim_cancel assert
when CONFIG_PM and CONFIG_CPULOAD_ONESHOT are defined
sim_cancel may assert:
[429492.185400] [ 0] [ EMERG] [ap] _assert: Current Version: NuttX ap 12.3.0 5ffeb16111-dirty Dec  4 2023 14:32:27 sim
[429492.185400] [ 0] [ EMERG] [ap] _assert: Assertion failed : at file: sim/sim_oneshot.c:367 task: Idle_Task process: Kernel 0x323254d
[429492.185400] [ 0] [ EMERG] [ap] backtrace:
[429492.185400] [ 0] [ EMERG] [ap] [ 0] [<0xf7941ad5>] _fini+0xf0753010/0xf8e1155b
[429492.185400] [ 0] [ EMERG] [ap] [ 0] [<0x71def50>] host_backtrace+0x41/0x72
[429492.185400] [ 0] [ EMERG] [ap] [ 0] [<0x65b68bd>] up_backtrace+0x126/0x2f8
[429492.185400] [ 0] [ EMERG] [ap] [ 0] [<0x6554ceb>] sched_backtrace+0x70/0x8a
[429492.185400] [ 0] [ EMERG] [ap] [ 0] [<0x37585d2>] sched_dumpstack+0xed/0x494
[429492.185400] [ 0] [ EMERG] [ap] [ 0] [<0x3694d8e>] _assert+0x93b/0xa82
[429492.185400] [ 0] [ EMERG] [ap] [ 0] [<0x33223eb>] __assert+0x3e/0x4c
[429492.185400] [ 0] [ EMERG] [ap] [ 0] [<0x336b6d5>] sim_cancel+0xde/0x392
[429492.185400] [ 0] [ EMERG] [ap] [ 0] [<0x36a4301>] nxsched_oneshot_pmnotify+0x2aa/0x2ee
[429492.185400] [ 0] [ EMERG] [ap] [ 0] [<0x36bce77>] pm_changeall+0x478/0x526
[429492.185400] [ 0] [ EMERG] [ap] [ 0] [<0x36bd71f>] pm_changestate+0x380/0x82c
[429492.185400] [ 0] [ EMERG] [ap] [ 0] [<0x336297b>] up_idle+0x54/0xa6
[429492.185400] [ 0] [ EMERG] [ap] [ 0] [<0x32347b8>] nx_start+0x226b/0x226e
[429492.185400] [ 0] [ EMERG] [ap] [ 0] [<0x31d49f5>] main+0x54/0x70
[429492.185400] [ 0] [ EMERG] [ap] [ 0] [<0xf6bbcfa1>] _fini+0xef9ce4dc/0xf8e1155b
[429492.185400] [ 0] [ EMERG] [ap] [ 0] [<0x31914ac>] _start+0x31/0x46

Signed-off-by: dulibo1 <dulibo1@xiaomi.com>
2024-09-28 10:43:09 +08:00
hujun5
e98dd37534 xtensa: g_current_regs is only used to determine if we are in irq,
with other functionalities removed.

reason:
by doing this we can reduce context switch time,
When we exit from an interrupt handler, we directly use tcb->xcp.regs

before
text    data     bss     dec     hex filename
178368     876  130604  309848   4ba58 nuttx
after
text    data     bss     dec     hex filename
178120     876  130212  309208   4b7d8 nuttx

szie change -248

Signed-off-by: hujun5 <hujun5@xiaomi.com>
2024-09-27 23:44:04 +08:00
guoshichao
c7d801fd9c greenhills: fix the arch_interface archive error
: && cxarm cr arch/libarch_interface.a  arch/CMakeFiles/arch_interface.dir/arm/src/common/gnu/arm_signal_handler.S.obj  && echo arch/libarch_interface.a && :
[elxr] (error #16) cannot find file cr

Signed-off-by: guoshichao <guoshichao@xiaomi.com>
2024-09-27 23:39:56 +08:00
dulibo1
3107822c08 smp:fix sim build error under config CONFIG_SMP
CC:  sim/sim_smpsignal.c init/nx_smpstart.c: In function ‘nx_idle_trampoline’:
init/nx_smpstart.c:68:21: warning: unused variable ‘tcb’ [-Wunused-variable]
   68 |   FAR struct tcb_s *tcb = this_task_inirq();
      |                     ^~~
sim/sim_smpsignal.c: In function ‘host_cpu_started’:
sim/sim_smpsignal.c:271:17: warning: unused variable ‘tcb’ [-Wunused-variable]
  271 |   struct tcb_s *tcb = this_task();

sim/sim_smpsignal.c:249:33: error: ‘cpu’ undeclared (first use in this function)
  249 |   restore_critical_section(tcb, cpu);
      |                                 ^~~

Signed-off-by: buxiasen <buxiasen@xiaomi.com>
2024-09-27 23:30:40 +08:00
Jani Paalijarvi
21f9fc2b28 mpfs_serial.c: Add RX flowcontrol
Disable RX interrupts and clear the fifo in case of full RX buffer.
Enable RX interrupts in case of empty buffer.
2024-09-27 10:53:12 -03:00
hujun5
3e459c0477 riscv: use g_running_task store current regs
This commit fixes the regression from https://github.com/apache/nuttx/pull/13561

In order to determine whether a context switch has occurred,
we can use g_running_task to store the current regs.
This allows us to compare the current register state with the previously
stored state to identify if a context switch has taken place.

Signed-off-by: hujun5 <hujun5@xiaomi.com>
2024-09-27 18:07:31 +08:00
ligd
981fd0cf53 xtesa: fix lost save & restore states caused by merge code
this is caused by:
35c8c80a00

Signed-off-by: ligd <liguiding1@xiaomi.com>
2024-09-27 16:18:36 +08:00
Jinliang Li
19230e3a2b arm/armv8-r: fix armv8 build error without neon
Fix the build error:
armv8-r/arm_vectors.S:205:Error: VFP single precision
register expected -- `vstmdb.64 sp!,{d16-d31}'
armv8-r/arm_vectors.S:242:Error: VFP single precision
register expected -- `vldmia.64 r0!,{d16-d31}'

Signed-off-by: Jinliang Li <lijinliang1@lixiang.com>
2024-09-27 11:23:05 +08:00
Ville Juven
9ef76e3735 riscv_fork.c: Fix race condition when handling parent integer registers
We need to record the parent's integer register context upon exception
entry to a separate non-volatile area. Why?

Because xcp.regs can move due to a context switch within the fork() system
call, be it either via interrupt or a synchronization point.

Fix this by adding a "sregs" area where the saved user context is placed.
The critical section within fork() is also unnecessary.
2024-09-27 10:22:43 +08:00
Ville Juven
172d2a8491 riscv_fork.c: Fix vfork() for kernel mode + SMP
There was an error in the fork() routine when system calls are in use:
the child context is saved on the child's user stack, which is incorrect,
the context must be saved on the kernel stack instead.

The result is a full system crash if (when) the child executes on a
different CPU which does not have the same MMU mappings active.
2024-09-27 10:22:43 +08:00
ligd
35c8c80a00 arch: change nxsched_suspend/resume_scheduler() called position
for the citimon stats:

thread 0:                     thread 1:
enter_critical (t0)
up_switch_context
note suspend thread0 (t1)

                              thread running
                              IRQ happen, in ISR:
                                post thread0
                                up_switch_context
                                note resume thread0 (t2)
                                ISR continue f1
                                ISR continue f2
                                ...
                                ISR continue fn

leave_critical (t3)

You will see, the thread 0, critical_section time is:
(t1 - t0) + (t3 - t2)

BUT, this result contains f1 f2 .. fn time spent, it is wrong
to tell user thead0 hold the critical lots of time but actually
not belong to it.

Resolve:
change the nxsched_suspend/resume_scheduler to real hanppends

Signed-off-by: ligd <liguiding1@xiaomi.com>
2024-09-27 09:53:33 +08:00
guoshichao
dbe09c1505 greenhills: add -Osize build option to reduce the size
Signed-off-by: guoshichao <guoshichao@xiaomi.com>
2024-09-27 00:17:58 +08:00
guoshichao
8c651d3d05 greenhills: add support for cortex-m4 platform
Signed-off-by: guoshichao <guoshichao@xiaomi.com>
2024-09-27 00:17:58 +08:00
qinwei1
8ae35754e5 arm64: add arm64_current_el to obtain current EL
Summary
  Add a macro to obtain current execute level

Signed-off-by: qinwei1 <qinwei1@xiaomi.com>
2024-09-27 00:16:41 +08:00
qinwei1
c535fb1438 arm64: refine the fatal handler
Summary
  The original implement for exception handler is very simple and
haven't framework for breakpoint/watchpoint routine or brk instruction.
  I refine the fatal handler and add framework for debug handler to
register or unregister. this is a prepare for watchpoint/breakpoint
implement

Signed-off-by: qinwei1 <qinwei1@xiaomi.com>
2024-09-27 00:16:41 +08:00
ligd
551e6ce3ab compile: add DEBUG_SYMBOLS_LEVEL allow custom the level
Signed-off-by: ligd <liguiding1@xiaomi.com>
2024-09-27 00:13:07 +08:00
anjiahao
c76e83beaa Debug option:change -g to -g3, add macro information to elf
Signed-off-by: anjiahao <anjiahao@xiaomi.com>
2024-09-27 00:13:07 +08:00
YAMAMOTO Takashi
08dcef4de0 xtensa_macros.S: fix tab/space mismatches 2024-09-27 00:10:42 +08:00
lipengfei28
56f57e5f9b add pci irq interface
Signed-off-by: lipengfei28 <lipengfei28@xiaomi.com>
2024-09-27 00:10:19 +08:00
ouyangxiangzhen
f3973c7e46 imx8qm-mek: Fix early print
Function `arm64_lowputc` corrupted the x1 register which is used in function `boot_stage_puts`.

Signed-off-by: ouyangxiangzhen <ouyangxiangzhen@xiaomi.com>
2024-09-27 00:09:50 +08:00
nuttxs
1dfea8798b arch/xtensa/esp32s3: Adding an ioctl interface ota_invalidate_bootseq()
to the ESP32-S3 partitions, by deleting the corresponding otadata, makes
the boot sequence (ota_0/1) invalid.
2024-09-26 23:52:17 +08:00
guoshichao
74d627f5f0 greenhills: fix the arm_signal_handler.S build error
[asarm] (error #2067) /home/guoshichao/work_profile/vela_os/vela_car_6/nuttx/arch/arm/src/common/gnu/arm_signal_handler.S 35: unknown instruction
  .syntax unified
--^

[asarm] (error #2067) /home/guoshichao/work_profile/vela_os/vela_car_6/nuttx/arch/arm/src/common/gnu/arm_signal_handler.S 70: unknown instruction
  .thumb_func
--^

[asarm] (error #2230) /home/guoshichao/work_profile/vela_os/vela_car_6/nuttx/arch/arm/src/common/gnu/arm_signal_handler.S 72: bad directive
  .type up_signal_handler , function
----------------------------^

Signed-off-by: guoshichao <guoshichao@xiaomi.com>
2024-09-26 23:15:07 +08:00
Huang Qi
d9b95c5ca0 riscv: Remove some unnecessary macro guards
If CONFIG_SMP is not enabled, riscv_cpuindex.c will not be compiled
anyway.

And for CONFIG_ARCH_FPU, if it's not enabled, riscv_fpucmp.c will not
be compiled.

So we can remove the unnecessary macro guard for up_cpu_index() and
up_fpucmp().

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2024-09-26 16:23:48 +08:00
chao an
a04e44ea75 syslog/channel: move syslog channel map into rodata
add SYSLOG_REGISTER to support disable syslog channel register

Signed-off-by: chao an <anchao@lixiang.com>
2024-09-26 16:10:29 +08:00
chao an
9abe737ef3 syslog/channel: add constant attribute if SYSLOG_IOCTL is not enabled
move all private channel define from data to rodata

Signed-off-by: chao an <anchao@lixiang.com>
2024-09-26 16:10:29 +08:00
Jukka Laitinen
950b63c7f1 arch/risc-v/src/mpfs/mpfs_opensbi.c: Fix conflicting datatypes defined by NuttX vs. opensbi
Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
2024-09-26 16:10:09 +08:00
Jukka Laitinen
82ef3813bd arch/risc-v/src/mpfs: Make mpfs_hart_index2id table modifiable by bootloader
This is actually the same table as entrypoints, so just use the same data, which
can be set before booting any of the harts

Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
2024-09-26 16:10:09 +08:00
Ville Juven
27648479bc mpfs_mpucfg.h: Add missing MPUCFG registers
Now all registers are defined
2024-09-26 16:09:54 +08:00
Jukka Laitinen
06b3416384 arch/risc-v/src/common/riscv_initialstate.c: Fix stack pointer in coloration
The logical CPU index should be retrieved with this_cpu(); the
riscv_mhartid() returns the actual hart id of the SoC.

For mpfs target for example, NuttX can run on a single HART, for example on mhartid 2, but there is still just one logical CPU for the NuttX.

Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
2024-09-26 08:35:42 +08:00
adriendesp
6d72a8d676 [arch/xmc4] added register description for ERU and POSIF peripherals
Register map of ERU and POSIF peripherals, from the Ref. Manuals for both XMC45 and XMC4[7-8]
2024-09-25 19:05:12 -03:00
Bowen Wang
dbe43b0ae9 rptun: move rptun cmd definition before the resource table
Because locate the command at the end the resource table is unfriendly
when we want to support multi virtio devices instead only one virtio
rpmsg device.

Signed-off-by: Bowen Wang <wangbowen6@xiaomi.com>
2024-09-26 00:04:05 +08:00
Yongrong Wang
10e8b6c9f6 rptun/rpmsg_virtio: remove chip cmd and reuse the common ones
Add more common command for rptun and rpmsg_virtio frameworks,
also modify the rptun and rpmsg_virtio driver to use the common
commands.

Signed-off-by: Yongrong Wang <wangyongrong@xiaomi.com>
2024-09-26 00:04:05 +08:00
Yongrong Wang
420af99797 sim_rptun.c: remove sim_rptun_panic
Because we can use the common part implemented in rptun

Signed-off-by: Yongrong Wang <wangyongrong@xiaomi.com>
2024-09-26 00:04:05 +08:00
Yongrong Wang
7c7d08d13a rptun.c/rpmsg_virtio.c: move panic logic from chip to rptun/rpmsg_virtio
Move the panic logic in common places, later we can move more logic to
the framework instead of having the drivers implement it repeatedly.

Signed-off-by: Yongrong Wang <wangyongrong@xiaomi.com>
Signed-off-by: Bowen Wang <wangbowen6@xiaomi.com>
2024-09-26 00:04:05 +08:00
Bowen Wang
9cceccb14a sim/sim_rptun: add 64-bit support for sim_rptun
add remote addrenv to make the da is start from 0, so the uint32_t
da in resource table can store the correct address

Signed-off-by: Bowen Wang <wangbowen6@xiaomi.com>
2024-09-26 00:04:05 +08:00
wangyongrong
5668a3e283 x86_64_pci.c: x86_64_pci_read/write_io memory support
Signed-off-by: wangyongrong <wangyongrong@xiaomi.com>
2024-09-26 00:00:03 +08:00
Eero Nurkkala
737d4bf418 risc-v/mpfs: emmcsd: enforce HS DDR mode
Previously, address 0x03b70000u was written with shift bits
that only changed the bit width, not the mode. HS mode is
changed via 0x03B90100, which is required, according to Jedec
specs, for DDR mode. HS mode was not applied before. Enforce
DDR mode (50 MHz) for now.

The real boost, however, comes from removing the DMA limitation
at 0x08xxxxxx address space, which now seems unnecessary.

Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
2024-09-25 23:58:08 +08:00
Eero Nurkkala
6db0f7f009 risc-v/mpfs: emmcsd: deny unaligned access
Don't allow unaligned access with the DMA requests.
Return -EFAULT in case the provided address is unaligned.

Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
2024-09-25 23:58:08 +08:00
Jari Nippula
9b60f8d9d0 emmc interrupt blackout issue fix
sendfifo() function need enable BWR_IE before checking if BWE is enabled
to avoid BWE to be activated between the BWE check and BWR interrupt
enabling, which causes the interrupt to be missed and Data Timeout error.
2024-09-25 23:58:08 +08:00
Ville Juven
c23babbcc7 mpfs/emmcsd: Set 8-bit data width and DDR HS mode for eMMC
This is not the correct way to do this, but it gives a nice perf. boost
2024-09-25 23:58:08 +08:00
Ville Juven
c36bdba3cb mpfs/emmcsd: Set same base clock for SDR/DDR modes 2024-09-25 23:58:08 +08:00
Huang Qi
c1b41fefeb riscv_cpuinfo: Add support for RVV extension in CPU info
Add missing info for RVV ISA extention, which is already supported
by NuttX.

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2024-09-25 23:54:19 +08:00
Jani Paalijarvi
3613eb209a arch/risc-v/src/mpfs/mpfs_corepwm.c: Disable PWM channels in setup
Set frequency to zero and disable channels in pwm_setup()
to avoid unexpected behaviour when starting PWM.

Signed-off-by: Jani Paalijarvi <jani.paalijarvi@unikie.com>
2024-09-25 21:47:15 +08:00
Jukka Laitinen
7e6e18697c arch/risc-v/src/mpfs: Remove CONFIG_MPFS_COREPWMx_PWMCLK configs
These are always the same as FPGA peripheral clock, so use that directly

Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
2024-09-25 21:47:15 +08:00
hujun5
efdb4322fc arm: we should use tcb->xcp.regs instead of up_current_regs() as the basis for judging whether to call restore_critical_section.
This commit fixes the regression from https://github.com/apache/nuttx/pull/13444

Signed-off-by: hujun5 <hujun5@xiaomi.com>
2024-09-25 17:10:14 +09:00
chao an
542e2ba625 CMake/preprocess: fix typo PREPROCES -> PREPROCESS
correct the marco define from PREPROCES to PREPROCESS

Signed-off-by: chao an <anchao@lixiang.com>
2024-09-25 11:55:06 +08:00
hujun5
b0f8b6e2ca arm64: g_current_regs is only used to determine if we are in irq,
with other functionalities removed.

Signed-off-by: hujun5 <hujun5@xiaomi.com>
2024-09-25 08:58:20 +08:00
hujun5
c9bdb598b7 irq: use up_interrupt_context to replace up_current_regs
Signed-off-by: hujun5 <hujun5@xiaomi.com>
2024-09-25 08:58:20 +08:00