Fix CMake-based build system to include the toolchain's libm only
when `CONFIG_LIBM_TOOLCHAIN` is selected. Before this commit, if
the user selected `CONFIG_LIBM_NEWLIB`, for instance, the build
system would still link the toolchain's libm functions instead of
the ones provided by newlib.
PS: this commit applies the same changes previously introduced for
the other architectures.
Most tools used for compliance and SBOM generation use SPDX identifiers
This change brings us a step closer to an easy SBOM generation.
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
reason:
Since the scheduling records have already been moved to the interrupt exit in this submission,
we need to delete the original records' locations.
This commit fixes the regression from https://github.com/apache/nuttx/pull/13651
Signed-off-by: hujun5 <hujun5@xiaomi.com>
reason:
up_set_current_regs initially had two functions:
1: To mark the entry into an interrupt state.
2: To record the context before an interrupt/exception. If we switch to
a new task, we need to store the upcoming context regs by calling up_set_current_regs(regs).
Currently, we record the context in other ways, so the second function is obsolete. Therefore,
we need to rename up_set_current_regs to better reflect its actual meaning, which is solely to mark an interrupt.
Signed-off-by: hujun5 <hujun5@xiaomi.com>
profile-generate is used to generate compilation feedback optimization data, not just code coverage data
It will rely on the toolchain library:
nuttx/libs/libc/misc/lib_utsname.c:94:(.text.uname+0x2c): undefined reference to `__gcov_indirect_call_profiler_v4'
arm-none-eabi-ld: nuttx/libs/libc/misc/lib_utsname.c:113:(.text.uname+0x178): undefined reference to `__gcov_indirect_call'
arm-none-eabi-ld: nuttx/libs/libc/misc/lib_utsname.c:113:(.text.uname+0x188): undefined reference to `__gcov_time_profiler_counter'
arm-none-eabi-ld: nuttx/staging/libc.a(lib_utsname.o):(.data..LPBX0+0x30): undefined reference to `__gcov_merge_time_profile'
Signed-off-by: yinshengkai <yinshengkai@xiaomi.com>
Read base frequency from system counter0 and write it
to arm core register. This corrects timers to work properly
Then enable counting.
Signed-off-by: Jouni Ukkonen <jouni.ukkonen@unikie.com>
Hardware initialization is based refcount, not
spi enable bit and add interface to unitialize bus
Signed-off-by: Jouni Ukkonen <jouni.ukkonen@unikie.com>
Both RX and TX interrupts can be enabled after the setup of the transfer; the TX interrupt
must be enabled after queuing the first byte as done before. It is not possible to miss the
RX interrupts, as it pends as long as the byte gets read from the FIFO
When starting the TX, the first byte can be queued instantly, it won't be sent out to the
bus if there is NACK to the address. This also prevents spurious TX interrupts in error
cases, since the TX queue is not empty after initiating a transfer.
In some error cases controller sends STOP by itself even if AUTOSTOP is disabled.
It is better to tell the controller to ABORT, which will also generate STOP only when needed.
Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
time/lib_localtime.c: In function 'tz_lock':
time/lib_localtime.c:396:7: error: 'tpidr_el1' undeclared (first use in this function)
396 | if (up_interrupt_context() || (sched_idletask() && OSINIT_IDLELOOP()))
| ^~~~~~~~~~~~~~~~~~~~
Signed-off-by: ligd <liguiding1@xiaomi.com>
reason:
When entering an exception or interrupt, there are two sets of registers:
one is the "running regs", which we need to save,
and the other is the "ready to running regs", which we may soon use.
For consistency in logic, we can always store the "running regs" in the regs field of g_running_tasks,
otherwise it may lead to errors in the storage location of the "running regs."
When we need to access the "running regs," we should uniformly retrieve them from the regs field of g_running_tasks.
As the next step, we will rename the set_current_regs/up_current_regs functions
for each architecture to more appropriate names, solely for the purpose of identifying interrupts.
Signed-off-by: hujun5 <hujun5@xiaomi.com>
This performs the DDR training for imx93-evk. In addition to the source code,
it downloads binaries which are included in the final image. The bootloader
must be ARCH_CORTEX_A53 instead of A55 due to atomic instructions that don't
work with the OCRAM / EL3 combination.
Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
Trdc is configured in EL3 bootloader
Clock pre-initialization is also executed there.
Trdc board configuration for imx93evk included
Signed-off-by: Jouni Ukkonen <jouni.ukkonen@unikie.com>
when we build mbedtls in vela with ghs compiler, the mbedtls need to
access __ARM_ARCH and __ARM_FEATURE_DSP, and to construct the inline asm
code based on these two macros.
With ghs compiler, these two macros are not defined, and will be
evaluated as 0 by default, and thus will using to wrong inline asm code,
in order to handle this issue, we need to add conversion between the ghs
and gcc with __ARM_ARCH, __ARM_FEATURE_DSP
Signed-off-by: guoshichao <guoshichao@xiaomi.com>
In the virtualized environment, each time an SGI is sent, the value of IGROUPR0 needs to be read once. Since the GIC Redistributor is a purely emulated device, each read of IGROUPR0 will cause a VM exit, causing serious performance degradation. This patch replaces the read with the value previously set in `gicv3_cpuif_init`, and we assume that this value has not been modified after initialization.
Signed-off-by: ouyangxiangzhen <ouyangxiangzhen@xiaomi.com>
