tcp: Remove incomplete support for TCP reassembly

Urgent data preceded "normal" data in the TCP payload.  If the urgent data is larger than the size of the TCP payload, this indicates that the entire payload is urgent data and that urgent data continues in the next packet.

This case was handled correctly for the case where urgent data was present but was not being handled correctly in the case where the urgent data was NOT present.

.github/workflows/build.yml

@@ -124,7 +124,7 @@ jobs:
 
     strategy:
       matrix:
-        boards: [arm-01, arm-02, arm-03, arm-04, arm-05, arm-06, arm-07, arm-08, arm-09, arm-10, arm-11, arm-12, arm-13, avr-mips-riscv-x86-xtensa, sim, renesas]
+        boards: [arm-01, arm-02, arm-03, arm-04, arm-05, arm-06, arm-07, arm-08, arm-09, arm-10, arm-11, arm-12, arm-13, other, sim]
 
     steps:
       - name: Download Source Artifact
@@ -150,7 +150,7 @@ jobs:
           command: docker pull docker.pkg.github.com/apache/incubator-nuttx-testing/nuttx-ci-linux
 
       - name: Export NuttX Repo SHA
-        run:  echo "::set-env name=nuttx_sha::`git -C sources/nuttx rev-parse HEAD`"
+        run:  echo "nuttx_sha=`git -C sources/nuttx rev-parse HEAD`" >> $GITHUB_ENV
       - name: Run builds
         uses: ./sources/testing/.github/actions/ci-container
         env:
@@ -161,15 +161,20 @@ jobs:
             export CCACHE_DIR=`pwd`/ccache
             mkdir $CCACHE_DIR
             cd sources/testing
-            ./cibuild.sh -c testlist/${{matrix.boards}}.dat
+            export ARTIFACTDIR=`pwd`/../../buildartifacts
+            ./cibuild.sh -A -c testlist/${{matrix.boards}}.dat
             ccache -s
+      - uses: actions/upload-artifact@v2
+        with:
+          name: linux-builds
+          path: buildartifacts/
 
   macOS:
     runs-on: macos-10.15
     needs: Fetch-Source
     strategy:
       matrix:
-        boards: [arm-12, avr-mips-riscv-x86-xtensa, sim]
+        boards: [arm-12, other, sim]
     steps:
       - name: Download Source Artifact
         uses: actions/download-artifact@v1
@@ -188,12 +193,17 @@ jobs:
           key: ${{ runner.os }}-tools-${{ hashFiles('./sources/testing/cibuild.sh') }}
 
       - name: Export NuttX Repo SHA
-        run:  echo "::set-env name=nuttx_sha::`git -C sources/nuttx rev-parse HEAD`"
+        run:  echo "nuttx_sha=`git -C sources/nuttx rev-parse HEAD`" >> $GITHUB_ENV
       - name: Run Builds
         run: |
           echo "::add-matcher::sources/nuttx/.github/gcc.json"
           export CCACHE_DIR=`pwd`/ccache
           mkdir $CCACHE_DIR
           cd sources/testing
-          ./cibuild.sh -i -c testlist/${{matrix.boards}}.dat
+          export ARTIFACTDIR=`pwd`/../../buildartifacts
+          ./cibuild.sh -i -A -c testlist/${{matrix.boards}}.dat
           ccache -s
+      - uses: actions/upload-artifact@v2
+        with:
+          name: macos-builds
+          path: buildartifacts/

Documentation/Makefile

@@ -23,7 +23,7 @@
 
 # You can set these variables from the command line, and also
 # from the environment for the first two.
-SPHINXOPTS    ?= -j auto
+SPHINXOPTS    ?= -j auto -A nuttx_versions="latest,${NUTTX_VERSIONS}"
 SPHINXBUILD   ?= sphinx-build
 SOURCEDIR     = .
 BUILDDIR      = _build

Documentation/_static/custom.css

@@ -78,3 +78,16 @@ kbd {
   -webkit-border-radius: 3px;
   text-shadow: 0 1px 0 #fff;
 }
+
+span.menuselection
+{
+  margin: 0px 0.1em;
+  padding: 0.1em 0.1em;
+  border-radius: 3px;
+  border: 1px solid rgb(204, 204, 204);
+}
+
+div.version-selector
+{
+  margin-bottom: 1em;
+}

Documentation/_templates/layout.html

@@ -37,9 +37,9 @@
        more modern -->
        
   <div class="version-selector">
-    <select>
-    {% for nuttx_version in nuttx_versions %}
-      <option value="{{ nuttx_version }}" {% if nuttx_version == version %}selected="selected"{% endif %}>{{ nuttx_version }}</option>
+    <select onchange="javascript:location.href = this.value;">
+    {% for nuttx_version in nuttx_versions.split(',') %}
+    <option value="{{ url_root }}../{{ nuttx_version }}" {% if nuttx_version == version %}selected="selected"{% endif %}>{{ nuttx_version }}</option>
     {% endfor %}
     </select>
   </div>

Documentation/conf.py

@@ -74,10 +74,12 @@ templates_path = ['_templates']
 # This pattern also affects html_static_path and html_extra_path.
 exclude_patterns = ['_build', 'Thumbs.db', '.DS_Store']
 
-# list of documentation versions to offer (besides latest)
+# list of documentation versions to offer (besides latest). this will be
+# overriden by command line option but we can provide a sane default
+# this way
 
 html_context = dict()
-html_context['nuttx_versions'] = ['latest']
+html_context['nuttx_versions'] = 'latest'
 
 # TODO: append other options using releases detected from git (or maybe just
 # a few hand-selected ones, or maybe just a "stable" option)

Documentation/quickstart/configuring.rst

@@ -32,7 +32,6 @@ has your configuration options selected.
        -l selects the Linux (l) host environment.
        -m selects the macOS (m) host environment.
        -c selects the Windows host and Cygwin (c) environment.
-       -u selects the Windows host and Ubuntu under Windows 10 (u) environment.
        -g selects the Windows host and MinGW/MSYS environment.
        -n selects the Windows host and Windows native (n) environment.
 

Kconfig

@@ -93,12 +93,6 @@ config WINDOWS_CYGWIN
 		Build natively in a Cygwin environment with POSIX style paths (like
 		/cygdrive/c/Program Files)
 
-config WINDOWS_UBUNTU
-	bool "Ubuntu under Windows 10"
-	---help---
-		Build natively in an Ubuntu shell under Windows 10 environment with
-		POSIX style paths (like /mnt/c/Program Files)
-
 config WINDOWS_MSYS
 	bool "MSYS or MSYS2"
 	select TOOLCHAIN_WINDOWS

TODO

@@ -1,4 +1,4 @@
-NuttX TODO List (Last updated July 19, 2020)
+NuttX TODO List (Last updated November 20, 2020)
 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
 
 This file summarizes known NuttX bugs, limitations, inconsistencies with
@@ -10,7 +10,7 @@ issues related to each board port.
 nuttx/:
 
  (16)  Task/Scheduler (sched/)
-  (5)  SMP
+  (3)  SMP
   (1)  Memory Management (mm/)
   (0)  Power Management (drivers/pm)
   (5)  Signals (sched/signal, arch/)
@@ -18,7 +18,7 @@ nuttx/:
   (0)  Message Queues (sched/mqueue)
   (1)  Work Queues (sched/wqueue)
   (6)  Kernel/Protected Build
-  (3)  C++ Support
+  (2)  C++ Support
   (5)  Binary loaders (binfmt/)
  (17)  Network (net/, drivers/net)
   (4)  USB (drivers/usbdev, drivers/usbhost)
@@ -448,34 +448,6 @@ o Task/Scheduler (sched/)
 o SMP
   ^^^
 
-  Title:       SMP AND DATA CACHES
-  Description: When spinlocks, semaphores, etc. are used in an SMP system with
-               a data cache, then there may be problems with cache coherency
-               in some CPU architectures:  When one CPU modifies the shared
-               object, the changes may not be visible to another CPU if it
-               does not share the data cache. That would cause failure in
-               the IPC logic.
-
-               Flushing the D-cache on writes and invalidating before a read is
-               not really an option.  That would essentially effect every memory
-               access and there may be side-effects due to cache line sizes
-               and alignment.
-
-               For the same reason a separate, non-cacheable memory region is
-               not an option.  Essentially all data would have to go in the
-               non-cached region and you would have no benefit from the data
-               cache.
-
-               On ARM Cortex-A, each CPU has a separate data cache.  However,
-               the MPCore's Snoop Controller Unit supports coherency among
-               the different caches.  The SCU is enabled by the SCU control
-               register and each CPU participates in the SMP coherency by
-               setting the ACTLR_SMP bit in the auxiliary control register
-               (ACTLR).
-
-  Status:      Closed
-  Priority:    High on platforms that may have the issue.
-
   Title:       MISUSE OF sched_lock() IN SMP MODE
   Description: The OS API sched_lock() disables pre-emption and locks a
                task in place.  In the single CPU case, it is also often
@@ -496,37 +468,6 @@ o SMP
   Priority:    Medium for SMP system.  Not critical to single CPU systems.
                NOTE:  There are no known bugs from this potential problem.
 
-  Title:       CORTEX-A GIC SGI INTERRUPT MASKING
-  Description: In the ARMv7-A GICv2 architecture, the inter-processor
-               interrupts (SGIs) are non maskable and will occur even if
-               interrupts are disabled.  This adds a lot of complexity
-               to the ARMV7-A critical section design.
-
-               Masayuki Ishikawa has suggested the use of the GICv2 ICCMPR
-               register to control SGI interrupts.  This register (much like
-               the ARMv7-M BASEPRI register) can be used to mask interrupts
-               by interrupt priority.  Since SGIs may be assigned priorities
-               the ICCMPR should be able to block execution of SGIs as well.
-
-               Such an implementation would be very similar to the BASEPRI
-               (vs PRIMASK) implementation for the ARMv7-M:  (1) The
-               up_irq_save() and up_irq_restore() registers would have to
-               set/restore the ICCMPR register, (2) register setup logic in
-               arch/arm/src/armv7-a for task start-up and signal dispatch
-               would have to set the ICCMPR correctly, and (3) the 'xcp'
-               structure would have to be extended to hold the ICCMPR
-               register;  logic would have to added be save/restore the
-               ICCMPR register in the 'xcp' structure on each interrupt and
-               context switch.
-
-               This would also be an essential part of a high priority,
-               nested interrupt implementation (unrelated).
-  Status:      Open
-  Priority:    Low.  There are no known issues with the current non-maskable
-               SGI implementation.  This change would, however, lead to
-               simplification in the design and permit commonality with
-               other, non-GIC implementations.
-
   Title:       ISSUES WITH ACCESSING CPU INDEX
   Description: The CPU number is accessed usually with the macro this_cpu().
                The returned CPU number is then used for various things,
@@ -550,7 +491,7 @@ o SMP
                can that occur?  I think it can occur in the following
                situation:
 
-               The log below was reported is Nuttx running on two cores
+               The log below was reported is NuttX running on two cores
                Cortex-A7 architecture in SMP mode.  You can notice see that
                when nxsched_add_readytorun() was called, the g_cpu_irqset is 3.
 
@@ -1077,23 +1018,6 @@ o Kernel/Protected Build
 o C++ Support
   ^^^^^^^^^^^
 
-  Title:       USE OF SIZE_T IN NEW OPERATOR
-  Description: The argument of the 'new' operators should take a type of
-               size_t (see libxx/libxx_new.cxx and libxx/libxx_newa.cxx).  But
-               size_t has an unknown underlying.  In the nuttx sys/types.h
-               header file, size_t is typed as uint32_t (which is determined by
-               architecture-specific logic).  But the C++ compiler may believe
-               that size_t is of a different type resulting in compilation errors
-               in the operator.  Using the underlying integer type Instead of
-               size_t seems to resolve the compilation issues.
-  Status:      Kind of open. There is a workaround. Setting CONFIG_ARCH_SIZET_LONG
-               =y will define the operators with argument of type unsigned long;
-               Setting CONFIG_ARCH_SIZET_LONG=n will define the operators with
-               argument of type unsigned int. But this is pretty ugly!  A better
-               solution would be to get a hold of the compilers definition of
-               size_t.
-  Priority:    Low.
-
   Title:       STATIC CONSTRUCTORS AND MULTITASKING
   Description: The logic that calls static constructors operates on the main
                thread of the initial user application task.  Any static

arch/arm/src/a1x/a1x_serial.c

@@ -1270,8 +1270,6 @@ static int up_ioctl(struct file *filep, int cmd, unsigned long arg)
          * that only one speed is supported.
          */
 
-        /* Get the c_speed field in the termios struct */
-
         priv->baud = cfgetispeed(termiosp);
 
         /* TODO: Re-calculate the optimal CCLK divisor for the new baud and

arch/arm/src/am335x/am335x_serial.c

@@ -515,7 +515,8 @@ static inline uint32_t up_serialin(struct up_dev_s *priv, int offset)
  * Name: up_serialout
  ****************************************************************************/
 
-static inline void up_serialout(struct up_dev_s *priv, int offset, uint32_t value)
+static inline void up_serialout(struct up_dev_s *priv, int offset,
+                                uint32_t value)
 {
   putreg32(value, priv->uartbase + offset);
 }
@@ -565,13 +566,13 @@ static inline void up_enablebreaks(struct up_dev_s *priv, bool enable)
   up_serialout(priv, AM335X_UART_LCR_OFFSET, lcr);
 }
 
-/************************************************************************************
+/****************************************************************************
  * Name: am335x_uart0config, uart1config, uart2config, ..., uart5config
  *
  * Descrption:
  *   Configure the UART
  *
- ************************************************************************************/
+ ****************************************************************************/
 
 #ifdef CONFIG_AM335X_UART0
 static inline void am335x_uart0config(void)
@@ -699,7 +700,7 @@ static inline void am335x_uart5config(void)
 };
 #endif
 
-/************************************************************************************
+/****************************************************************************
  * Name: am335x_uartdl
  *
  * Description:
@@ -708,7 +709,7 @@ static inline void am335x_uart5config(void)
  *     BAUD = PCLK / (16 * DL), or
  *     DL   = PCLK / BAUD / 16
  *
- ************************************************************************************/
+ ****************************************************************************/
 
 static inline uint32_t am335x_uartdl(uint32_t baud)
 {
@@ -758,11 +759,13 @@ static int up_setup(struct uart_dev_s *dev)
 
   /* Clear FIFOs */
 
-  up_serialout(priv, AM335X_UART_FCR_OFFSET, (UART_FCR_RFIFO_CLEAR | UART_FCR_TFIFO_CLEAR));
+  up_serialout(priv, AM335X_UART_FCR_OFFSET,
+               (UART_FCR_RFIFO_CLEAR | UART_FCR_TFIFO_CLEAR));
 
   /* Configure the FIFOs */
 
-  up_serialout(priv, AM335X_UART_FCR_OFFSET, (UART_FCR_FIFO_EN | UART_FCR_RFT_60CHAR | UART_FCR_TFT_56CHAR));
+  up_serialout(priv, AM335X_UART_FCR_OFFSET,
+    (UART_FCR_FIFO_EN | UART_FCR_RFT_60CHAR | UART_FCR_TFT_56CHAR));
 
   /* Set up the IER */
 
@@ -846,14 +849,15 @@ static void up_shutdown(struct uart_dev_s *dev)
  * Name: up_attach
  *
  * Description:
- *   Configure the UART to operation in interrupt driven mode.  This method is
- *   called when the serial port is opened.  Normally, this is just after the
+ *   Configure the UART to operation in interrupt driven mode.  This method
+ *   is called when the serial port is opened.  Normally, this is just after
  *   the setup() method is called, however, the serial console may operate in
  *   a non-interrupt driven mode during the boot phase.
  *
- *   RX and TX interrupts are not enabled when by the attach method (unless the
- *   hardware supports multiple levels of interrupt enabling).  The RX and TX
- *   interrupts are not enabled until the txint() and rxint() methods are called.
+ *   RX and TX interrupts are not enabled when by the attach method (unless
+ *   the hardware supports multiple levels of interrupt enabling).  The RX
+ *   and TX interrupts are not enabled until the txint() and rxint() methods
+ *   are called.
  *
  ****************************************************************************/
 
@@ -882,8 +886,8 @@ static int up_attach(struct uart_dev_s *dev)
  *
  * Description:
  *   Detach UART interrupts.  This method is called when the serial port is
- *   closed normally just before the shutdown method is called.  The exception is
- *   the serial console which is never shutdown.
+ *   closed normally just before the shutdown method is called.  The
+ *   exception is the serial console which is never shutdown.
  *
  ****************************************************************************/
 
@@ -990,7 +994,9 @@ static int uart_interrupt(int irq, void *context, void *arg)
               return OK;
             }
 
-            /* Otherwise we have received an interrupt that we cannot handle */
+            /* Otherwise we have received an interrupt that we cannot
+             * handle
+             */
 
           default:
             {
@@ -1090,16 +1096,16 @@ static int up_ioctl(struct file *filep, int cmd, unsigned long arg)
          * that only one speed is supported.
          */
 
-        /* Get the c_speed field in the termios struct */
-
         priv->baud = cfgetispeed(termiosp);
 
         /* TODO: Re-calculate the optimal CCLK divisor for the new baud and
          * and reset the divider in the CLKSEL0/1 register.
          */
 
-        /* DLAB open latch */
-        /* REVISIT:  Shouldn't we just call up_setup() to do all of the following? */
+        /* DLAB open latch
+         * REVISIT:  Shouldn't we just call up_setup() to do all of the
+         *           following?
+         */
 
         lcr = up_serialin(priv, AM335X_UART_LCR_OFFSET);
         up_serialout(priv, AM335X_UART_LCR_OFFSET, (lcr | UART_LCR_DLAB));
@@ -1107,7 +1113,8 @@ static int up_ioctl(struct file *filep, int cmd, unsigned long arg)
         /* Set the BAUD divisor */
 
         dl = am335x_uartdl(priv->baud);
-        up_serialout(priv, AM335X_UART_DLH_OFFSET, (dl >> 8) & UART_DLH_MASK);
+        up_serialout(priv, AM335X_UART_DLH_OFFSET,
+                     (dl >> 8) & UART_DLH_MASK);
         up_serialout(priv, AM335X_UART_DLL_OFFSET, dl & UART_DLL_MASK);
 
         /* Clear DLAB */

arch/arm/src/arm/arm_assert.c

@@ -210,18 +210,12 @@ static void up_dumpstate(void)
    * stack?
    */
 
-  if (sp <= istackbase && sp > istackbase - istacksize)
+  if (sp < istackbase && sp > istackbase - istacksize)
     {
       /* Yes.. dump the interrupt stack */
 
+      _alert("Interrupt Stack\n", sp);
       up_stackdump(sp, istackbase);
-
-      /* Extract the user stack pointer which should lie
-       * at the base of the interrupt stack.
-       */
-
-      sp = g_intstackbase;
-      _alert("sp:     %08x\n", sp);
     }
   else if (CURRENT_REGS)
     {
@@ -229,6 +223,17 @@ static void up_dumpstate(void)
       up_stackdump(istackbase - istacksize, istackbase);
     }
 
+  /* Extract the user stack pointer if we are in an interrupt handler.
+   * If we are not in an interrupt handler.  Then sp is the user stack
+   * pointer (and the above range check should have failed).
+   */
+
+  if (CURRENT_REGS)
+    {
+      sp = CURRENT_REGS[REG_R13];
+      _alert("User sp: %08x\n", sp);
+    }
+
   /* Show user stack info */
 
   _alert("User stack:\n");

arch/arm/src/arm/arm_vectors.S

@@ -132,7 +132,7 @@ arm_vectorirq:
 
 #if CONFIG_ARCH_INTERRUPTSTACK > 3
 	ldr	sp, .Lirqstackbase	/* SP = interrupt stack base */
-	str	r0, [sp]		/* Save the user stack pointer */
+	str	r0, [sp, #-4]!		/* Save the xcp address at SP-4 then update SP */
 	bl	arm_decodeirq		/* Call the handler */
 	ldr	sp, [sp]		/* Restore the user stack pointer */
 #else
@@ -432,13 +432,13 @@ arm_vectorfiq:
 
 #if CONFIG_ARCH_INTERRUPTSTACK > 3
 	.bss
-	.align	4
+	.balign	4
 	.globl	g_intstackalloc
 	.type	g_intstackalloc, object
 	.globl	g_intstackbase
 	.type	g_intstackbase, object
 g_intstackalloc:
-	.skip	((CONFIG_ARCH_INTERRUPTSTACK & ~3) - 4)
+	.skip	(CONFIG_ARCH_INTERRUPTSTACK & ~3)
 g_intstackbase:
 	.skip	4
 	.size	g_intstackbase, 4

arch/arm/src/armv6-m/arm_assert.c

@@ -247,7 +247,7 @@ static void up_dumpstate(void)
    * stack?
    */
 
-  if (sp <= istackbase && sp > istackbase - istacksize)
+  if (sp < istackbase && sp > istackbase - istacksize)
     {
       /* Yes.. dump the interrupt stack */
 

arch/arm/src/armv6-m/arm_exception.S

@@ -270,7 +270,7 @@ exception_common:
 	.bss
 	.global	g_intstackalloc
 	.global g_intstackbase
-	.align	4
+	.balign	4
 g_intstackalloc:
 	.skip	(CONFIG_ARCH_INTERRUPTSTACK & ~3)
 g_intstackbase:

arch/arm/src/armv7-a/arm_assert.c

@@ -252,7 +252,7 @@ static void up_dumpstate(void)
   if (rtcb->xcp.kstack)
     {
       kstackbase = (uint32_t)rtcb->xcp.kstack +
-                   CONFIG_ARCH_KERNEL_STACKSIZE - 4;
+                   CONFIG_ARCH_KERNEL_STACKSIZE;
 
       _alert("Kernel stack:\n");
       _alert("  base: %08x\n", kstackbase);
@@ -265,24 +265,10 @@ static void up_dumpstate(void)
 
   if (sp > istackbase - istacksize && sp < istackbase)
     {
-      uint32_t *stackbase;
-
       /* Yes.. dump the interrupt stack */
 
       _alert("Interrupt Stack\n", sp);
       up_stackdump(sp, istackbase);
-
-      /* Extract the user stack pointer which should lie
-       * at the base of the interrupt stack.
-       */
-
-#ifdef CONFIG_SMP
-      stackbase = (uint32_t *)arm_intstack_base();
-#else
-      stackbase = (uint32_t *)&g_intstackbase;
-#endif
-      sp        = *stackbase;
-      _alert("User sp: %08x\n", sp);
     }
   else if (CURRENT_REGS)
     {
@@ -291,6 +277,17 @@ static void up_dumpstate(void)
     }
 #endif
 
+  /* Extract the user stack pointer if we are in an interrupt handler.
+   * If we are not in an interrupt handler.  Then sp is the user stack
+   * pointer (and the above range check should have failed).
+   */
+
+  if (CURRENT_REGS)
+    {
+      sp = CURRENT_REGS[REG_R13];
+      _alert("User sp: %08x\n", sp);
+    }
+
   /* Dump the user stack if the stack pointer lies within the allocated user
    * stack memory.
    */

arch/arm/src/armv7-a/arm_cpuhead.S

@@ -420,12 +420,13 @@ __cpu3_start:
 	 */
 
 	adr		r3, .Lstkinit
-	ldmia	r3, {r0, r1, r2}	/* R0 = start of IDLE stack; R1 = Size of stack; R2 = coloration */
+	mov		r0, sp		/* R0 = end of IDLE stack */
+	ldmia		r3, {r1, r2}	/* R1 = Size of stack; R2 = coloration */
 
 1:								/* Top of the loop */
 	sub		r1, r1, #1			/* R1 = Number of words remaining */
 	cmp		r1, #0				/* Check (nwords == 0) */
-	str		r2, [r0], #4		/* Save stack color word, increment stack address */
+	str		r2, [r0, #-4]!		/* Save stack color word, increment stack address */
 	bne		1b					/* Bottom of the loop */
 #endif
 
@@ -494,14 +495,5 @@ g_cpu3_idlestack:
 #endif /* CONFIG_SMP_NCPUS > 3 */
 #endif /* CONFIG_SMP_NCPUS > 2 */
 #endif /* CONFIG_SMP_NCPUS > 1 */
-
-	.align	8
-	.globl	g_idle_topstack
-	.type	g_idle_topstack, object
-
-g_idle_topstack:
-	.long	_enoinit
-	.size	g_idle_topstack, .-g_idle_topstack
-
 #endif /* CONFIG_SMP */
 	.end

arch/arm/src/armv7-a/arm_cpuidlestack.c

@@ -133,10 +133,9 @@ int up_cpu_idlestack(int cpu, FAR struct tcb_s *tcb, size_t stack_size)
 
   /* Get the top of the stack */
 
-
   stack_alloc          = (uintptr_t)g_cpu_stackalloc[cpu];
   DEBUGASSERT(stack_alloc != 0 && STACK_ISALIGNED(stack_alloc));
-  top_of_stack         = stack_alloc + SMP_STACK_TOP;
+  top_of_stack         = stack_alloc + SMP_STACK_SIZE;
 
   tcb->adj_stack_size  = SMP_STACK_SIZE;
   tcb->stack_alloc_ptr = (FAR uint32_t *)stack_alloc;

arch/arm/src/armv7-a/arm_cpustart.c

@@ -171,10 +171,6 @@ int up_cpu_start(int cpu)
   sched_note_cpu_start(this_task(), cpu);
 #endif
 
-  /* Make the content of CPU0 L1 cache has been written to coherent L2 */
-
-  cp15_clean_dcache(CONFIG_RAM_START, CONFIG_RAM_END - 1);
-
   /* Execute SGI1 */
 
   return arm_cpu_sgi(GIC_IRQ_SGI1, (1 << cpu));

arch/arm/src/armv7-a/arm_head.S

@@ -754,6 +754,8 @@ arm_data_initialize:
 .Lstackpointer:
 #ifdef CONFIG_BOOT_SDRAM_DATA
 	.long	IDLE_STACK_VBASE+CONFIG_IDLETHREAD_STACKSIZE-4
+#elif defined(CONFIG_SMP)
+	.long	_enoinit+CONFIG_IDLETHREAD_STACKSIZE-4
 #else
 	.long	_ebss+CONFIG_IDLETHREAD_STACKSIZE-4
 #endif
@@ -773,6 +775,8 @@ arm_data_initialize:
 .Lstkinit:
 #ifdef CONFIG_BOOT_SDRAM_DATA
 	.long	IDLE_STACK_VBASE		/* Beginning of the IDLE stack, then words of IDLE stack */
+#elif defined(CONFIG_SMP)
+	.long	_enoinit
 #else
 	.long	_ebss					/* Beginning of the IDLE stack, then words of IDLE stack */
 #endif
@@ -785,7 +789,6 @@ arm_data_initialize:
  * Data section variables
  ***************************************************************************/
 
-#ifndef CONFIG_SMP
 	/* This global variable is unsigned long g_idle_topstack and is
 	 * exported from here only because of its coupling to .Linitparms
 	 * above.
@@ -800,10 +803,11 @@ g_idle_topstack:
 
 #ifdef CONFIG_BOOT_SDRAM_DATA
 	.long	IDLE_STACK_VBASE+CONFIG_IDLETHREAD_STACKSIZE
+#elif defined(CONFIG_SMP)
+	.long	_enoinit+CONFIG_IDLETHREAD_STACKSIZE
 #else
 	.long	_ebss+CONFIG_IDLETHREAD_STACKSIZE
 #endif
 	.size	g_idle_topstack, .-g_idle_topstack
-#endif
 	.end
 #endif

arch/arm/src/armv7-a/arm_l2cc_pl310.c

@@ -1,4 +1,4 @@
-/************************************************************************************
+/****************************************************************************
  * arch/arm/src/armv7-a/chip/arm-l2cc_pl310.c
  *
  *   Copyright (C) 2014, 2016 Gregory Nutt. All rights reserved.
@@ -36,7 +36,7 @@
  * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  * POSSIBILITY OF SUCH DAMAGE.
  *
- ************************************************************************************/
+ ****************************************************************************/
 
 /****************************************************************************
  * Included Files
@@ -59,13 +59,15 @@
 /****************************************************************************
  * Pre-processor Definitions
  ****************************************************************************/
-/* Configuration ***********************************************************/
+
+/* Configuration ************************************************************/
+
 /* Number of ways depends on ARM configuration */
 
 #if defined(CONFIG_ARMV7A_ASSOCIATIVITY_8WAY)
 #  define PL310_NWAYS      8
 #  define PL310_WAY_MASK   0x000000ff
-#elif defined(CONFIG_ARMV7A_ASSOCIATIVITY_8WAY)
+#elif defined(CONFIG_ARMV7A_ASSOCIATIVITY_16WAY)
 #  define PL310_NWAYS 16
 #  define PL310_WAY_MASK   0x0000ffff
 #else
@@ -315,38 +317,45 @@ void arm_l2ccinitialize(void)
 
   /* Make sure that this is a PL310 cache, version r3p2.
    *
-   * REVISIT: The SAMA5D4 is supposed to report its ID as 0x410000C8 which is
-   * r3p2, but the chip that I have actually* reports 0x410000C9 which is some
-   * later revision.
+   * REVISIT: The SAMA5D4 is supposed to report its ID as 0x410000C8 which
+   * is r3p2, but the chip that I have actually* reports 0x410000C9 which
+   * is some later revision.
    */
 
-  //DEBUGASSERT((getreg32(L2CC_IDR) & L2CC_IDR_REV_MASK) == L2CC_IDR_REV_R3P2);
+  /* DEBUGASSERT((getreg32(L2CC_IDR) & L2CC_IDR_REV_MASK) ==
+   *             L2CC_IDR_REV_R3P2);
+   */
 
   /* Make sure that actual cache configuration agrees with the configured
    * cache configuration.
    */
 
-
 #if defined(CONFIG_ARMV7A_ASSOCIATIVITY_8WAY)
   DEBUGASSERT((getreg32(L2CC_ACR) & L2CC_ACR_ASS) == 0);
 #elif defined(CONFIG_ARMV7A_ASSOCIATIVITY_16WAY)
-  DEBUGASSERT((getreg32(L2CC_ACR) & L2CC_ACR_ASS) == 1);
+  DEBUGASSERT((getreg32(L2CC_ACR) & L2CC_ACR_ASS) == L2CC_ACR_ASS);
 #else
 #  error No associativity selected
 #endif
 
 #if defined(CONFIG_ARMV7A_WAYSIZE_16KB)
-  DEBUGASSERT((getreg32(L2CC_ACR) & L2CC_ACR_WAYSIZE_MASK) == L2CC_ACR_WAYSIZE_16KB);
+  DEBUGASSERT((getreg32(L2CC_ACR) & L2CC_ACR_WAYSIZE_MASK) ==
+              L2CC_ACR_WAYSIZE_16KB);
 #elif defined(CONFIG_ARMV7A_WAYSIZE_32KB)
-  DEBUGASSERT((getreg32(L2CC_ACR) & L2CC_ACR_WAYSIZE_MASK) == L2CC_ACR_WAYSIZE_32KB);
+  DEBUGASSERT((getreg32(L2CC_ACR) & L2CC_ACR_WAYSIZE_MASK) ==
+              L2CC_ACR_WAYSIZE_32KB);
 #elif defined(CONFIG_ARMV7A_WAYSIZE_64KB)
-  DEBUGASSERT((getreg32(L2CC_ACR) & L2CC_ACR_WAYSIZE_MASK) == L2CC_ACR_WAYSIZE_64KB);
+  DEBUGASSERT((getreg32(L2CC_ACR) & L2CC_ACR_WAYSIZE_MASK) ==
+              L2CC_ACR_WAYSIZE_64KB);
 #elif defined(CONFIG_ARMV7A_WAYSIZE_128KB)
-  DEBUGASSERT((getreg32(L2CC_ACR) & L2CC_ACR_WAYSIZE_MASK) == L2CC_ACR_WAYSIZE_128KB);
+  DEBUGASSERT((getreg32(L2CC_ACR) & L2CC_ACR_WAYSIZE_MASK) ==
+              L2CC_ACR_WAYSIZE_128KB);
 #elif defined(CONFIG_ARMV7A_WAYSIZE_256KB)
-  DEBUGASSERT((getreg32(L2CC_ACR) & L2CC_ACR_WAYSIZE_MASK) == L2CC_ACR_WAYSIZE_256KB);
+  DEBUGASSERT((getreg32(L2CC_ACR) & L2CC_ACR_WAYSIZE_MASK) ==
+              L2CC_ACR_WAYSIZE_256KB);
 #elif defined(CONFIG_ARMV7A_WAYSIZE_512KB)
-  DEBUGASSERT((getreg32(L2CC_ACR) & L2CC_ACR_WAYSIZE_MASK) == L2CC_ACR_WAYSIZE_512KB);
+  DEBUGASSERT((getreg32(L2CC_ACR) & L2CC_ACR_WAYSIZE_MASK) ==
+              L2CC_ACR_WAYSIZE_512KB);
 #else
 #  error No way size selected
 #endif

arch/arm/src/armv7-a/arm_vectors.S

@@ -261,7 +261,7 @@ arm_vectorirq:
 	/* Call arm_decodeirq() on the interrupt stack */
 
 	setirqstack r1, r3				/* SP = IRQ stack top */
-	str		r0, [sp]				/* Save the user stack pointer */
+	str		r0, [sp, #-4]!			/* Save the xcp address at SP-4 then update SP */
 	mov		r4, sp					/* Save the SP in a preserved register */
 	bic		sp, sp, #7				/* Force 8-byte alignment */
 	bl		arm_decodeirq			/* Call the handler */
@@ -1004,7 +1004,7 @@ arm_vectorfiq:
 
 #if CONFIG_ARCH_INTERRUPTSTACK > 7
 	setfiqstack r1, r4				/* SP = FIQ stack top */
-	str		r0, [sp]				/* Save the user stack pointer */
+	str		r0, [sp, #-4]!			/* Save the xcp address at SP-4 then update SP */
 	mov		r4, sp					/* Save the SP in a preserved register */
 	bic		sp, sp, #7				/* Force 8-byte alignment */
 	bl		arm_decodefiq			/* Call the handler */
@@ -1072,7 +1072,7 @@ arm_vectorfiq:
 
 #if !defined(CONFIG_SMP) && CONFIG_ARCH_INTERRUPTSTACK > 7
 	.bss
-	.align	4
+	.balign	8
 
 	.globl	g_intstackalloc
 	.type	g_intstackalloc, object
@@ -1080,7 +1080,7 @@ arm_vectorfiq:
 	.type	g_intstackbase, object
 
 g_intstackalloc:
-	.skip	((CONFIG_ARCH_INTERRUPTSTACK & ~7) - 4)
+	.skip	((CONFIG_ARCH_INTERRUPTSTACK + 4) & ~7)
 g_intstackbase:
 	.skip	4
 	.size	g_intstackbase, 4
@@ -1096,7 +1096,7 @@ g_intstackbase:
 	.type	g_fiqstackbase, object
 
 g_fiqstackalloc:
-	.skip	((CONFIG_ARCH_INTERRUPTSTACK & ~7) - 4)
+	.skip	((CONFIG_ARCH_INTERRUPTSTACK + 4) & ~7)
 g_fiqstackbase:
 	.skip	4
 	.size	g_fiqstackbase, 4

arch/arm/src/armv7-a/l2cc_pl310.h

@@ -52,11 +52,12 @@
  * header file as L2CC_VBASE.
  */
 
-#include "chip/chip.h"
+#include "chip.h"
 
 /************************************************************************************
  * Pre-processor Definitions
  ************************************************************************************/
+
 /* General Definitions **************************************************************/
 
 #define PL310_CACHE_LINE_SIZE      32
@@ -110,7 +111,7 @@
 
 #define L2CC_DLKR_OFFSET(n)        (0x0900 + ((n) << 3)) /* Data Lockdown Register */
 #define L2CC_ILKR_OFFSET(n)        (0x0904 + ((n) << 3)) /* Instruction Lockdown Register */
-                                          /* 0x0940-0x0f4c Reserved */
+                                                         /* 0x0940-0x0f4c Reserved */
 #ifdef CONFIG_PL310_LOCKDOWN_BY_LINE
 #  define L2CC_LKLN_OFFSET         0x0950 /* Lock Line Enable Register */
 #  define L2CC_UNLKW_OFFSET        0x0954 /* Unlock Way Register */
@@ -170,23 +171,23 @@
 /* Cache ID Register (32-bit ID) */
 
 #define L2CC_IDR_REV_MASK          0x0000003f
-#  define L2CC_IDR_REV_R0P0        0x00000000
-#  define L2CC_IDR_REV_R1P0        0x00000002
-#  define L2CC_IDR_REV_R2P0        0x00000004
-#  define L2CC_IDR_REV_R3P0        0x00000005
-#  define L2CC_IDR_REV_R3P1        0x00000006
-#  define L2CC_IDR_REV_R3P2        0x00000008
+#define L2CC_IDR_REV_R0P0          0x00000000
+#define L2CC_IDR_REV_R1P0          0x00000002
+#define L2CC_IDR_REV_R2P0          0x00000004
+#define L2CC_IDR_REV_R3P0          0x00000005
+#define L2CC_IDR_REV_R3P1          0x00000006
+#define L2CC_IDR_REV_R3P2          0x00000008
 
 /* Cache Type Register */
 
 #define L2CC_TYPR_IL2ASS           (1 << 6)  /* Bit 6:  Instruction L2 Cache Associativity */
 #define L2CC_TYPR_IL2WSIZE_SHIFT   (8)       /* Bits 8-10: Instruction L2 Cache Way Size */
 #define L2CC_TYPR_IL2WSIZE_MASK    (7 << L2CC_TYPR_IL2WSIZE_SHIFT)
-#  define L2CC_TYPR_IL2WSIZE(n)    ((uint32_t)(n) << L2CC_TYPR_IL2WSIZE_SHIFT)
+#define L2CC_TYPR_IL2WSIZE(n)      ((uint32_t)(n) << L2CC_TYPR_IL2WSIZE_SHIFT)
 #define L2CC_TYPR_DL2ASS           (1 << 18) /* Bit 18: Data L2 Cache Associativity */
 #define L2CC_TYPR_DL2WSIZE_SHIFT   (20)      /* Bits 20-22: Data L2 Cache Way Size */
 #define L2CC_TYPR_DL2WSIZE_MASK    (7 << L2CC_TYPR_DL2WSIZE_SHIFT)
-#  define L2CC_TYPR_DL2WSIZE(n)    ((uint32_t)(n) << L2CC_TYPR_DL2WSIZE_SHIFT)
+#define L2CC_TYPR_DL2WSIZE(n)      ((uint32_t)(n) << L2CC_TYPR_DL2WSIZE_SHIFT)
 
 /* Control Register */
 
@@ -202,21 +203,22 @@
 #define L2CC_ACR_ASS               (1 << 16) /* Bit 16: Associativity */
 #define L2CC_ACR_WAYSIZE_SHIFT     (17)      /* Bits 17-19: Way Size */
 #define L2CC_ACR_WAYSIZE_MASK      (7 << L2CC_ACR_WAYSIZE_SHIFT)
-#  define L2CC_ACR_WAYSIZE_16KB    (1 << L2CC_ACR_WAYSIZE_SHIFT)
-#  define L2CC_ACR_WAYSIZE_32KB    (2 << L2CC_ACR_WAYSIZE_SHIFT)
-#  define L2CC_ACR_WAYSIZE_64KB    (3 << L2CC_ACR_WAYSIZE_SHIFT)
-#  define L2CC_ACR_WAYSIZE_128KB   (4 << L2CC_ACR_WAYSIZE_SHIFT)
-#  define L2CC_ACR_WAYSIZE_256KB   (5 << L2CC_ACR_WAYSIZE_SHIFT)
-#  define L2CC_ACR_WAYSIZE_512KB   (6 << L2CC_ACR_WAYSIZE_SHIFT)
+#define L2CC_ACR_WAYSIZE_16KB      (1 << L2CC_ACR_WAYSIZE_SHIFT)
+#define L2CC_ACR_WAYSIZE_32KB      (2 << L2CC_ACR_WAYSIZE_SHIFT)
+#define L2CC_ACR_WAYSIZE_64KB      (3 << L2CC_ACR_WAYSIZE_SHIFT)
+#define L2CC_ACR_WAYSIZE_128KB     (4 << L2CC_ACR_WAYSIZE_SHIFT)
+#define L2CC_ACR_WAYSIZE_256KB     (5 << L2CC_ACR_WAYSIZE_SHIFT)
+#define L2CC_ACR_WAYSIZE_512KB     (6 << L2CC_ACR_WAYSIZE_SHIFT)
 #define L2CC_ACR_EMBEN             (1 << 20) /* Bit 20: Event Monitor Bus Enable */
 #define L2CC_ACR_PEN               (1 << 21) /* Bit 21: Parity Enable */
 #define L2CC_ACR_SAOEN             (1 << 22) /* Bit 22: Shared Attribute Override Enable */
 #define L2CC_ACR_FWA_SHIFT         (23)      /* Bits 23-24:  Force Write Allocate */
 #define L2CC_ACR_FWA_MASK          (3 << L2CC_ACR_FWA_SHIFT)
-#  define L2CC_ACR_FWA_AWCACHE     (0 << L2CC_ACR_FWA_SHIFT) /* Use AWCACHE attributes for WA */
-#  define L2CC_ACR_FWA_NOALLOC     (1 << L2CC_ACR_FWA_SHIFT) /* No allocate */
-#  define L2CC_ACR_FWA_OVERRIDE    (2 << L2CC_ACR_FWA_SHIFT) /* Override AWCACHE attributes */
-#  define L2CC_ACR_FWA_MAPPED      (3 << L2CC_ACR_FWA_SHIFT) /* Internally mapped to 00 */
+#define L2CC_ACR_FWA_AWCACHE       (0 << L2CC_ACR_FWA_SHIFT) /* Use AWCACHE attributes for WA */
+#define L2CC_ACR_FWA_NOALLOC       (1 << L2CC_ACR_FWA_SHIFT) /* No allocate */
+#define L2CC_ACR_FWA_OVERRIDE      (2 << L2CC_ACR_FWA_SHIFT) /* Override AWCACHE attributes */
+#define L2CC_ACR_FWA_MAPPED        (3 << L2CC_ACR_FWA_SHIFT) /* Internally mapped to 00 */
+
 #define L2CC_ACR_CRPOL             (1 << 25) /* Bit 25: Cache Replacement Policy */
 #define L2CC_ACR_NSLEN             (1 << 26) /* Bit 26: Non-Secure Lockdown Enable */
 #define L2CC_ACR_NSIAC             (1 << 27) /* Bit 27: Non-Secure Interrupt Access Control */
@@ -230,25 +232,25 @@
 
 #define L2CC_TRCR_TSETLAT_SHIFT    (0)       /* Bits 0-2: Setup Latency */
 #define L2CC_TRCR_TSETLAT_MASK     (7 << L2CC_TRCR_TSETLAT_SHIFT)
-#  define L2CC_TRCR_TSETLAT(n)     ((uint32_t)(n) << L2CC_TRCR_TSETLAT_SHIFT)
+#define L2CC_TRCR_TSETLAT(n)       ((uint32_t)(n) << L2CC_TRCR_TSETLAT_SHIFT)
 #define L2CC_TRCR_TRDLAT_SHIFT     (4)       /* Bits 4-6: Read Access Latency */
 #define L2CC_TRCR_TRDLAT_MASK      (7 << L2CC_TRCR_TRDLAT_SHIFT)
-#  define L2CC_TRCR_TRDLAT(n)      ((uint32_t)(n) << L2CC_TRCR_TRDLAT_SHIFT)
+#define L2CC_TRCR_TRDLAT(n)        ((uint32_t)(n) << L2CC_TRCR_TRDLAT_SHIFT)
 #define L2CC_TRCR_TWRLAT_SHIFT     (8)       /* Bits 8-10: Write Access Latency */
 #define L2CC_TRCR_TWRLAT_MASK      (7 << L2CC_TRCR_TWRLAT_SHIFT)
-#  define L2CC_TRCR_TWRLAT(n)      ((uint32_t)(n) << L2CC_TRCR_TWRLAT_SHIFT)
+#define L2CC_TRCR_TWRLAT(n)        ((uint32_t)(n) << L2CC_TRCR_TWRLAT_SHIFT)
 
 /* Data RAM Control Register */
 
 #define L2CC_DRCR_DSETLAT_SHIFT    (0)       /* Bits 0-2: Setup Latency */
 #define L2CC_DRCR_DSETLAT_MASK     (7 << L2CC_DRCR_DSETLAT_SHIFT)
-#  define L2CC_DRCR_DSETLAT(n)     ((uint32_t)(n) << L2CC_DRCR_DSETLAT_SHIFT)
+#define L2CC_DRCR_DSETLAT(n)       ((uint32_t)(n) << L2CC_DRCR_DSETLAT_SHIFT)
 #define L2CC_DRCR_DRDLAT_SHIFT     (4)       /* Bits 4-6: Read Access Latency */
 #define L2CC_DRCR_DRDLAT_MASK      (7 << L2CC_DRCR_DRDLAT_SHIFT)
-#  define L2CC_DRCR_DRDLAT(n)      ((uint32_t)(n) << L2CC_DRCR_DRDLAT_SHIFT)
+#define L2CC_DRCR_DRDLAT(n)        ((uint32_t)(n) << L2CC_DRCR_DRDLAT_SHIFT)
 #define L2CC_DRCR_DWRLAT_SHIFT     (8)       /* Bits 8-10: Write Access Latency */
 #define L2CC_DRCR_DWRLAT_MASK      (7 << L2CC_DRCR_DWRLAT_SHIFT)
-#  define L2CC_DRCR_DWRLAT(n)      ((uint32_t)(n) << L2CC_DRCR_DWRLAT_SHIFT)
+#define L2CC_DRCR_DWRLAT(n)        ((uint32_t)(n) << L2CC_DRCR_DWRLAT_SHIFT)
 
 /* Event Counter Control Register */
 
@@ -258,60 +260,60 @@
 
 /* Event Counter 1 Configuration Register */
 
-
-#define L2CC_ECFGR1_EIGEN_SHIFT    (0)       /* Bits 0-1: Event Counter Interrupt Generation */
-#define L2CC_ECFGR1_EIGEN_MASK     (3 << L2CC_ECFGR1_EIGEN_SHIFT)
-#  define L2CC_ECFGR1_EIGEN_INTDIS    (0 << L2CC_ECFGR1_EIGEN_SHIFT) /* Disables (default) */
-#  define L2CC_ECFGR1_EIGEN_INTENINCR (1 << L2CC_ECFGR1_EIGEN_SHIFT) /* Enables with Increment condition */
-#  define L2CC_ECFGR1_EIGEN_INTENOVER (2 << L2CC_ECFGR1_EIGEN_SHIFT) /* Enables with Overflow condition */
-#  define L2CC_ECFGR1_EIGEN_INTGENDIS (3 << L2CC_ECFGR1_EIGEN_SHIFT) /* Disables Interrupt generation */
-#define L2CC_ECFGR1_ESRC_SHIFT     (2)       /* Bits 2-5: Event Counter Source */
-#define L2CC_ECFGR1_ESRC_MASK      (15 << L2CC_ECFGR1_ESRC_SHIFT)
-#  define L2CC_ECFGR1_ESRC_CNTDIS     (0 << L2CC_ECFGR1_ESRC_SHIFT)  /* Counter Disabled */
-#  define L2CC_ECFGR1_ESRC_CO         (1 << L2CC_ECFGR1_ESRC_SHIFT)  /* Source is CO */
-#  define L2CC_ECFGR1_ESRC_DRHIT      (2 << L2CC_ECFGR1_ESRC_SHIFT)  /* Source is DRHIT */
-#  define L2CC_ECFGR1_ESRC_DRREQ      (3 << L2CC_ECFGR1_ESRC_SHIFT)  /* Source is DRREQ */
-#  define L2CC_ECFGR1_ESRC_DWHIT      (4 << L2CC_ECFGR1_ESRC_SHIFT)  /* Source is DWHIT */
-#  define L2CC_ECFGR1_ESRC_DWREQ      (5 << L2CC_ECFGR1_ESRC_SHIFT)  /* Source is DWREQ */
-#  define L2CC_ECFGR1_ESRC_DWTREQ     (6 << L2CC_ECFGR1_ESRC_SHIFT)  /* Source is DWTREQ */
-#  define L2CC_ECFGR1_ESRC_IRHIT      (7 << L2CC_ECFGR1_ESRC_SHIFT)  /* Source is IRHIT */
-#  define L2CC_ECFGR1_ESRC_IRREQ      (8 << L2CC_ECFGR1_ESRC_SHIFT)  /* Source is IRREQ */
-#  define L2CC_ECFGR1_ESRC_WA         (9 << L2CC_ECFGR1_ESRC_SHIFT)  /* Source is WA */
-#  define L2CC_ECFGR1_ESRC_IPFALLOC   (10 << L2CC_ECFGR1_ESRC_SHIFT) /* Source is IPFALLOC */
-#  define L2CC_ECFGR1_ESRC_EPFHIT     (11 << L2CC_ECFGR1_ESRC_SHIFT) /* Source is EPFHIT */
-#  define L2CC_ECFGR1_ESRC_EPFALLOC   (12 << L2CC_ECFGR1_ESRC_SHIFT) /* Source is EPFALLOC */
-#  define L2CC_ECFGR1_ESRC_SRRCVD     (13 << L2CC_ECFGR1_ESRC_SHIFT) /* Source is SRRCVD */
-#  define L2CC_ECFGR1_ESRC_SRCONF     (14 << L2CC_ECFGR1_ESRC_SHIFT) /* Source is SRCONF */
-#  define L2CC_ECFGR1_ESRC_EPFRCVD    (15 << L2CC_ECFGR1_ESRC_SHIFT) /* Source is EPFRCVD */
+#define L2CC_ECFGR1_EIGEN_SHIFT     (0)       /* Bits 0-1: Event Counter Interrupt Generation */
+#define L2CC_ECFGR1_EIGEN_MASK      (3 << L2CC_ECFGR1_EIGEN_SHIFT)
+#define L2CC_ECFGR1_EIGEN_INTDIS    (0 << L2CC_ECFGR1_EIGEN_SHIFT) /* Disables (default) */
+#define L2CC_ECFGR1_EIGEN_INTENINCR (1 << L2CC_ECFGR1_EIGEN_SHIFT) /* Enables with Increment condition */
+#define L2CC_ECFGR1_EIGEN_INTENOVER (2 << L2CC_ECFGR1_EIGEN_SHIFT) /* Enables with Overflow condition */
+#define L2CC_ECFGR1_EIGEN_INTGENDIS (3 << L2CC_ECFGR1_EIGEN_SHIFT) /* Disables Interrupt generation */
+#define L2CC_ECFGR1_ESRC_SHIFT      (2)                            /* Bits 2-5: Event Counter Source */
+#define L2CC_ECFGR1_ESRC_MASK       (15 << L2CC_ECFGR1_ESRC_SHIFT)
+#define L2CC_ECFGR1_ESRC_CNTDIS     (0 << L2CC_ECFGR1_ESRC_SHIFT)  /* Counter Disabled */
+#define L2CC_ECFGR1_ESRC_CO         (1 << L2CC_ECFGR1_ESRC_SHIFT)  /* Source is CO */
+#define L2CC_ECFGR1_ESRC_DRHIT      (2 << L2CC_ECFGR1_ESRC_SHIFT)  /* Source is DRHIT */
+#define L2CC_ECFGR1_ESRC_DRREQ      (3 << L2CC_ECFGR1_ESRC_SHIFT)  /* Source is DRREQ */
+#define L2CC_ECFGR1_ESRC_DWHIT      (4 << L2CC_ECFGR1_ESRC_SHIFT)  /* Source is DWHIT */
+#define L2CC_ECFGR1_ESRC_DWREQ      (5 << L2CC_ECFGR1_ESRC_SHIFT)  /* Source is DWREQ */
+#define L2CC_ECFGR1_ESRC_DWTREQ     (6 << L2CC_ECFGR1_ESRC_SHIFT)  /* Source is DWTREQ */
+#define L2CC_ECFGR1_ESRC_IRHIT      (7 << L2CC_ECFGR1_ESRC_SHIFT)  /* Source is IRHIT */
+#define L2CC_ECFGR1_ESRC_IRREQ      (8 << L2CC_ECFGR1_ESRC_SHIFT)  /* Source is IRREQ */
+#define L2CC_ECFGR1_ESRC_WA         (9 << L2CC_ECFGR1_ESRC_SHIFT)  /* Source is WA */
+#define L2CC_ECFGR1_ESRC_IPFALLOC   (10 << L2CC_ECFGR1_ESRC_SHIFT) /* Source is IPFALLOC */
+#define L2CC_ECFGR1_ESRC_EPFHIT     (11 << L2CC_ECFGR1_ESRC_SHIFT) /* Source is EPFHIT */
+#define L2CC_ECFGR1_ESRC_EPFALLOC   (12 << L2CC_ECFGR1_ESRC_SHIFT) /* Source is EPFALLOC */
+#define L2CC_ECFGR1_ESRC_SRRCVD     (13 << L2CC_ECFGR1_ESRC_SHIFT) /* Source is SRRCVD */
+#define L2CC_ECFGR1_ESRC_SRCONF     (14 << L2CC_ECFGR1_ESRC_SHIFT) /* Source is SRCONF */
+#define L2CC_ECFGR1_ESRC_EPFRCVD    (15 << L2CC_ECFGR1_ESRC_SHIFT) /* Source is EPFRCVD */
 
 /* Event Counter 0 Configuration Register */
 
-#define L2CC_ECFGR0_EIGEN_SHIFT    (0)       /* Bits 0-1: Event Counter Interrupt Generation */
-#define L2CC_ECFGR0_EIGEN_MASK     (3 << L2CC_ECFGR0_EIGEN_SHIFT)
-#  define L2CC_ECFGR0_EIGEN_INTDIS    (0 << L2CC_ECFGR0_EIGEN_SHIFT) /* Disables (default) */
-#  define L2CC_ECFGR0_EIGEN_INTENINCR (1 << L2CC_ECFGR0_EIGEN_SHIFT) /* Enables with Increment condition */
-#  define L2CC_ECFGR0_EIGEN_INTENOVER (2 << L2CC_ECFGR0_EIGEN_SHIFT) /* Enables with Overflow condition */
-#  define L2CC_ECFGR0_EIGEN_INTGENDIS (3 << L2CC_ECFGR0_EIGEN_SHIFT) /* Disables Interrupt generation */
-#define L2CC_ECFGR0_ESRC_SHIFT     (2)       /* Bits 2-5: Event Counter Source */
-#define L2CC_ECFGR0_ESRC_MASK      (15 << L2CC_ECFGR0_ESRC_SHIFT)
-#  define L2CC_ECFGR0_ESRC_CNTDIS     (0 << L2CC_ECFGR0_ESRC_SHIFT)  /* Counter Disabled */
-#  define L2CC_ECFGR0_ESRC_CO         (1 << L2CC_ECFGR0_ESRC_SHIFT)  /* Source is CO */
-#  define L2CC_ECFGR0_ESRC_DRHIT      (2 << L2CC_ECFGR0_ESRC_SHIFT)  /* Source is DRHIT */
-#  define L2CC_ECFGR0_ESRC_DRREQ      (3 << L2CC_ECFGR0_ESRC_SHIFT)  /* Source is DRREQ */
-#  define L2CC_ECFGR0_ESRC_DWHIT      (4 << L2CC_ECFGR0_ESRC_SHIFT)  /* Source is DWHIT */
-#  define L2CC_ECFGR0_ESRC_DWREQ      (5 << L2CC_ECFGR0_ESRC_SHIFT)  /* Source is DWREQ */
-#  define L2CC_ECFGR0_ESRC_DWTREQ     (6 << L2CC_ECFGR0_ESRC_SHIFT)  /* Source is DWTREQ */
-#  define L2CC_ECFGR0_ESRC_IRHIT      (7 << L2CC_ECFGR0_ESRC_SHIFT)  /* Source is IRHIT */
-#  define L2CC_ECFGR0_ESRC_IRREQ      (8 << L2CC_ECFGR0_ESRC_SHIFT)  /* Source is IRREQ */
-#  define L2CC_ECFGR0_ESRC_WA         (9 << L2CC_ECFGR0_ESRC_SHIFT)  /* Source is WA */
-#  define L2CC_ECFGR0_ESRC_IPFALLOC   (10 << L2CC_ECFGR0_ESRC_SHIFT) /* Source is IPFALLOC */
-#  define L2CC_ECFGR0_ESRC_EPFHIT     (11 << L2CC_ECFGR0_ESRC_SHIFT) /* Source is EPFHIT */
-#  define L2CC_ECFGR0_ESRC_EPFALLOC   (12 << L2CC_ECFGR0_ESRC_SHIFT) /* Source is EPFALLOC */
-#  define L2CC_ECFGR0_ESRC_SRRCVD     (13 << L2CC_ECFGR0_ESRC_SHIFT) /* Source is SRRCVD */
-#  define L2CC_ECFGR0_ESRC_SRCONF     (14 << L2CC_ECFGR0_ESRC_SHIFT) /* Source is SRCONF */
-#  define L2CC_ECFGR0_ESRC_EPFRCVD    (15 << L2CC_ECFGR0_ESRC_SHIFT) /* Source is EPFRCVD */
+#define L2CC_ECFGR0_EIGEN_SHIFT     (0)       /* Bits 0-1: Event Counter Interrupt Generation */
+#define L2CC_ECFGR0_EIGEN_MASK      (3 << L2CC_ECFGR0_EIGEN_SHIFT)
+#define L2CC_ECFGR0_EIGEN_INTDIS    (0 << L2CC_ECFGR0_EIGEN_SHIFT) /* Disables (default) */
+#define L2CC_ECFGR0_EIGEN_INTENINCR (1 << L2CC_ECFGR0_EIGEN_SHIFT) /* Enables with Increment condition */
+#define L2CC_ECFGR0_EIGEN_INTENOVER (2 << L2CC_ECFGR0_EIGEN_SHIFT) /* Enables with Overflow condition */
+#define L2CC_ECFGR0_EIGEN_INTGENDIS (3 << L2CC_ECFGR0_EIGEN_SHIFT) /* Disables Interrupt generation */
+#define L2CC_ECFGR0_ESRC_SHIFT      (2)                            /* Bits 2-5: Event Counter Source */
+#define L2CC_ECFGR0_ESRC_MASK       (15 << L2CC_ECFGR0_ESRC_SHIFT)
+#define L2CC_ECFGR0_ESRC_CNTDIS     (0 << L2CC_ECFGR0_ESRC_SHIFT)  /* Counter Disabled */
+#define L2CC_ECFGR0_ESRC_CO         (1 << L2CC_ECFGR0_ESRC_SHIFT)  /* Source is CO */
+#define L2CC_ECFGR0_ESRC_DRHIT      (2 << L2CC_ECFGR0_ESRC_SHIFT)  /* Source is DRHIT */
+#define L2CC_ECFGR0_ESRC_DRREQ      (3 << L2CC_ECFGR0_ESRC_SHIFT)  /* Source is DRREQ */
+#define L2CC_ECFGR0_ESRC_DWHIT      (4 << L2CC_ECFGR0_ESRC_SHIFT)  /* Source is DWHIT */
+#define L2CC_ECFGR0_ESRC_DWREQ      (5 << L2CC_ECFGR0_ESRC_SHIFT)  /* Source is DWREQ */
+#define L2CC_ECFGR0_ESRC_DWTREQ     (6 << L2CC_ECFGR0_ESRC_SHIFT)  /* Source is DWTREQ */
+#define L2CC_ECFGR0_ESRC_IRHIT      (7 << L2CC_ECFGR0_ESRC_SHIFT)  /* Source is IRHIT */
+#define L2CC_ECFGR0_ESRC_IRREQ      (8 << L2CC_ECFGR0_ESRC_SHIFT)  /* Source is IRREQ */
+#define L2CC_ECFGR0_ESRC_WA         (9 << L2CC_ECFGR0_ESRC_SHIFT)  /* Source is WA */
+#define L2CC_ECFGR0_ESRC_IPFALLOC   (10 << L2CC_ECFGR0_ESRC_SHIFT) /* Source is IPFALLOC */
+#define L2CC_ECFGR0_ESRC_EPFHIT     (11 << L2CC_ECFGR0_ESRC_SHIFT) /* Source is EPFHIT */
+#define L2CC_ECFGR0_ESRC_EPFALLOC   (12 << L2CC_ECFGR0_ESRC_SHIFT) /* Source is EPFALLOC */
+#define L2CC_ECFGR0_ESRC_SRRCVD     (13 << L2CC_ECFGR0_ESRC_SHIFT) /* Source is SRRCVD */
+#define L2CC_ECFGR0_ESRC_SRCONF     (14 << L2CC_ECFGR0_ESRC_SHIFT) /* Source is SRCONF */
+#define L2CC_ECFGR0_ESRC_EPFRCVD    (15 << L2CC_ECFGR0_ESRC_SHIFT) /* Source is EPFRCVD */
 
 /* Event Counter 1 Value Register (32-bit value) */
+
 /* Event Counter 0 Value Register (32-bit value) */
 
 /* Interrupt Mask Register, Masked Interrupt Status Register, Raw Interrupt Status
@@ -337,110 +339,110 @@
 #define L2CC_IPALR_C               (1 << 0)  /* Bit 0:  Cache Synchronization Status */
 #define L2CC_IPALR_IDX_SHIFT       (5)       /* Bits 5-13: Index Number */
 #define L2CC_IPALR_IDX_MASK        (0x1ff << L2CC_IPALR_IDX_SHIFT)
-#  define L2CC_IPALR_IDX(n)        ((uint32_t)(n) << L2CC_IPALR_IDX_SHIFT)
+#define L2CC_IPALR_IDX(n)          ((uint32_t)(n) << L2CC_IPALR_IDX_SHIFT)
 #define L2CC_IPALR_TAG_SHIFT       (14)      /* Bits 14-31: Tag Number */
 #define L2CC_IPALR_TAG_MASK        (0x3ffff << L2CC_IPALR_TAG_SHIFT)
-#  define L2CC_IPALR_TAG(n)        ((uint32_t)(n) << L2CC_IPALR_TAG_SHIFT)
+#define L2CC_IPALR_TAG(n)          ((uint32_t)(n) << L2CC_IPALR_TAG_SHIFT)
 
 /* Invalidate Way Register */
 
 #define L2CC_IWR_WAY(n)            (1 << (n)) /* Bist 0-7:  Invalidate Way Number n, n=0..7 */
-#  define L2CC_IWR_WAY0            (1 << 0)   /* Bit 0:  Invalidate Way Number 0 */
-#  define L2CC_IWR_WAY1            (1 << 1)   /* Bit 1:  Invalidate Way Number 1 */
-#  define L2CC_IWR_WAY2            (1 << 2)   /* Bit 2:  Invalidate Way Number 2 */
-#  define L2CC_IWR_WAY3            (1 << 3)   /* Bit 3:  Invalidate Way Number 3 */
-#  define L2CC_IWR_WAY4            (1 << 4)   /* Bit 4:  Invalidate Way Number 4 */
-#  define L2CC_IWR_WAY5            (1 << 5)   /* Bit 5:  Invalidate Way Number 5 */
-#  define L2CC_IWR_WAY6            (1 << 6)   /* Bit 6:  Invalidate Way Number 6 */
-#  define L2CC_IWR_WAY7            (1 << 7)   /* Bit 7:  Invalidate Way Number 7 */
+#define L2CC_IWR_WAY0              (1 << 0)   /* Bit 0:  Invalidate Way Number 0 */
+#define L2CC_IWR_WAY1              (1 << 1)   /* Bit 1:  Invalidate Way Number 1 */
+#define L2CC_IWR_WAY2              (1 << 2)   /* Bit 2:  Invalidate Way Number 2 */
+#define L2CC_IWR_WAY3              (1 << 3)   /* Bit 3:  Invalidate Way Number 3 */
+#define L2CC_IWR_WAY4              (1 << 4)   /* Bit 4:  Invalidate Way Number 4 */
+#define L2CC_IWR_WAY5              (1 << 5)   /* Bit 5:  Invalidate Way Number 5 */
+#define L2CC_IWR_WAY6              (1 << 6)   /* Bit 6:  Invalidate Way Number 6 */
+#define L2CC_IWR_WAY7              (1 << 7)   /* Bit 7:  Invalidate Way Number 7 */
 
 /* Clean Physical Address Line Register */
 
 #define L2CC_CPALR_C               (1 << 0)  /* Bit 0:  Cache Synchronization Status */
 #define L2CC_CPALR_IDX_SHIFT       (5)       /* Bits 5-13: Index number */
 #define L2CC_CPALR_IDX_MASK        (0x1ff << L2CC_CPALR_IDX_SHIFT)
-#  define L2CC_CPALR_IDX(n)        ((uint32_t)(n) << L2CC_CPALR_IDX_SHIFT)
+#define L2CC_CPALR_IDX(n)          ((uint32_t)(n) << L2CC_CPALR_IDX_SHIFT)
 #define L2CC_CPALR_TAG_SHIFT       (14)      /* Bits 14-31: Tag number */
 #define L2CC_CPALR_TAG_MASK        (0x3ffff << L2CC_CPALR_TAG_SHIFT)
-#  define L2CC_CPALR_TAG(n)        ((uint32_t)(n) << L2CC_CPALR_TAG_SHIFT)
+#define L2CC_CPALR_TAG(n)          ((uint32_t)(n) << L2CC_CPALR_TAG_SHIFT)
 
 /* Clean Index Register */
 
 #define L2CC_CIR_C                 (1 << 0)  /* Bit 0:  Cache Synchronization Status */
 #define L2CC_CIR_IDX_SHIFT         (5)       /* Bits 5-13: Index number */
 #define L2CC_CIR_IDX_MASK          (0x1ff << L2CC_CIR_IDX_SHIFT)
-#  define L2CC_CIR_IDX(n)          ((uint32_t)(n) << L2CC_CIR_IDX_SHIFT)
+#define L2CC_CIR_IDX(n)            ((uint32_t)(n) << L2CC_CIR_IDX_SHIFT)
 #define L2CC_CIR_WAY_SHIFT         (28)      /* Bits 28-30: Way number */
 #define L2CC_CIR_WAY_MASK          (7 << L2CC_CIR_WAY_SHIFT)
-#  define L2CC_CIR_WAY(n)          ((uint32_t)(n) << L2CC_CIR_WAY_SHIFT)
+#define L2CC_CIR_WAY(n)            ((uint32_t)(n) << L2CC_CIR_WAY_SHIFT)
 
 /* Clean Way Register */
 
 #define L2CC_CWR_WAY(n)            (1 << (n)) /* Bits 0-7:  Clean Way Number n, n=0..7 */
-#  define L2CC_CWR_WAY0            (1 << 0)   /* Bit 0:  Clean Way Number 0 */
-#  define L2CC_CWR_WAY1            (1 << 1)   /* Bit 1:  Clean Way Number 1 */
-#  define L2CC_CWR_WAY2            (1 << 2)   /* Bit 2:  Clean Way Number 2 */
-#  define L2CC_CWR_WAY3            (1 << 3)   /* Bit 3:  Clean Way Number 3 */
-#  define L2CC_CWR_WAY4            (1 << 4)   /* Bit 4:  Clean Way Number 4 */
-#  define L2CC_CWR_WAY5            (1 << 5)   /* Bit 5:  Clean Way Number 5 */
-#  define L2CC_CWR_WAY6            (1 << 6)   /* Bit 6:  Clean Way Number 6 */
-#  define L2CC_CWR_WAY7            (1 << 7)   /* Bit 7:  Clean Way Number 7 */
+#define L2CC_CWR_WAY0              (1 << 0)   /* Bit 0:  Clean Way Number 0 */
+#define L2CC_CWR_WAY1              (1 << 1)   /* Bit 1:  Clean Way Number 1 */
+#define L2CC_CWR_WAY2              (1 << 2)   /* Bit 2:  Clean Way Number 2 */
+#define L2CC_CWR_WAY3              (1 << 3)   /* Bit 3:  Clean Way Number 3 */
+#define L2CC_CWR_WAY4              (1 << 4)   /* Bit 4:  Clean Way Number 4 */
+#define L2CC_CWR_WAY5              (1 << 5)   /* Bit 5:  Clean Way Number 5 */
+#define L2CC_CWR_WAY6              (1 << 6)   /* Bit 6:  Clean Way Number 6 */
+#define L2CC_CWR_WAY7              (1 << 7)   /* Bit 7:  Clean Way Number 7 */
 
 /* Clean Invalidate Physical Address Line Register */
 
 #define L2CC_CIPALR_C              (1 << 0)  /* Bit 0:  Cache Synchronization Status */
 #define L2CC_CIPALR_IDX_SHIFT      (5)       /* Bits 5-13: Index Number */
 #define L2CC_CIPALR_IDX_MASK       (0x1ff << L2CC_CIPALR_IDX_SHIFT)
-#  define L2CC_CIPALR_IDX(n)       ((uint32_t)(n) << L2CC_CIPALR_IDX_SHIFT)
+#define L2CC_CIPALR_IDX(n)         ((uint32_t)(n) << L2CC_CIPALR_IDX_SHIFT)
 #define L2CC_CIPALR_TAG_SHIFT      (14)      /* Bits 14-31: Tag Number */
 #define L2CC_CIPALR_TAG_MASK       (0x3ffff << L2CC_CIPALR_TAG_SHIFT)
-#  define L2CC_CIPALR_TAG(n)       ((uint32_t)(n) << L2CC_CIPALR_TAG_SHIFT)
+#define L2CC_CIPALR_TAG(n)         ((uint32_t)(n) << L2CC_CIPALR_TAG_SHIFT)
 
 /* Clean Invalidate Index Register */
 
 #define L2CC_CIIR_C                (1 << 0)  /* Bit 0:  Cache Synchronization Status */
 #define L2CC_CIIR_IDX_SHIFT        (5)       /* Bits 5-13: Index Number */
 #define L2CC_CIIR_IDX_MASK         (0x1ff << L2CC_CIIR_IDX_SHIFT)
-#  define L2CC_CIIR_IDX(n)         ((uint32_t)(n) << L2CC_CIIR_IDX_SHIFT)
+#define L2CC_CIIR_IDX(n)           ((uint32_t)(n) << L2CC_CIIR_IDX_SHIFT)
 #define L2CC_CIIR_WAY_SHIFT        (28)      /* Bits 28-30: Way Number */
 #define L2CC_CIIR_WAY_MASK         (7 << L2CC_CIIR_WAY_SHIFT)
-#  define L2CC_CIIR_WAY(n)         ((uint32_t)(n) << L2CC_CIIR_WAY_SHIFT)
+#define L2CC_CIIR_WAY(n)           ((uint32_t)(n) << L2CC_CIIR_WAY_SHIFT)
 
 /* Clean Invalidate Way Register */
 
 #define L2CC_CIWR_WAY(n)           (1 << (n)) /* Bits 0-7:  Clean Invalidate Way Number n, n=1..7 */
-#  define L2CC_CIWR_WAY0           (1 << 0)   /* Bit 0:  Clean Invalidate Way Number 0 */
-#  define L2CC_CIWR_WAY1           (1 << 1)   /* Bit 1:  Clean Invalidate Way Number 1 */
-#  define L2CC_CIWR_WAY2           (1 << 2)   /* Bit 2:  Clean Invalidate Way Number 2 */
-#  define L2CC_CIWR_WAY3           (1 << 3)   /* Bit 3:  Clean Invalidate Way Number 3 */
-#  define L2CC_CIWR_WAY4           (1 << 4)   /* Bit 4:  Clean Invalidate Way Number 4 */
-#  define L2CC_CIWR_WAY5           (1 << 5)   /* Bit 5:  Clean Invalidate Way Number 5 */
-#  define L2CC_CIWR_WAY6           (1 << 6)   /* Bit 6:  Clean Invalidate Way Number 6 */
-#  define L2CC_CIWR_WAY7           (1 << 7)   /* Bit 7:  Clean Invalidate Way Number 7 */
+#define L2CC_CIWR_WAY0             (1 << 0)   /* Bit 0:  Clean Invalidate Way Number 0 */
+#define L2CC_CIWR_WAY1             (1 << 1)   /* Bit 1:  Clean Invalidate Way Number 1 */
+#define L2CC_CIWR_WAY2             (1 << 2)   /* Bit 2:  Clean Invalidate Way Number 2 */
+#define L2CC_CIWR_WAY3             (1 << 3)   /* Bit 3:  Clean Invalidate Way Number 3 */
+#define L2CC_CIWR_WAY4             (1 << 4)   /* Bit 4:  Clean Invalidate Way Number 4 */
+#define L2CC_CIWR_WAY5             (1 << 5)   /* Bit 5:  Clean Invalidate Way Number 5 */
+#define L2CC_CIWR_WAY6             (1 << 6)   /* Bit 6:  Clean Invalidate Way Number 6 */
+#define L2CC_CIWR_WAY7             (1 << 7)   /* Bit 7:  Clean Invalidate Way Number 7 */
 
 /* Data Lockdown Register */
 
 #define L2CC_DLKR_DLK(n)           (1 << (n)) /* Bits 0-7:  Data Lockdown in Way Number n, n=0..7 */
-#  define L2CC_DLKR_DLK0           (1 << 0)   /* Bit 0:  Data Lockdown in Way Number 0 */
-#  define L2CC_DLKR_DLK1           (1 << 1)   /* Bit 1:  Data Lockdown in Way Number 1 */
-#  define L2CC_DLKR_DLK2           (1 << 2)   /* Bit 2:  Data Lockdown in Way Number 2 */
-#  define L2CC_DLKR_DLK3           (1 << 3)   /* Bit 3:  Data Lockdown in Way Number 3 */
-#  define L2CC_DLKR_DLK4           (1 << 4)   /* Bit 4:  Data Lockdown in Way Number 4 */
-#  define L2CC_DLKR_DLK5           (1 << 5)   /* Bit 5:  Data Lockdown in Way Number 5 */
-#  define L2CC_DLKR_DLK6           (1 << 6)   /* Bit 6:  Data Lockdown in Way Number 6 */
-#  define L2CC_DLKR_DLK7           (1 << 7)   /* Bit 7:  Data Lockdown in Way Number 7 */
+#define L2CC_DLKR_DLK0             (1 << 0)   /* Bit 0:  Data Lockdown in Way Number 0 */
+#define L2CC_DLKR_DLK1             (1 << 1)   /* Bit 1:  Data Lockdown in Way Number 1 */
+#define L2CC_DLKR_DLK2             (1 << 2)   /* Bit 2:  Data Lockdown in Way Number 2 */
+#define L2CC_DLKR_DLK3             (1 << 3)   /* Bit 3:  Data Lockdown in Way Number 3 */
+#define L2CC_DLKR_DLK4             (1 << 4)   /* Bit 4:  Data Lockdown in Way Number 4 */
+#define L2CC_DLKR_DLK5             (1 << 5)   /* Bit 5:  Data Lockdown in Way Number 5 */
+#define L2CC_DLKR_DLK6             (1 << 6)   /* Bit 6:  Data Lockdown in Way Number 6 */
+#define L2CC_DLKR_DLK7             (1 << 7)   /* Bit 7:  Data Lockdown in Way Number 7 */
 
 /* Instruction Lockdown Register */
 
 #define L2CC_ILKR_ILK(n)           (1 << (n)) /* Bits 0-7:  Instruction Lockdown in Way Number n, n=0..7 */
-#  define L2CC_ILKR_ILK0           (1 << 0)   /* Bit 0:  Instruction Lockdown in Way Number 0 */
-#  define L2CC_ILKR_ILK1           (1 << 1)   /* Bit 1:  Instruction Lockdown in Way Number 1 */
-#  define L2CC_ILKR_ILK2           (1 << 2)   /* Bit 2:  Instruction Lockdown in Way Number 2 */
-#  define L2CC_ILKR_ILK3           (1 << 3)   /* Bit 3:  Instruction Lockdown in Way Number 3 */
-#  define L2CC_ILKR_ILK4           (1 << 4)   /* Bit 4:  Instruction Lockdown in Way Number 4 */
-#  define L2CC_ILKR_ILK5           (1 << 5)   /* Bit 5:  Instruction Lockdown in Way Number 5 */
-#  define L2CC_ILKR_ILK6           (1 << 6)   /* Bit 6:  Instruction Lockdown in Way Number 6 */
-#  define L2CC_ILKR_ILK7           (1 << 7)   /* Bit 7:  Instruction Lockdown in Way Number 7 */
+#define L2CC_ILKR_ILK0             (1 << 0)   /* Bit 0:  Instruction Lockdown in Way Number 0 */
+#define L2CC_ILKR_ILK1             (1 << 1)   /* Bit 1:  Instruction Lockdown in Way Number 1 */
+#define L2CC_ILKR_ILK2             (1 << 2)   /* Bit 2:  Instruction Lockdown in Way Number 2 */
+#define L2CC_ILKR_ILK3             (1 << 3)   /* Bit 3:  Instruction Lockdown in Way Number 3 */
+#define L2CC_ILKR_ILK4             (1 << 4)   /* Bit 4:  Instruction Lockdown in Way Number 4 */
+#define L2CC_ILKR_ILK5             (1 << 5)   /* Bit 5:  Instruction Lockdown in Way Number 5 */
+#define L2CC_ILKR_ILK6             (1 << 6)   /* Bit 6:  Instruction Lockdown in Way Number 6 */
+#define L2CC_ILKR_ILK7             (1 << 7)   /* Bit 7:  Instruction Lockdown in Way Number 7 */
 
 /* Lock Line Enable Register */
 
@@ -453,8 +455,8 @@
 #ifdef CONFIG_PL310_LOCKDOWN_BY_LINE
 #  define L2CC_UNLKW_WAY_SHIFT     (0)       /* Bits 0-15: Unlock line for corresponding way */
 #  define L2CC_UNLKW_WAY_MASK      (0xffff << L2CC_UNLKW_WAY_SHIFT)
-#    define L2CC_UNLKW_WAY_SET(n)  ((uint32_t)(n) << L2CC_UNLKW_WAY_SHIFT)
-#    define L2CC_UNLKW_WAY_BIT(n)  ((1 << (n)) << L2CC_UNLKW_WAY_SHIFT)
+#  define L2CC_UNLKW_WAY_SET(n)    ((uint32_t)(n) << L2CC_UNLKW_WAY_SHIFT)
+#  define L2CC_UNLKW_WAY_BIT(n)    ((1 << (n)) << L2CC_UNLKW_WAY_SHIFT)
 #endif
 
 /* Address filter start */
@@ -480,7 +482,7 @@
 
 #define L2CC_PCR_SHIFT             (0)       /* Bits 0-4: Prefetch Offset */
 #define L2CC_PCR_MASK              (31 << L2CC_PCR_SHIFT)
-#  define L2CC_PCR_PREFETCH(n)     ((uint32_t)(n) << L2CC_PCR_SHIFT)
+#define L2CC_PCR_PREFETCH(n)       ((uint32_t)(n) << L2CC_PCR_SHIFT)
 #define L2CC_PCR_NSIDEN            (1 << 21) /* Bit 21: Not Same ID on Exclusive Sequence Enable */
 #define L2CC_PCR_IDLEN             (1 << 23) /* Bit 23: INCR Double Linefill Enable */
 #define L2CC_PCR_PDEN              (1 << 24) /* Bit 24: Prefetch Drop Enable */

arch/arm/src/armv7-a/mmu.h

@@ -1,4 +1,4 @@
-/************************************************************************************
+/************************************************************************************************************
  * arch/arm/src/armv7-a/mmu.h
  * CP15 MMU register definitions
  *
@@ -40,14 +40,14 @@
  * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  * POSSIBILITY OF SUCH DAMAGE.
  *
- ************************************************************************************/
+ ************************************************************************************************************/
 
 #ifndef __ARCH_ARM_SRC_ARMV7_A_MMU_H
 #define __ARCH_ARM_SRC_ARMV7_A_MMU_H
 
-/************************************************************************************
+/************************************************************************************************************
  * Included Files
- ************************************************************************************/
+ ************************************************************************************************************/
 
 #include <nuttx/config.h>
 
@@ -57,10 +57,11 @@
 #  include "chip.h"
 #endif /* __ASSEMBLY__ */
 
-/************************************************************************************
+/************************************************************************************************************
  * Pre-processor Definitions
- ************************************************************************************/
-/* Configuration ********************************************************************/
+ ************************************************************************************************************/
+
+/* Configuration ********************************************************************************************/
 
 #if defined(CONFIG_PAGING) || defined(CONFIG_ARCH_ADDRENV)
 
@@ -73,7 +74,8 @@
 #endif
 #endif /* CONFIG_PAGING */
 
-/* MMU CP15 Register Bit Definitions ************************************************/
+/* MMU CP15 Register Bit Definitions ************************************************************************/
+
 /* Reference: Cortex-A5™ MPCore Paragraph 6.7, "MMU software accessible registers." */
 
 /* TLB Type Register TLB Type Register
@@ -84,9 +86,10 @@
  */
 
 /* System Control Register (SCTLR). see cstlr.h */
+
 /* Non-secure Access Control Register (NSACR).  See cstlr.h */
 
-/* Translation Table Base Register 0 (TTBR0)*/
+/* Translation Table Base Register 0 (TTBR0) */
 
 #define TTBR0_IRGN1          (1 << 0)  /* Bit 0:  Inner cacheability IRGN[1] (MP extensions) */
 #define TTBR0_C              (1 << 0)  /* Bit 0:  Inner cacheability for table walk */
@@ -94,15 +97,17 @@
                                        /* Bit 2:  Reserved */
 #define TTBR0_RGN_SHIFT      (3)       /* Bits 3-4: Outer cacheable attributes for table walk */
 #define TTBR0_RGN_MASK       (3 << TTBR0_RGN_SHIFT)
-#  define TTBR0_RGN_NONE     (0 << TTBR0_RGN_SHIFT) /* Non-cacheable */
-#  define TTBR0_RGN_WBWA     (1 << TTBR0_RGN_SHIFT) /* Write-Back cached + Write-Allocate */
-#  define TTBR0_RGN_WT       (2 << TTBR0_RGN_SHIFT) /* Write-Through */
-#  define TTBR0_RGN_WB       (3 << TTBR0_RGN_SHIFT) /* Write-Back */
-#define TTBR0_NOS            (1 << 5)  /* Bit 5:  Not Outer Shareable bit */
-#define TTBR0_IRGN0          (1 << 6)  /* Bit 6:  Inner cacheability IRGN[0] (MP extensions) */
-                                       /* Bits 7-n: Reserved, n=7-13 */
+#define TTBR0_RGN_NONE       (0 << TTBR0_RGN_SHIFT) /* Non-cacheable */
+#define TTBR0_RGN_WBWA       (1 << TTBR0_RGN_SHIFT) /* Write-Back cached + Write-Allocate */
+#define TTBR0_RGN_WT         (2 << TTBR0_RGN_SHIFT) /* Write-Through */
+#define TTBR0_RGN_WB         (3 << TTBR0_RGN_SHIFT) /* Write-Back */
+#define TTBR0_NOS            (1 << 5)               /* Bit 5:  Not Outer Shareable bit */
+#define TTBR0_IRGN0          (1 << 6)               /* Bit 6:  Inner cacheability IRGN[0] (MP extensions) */
+                                                    /* Bits 7-n: Reserved, n=7-13 */
+
 #define _TTBR0_LOWER(n)      (0xffffffff << (n))
-                                       /* Bits (n+1)-31: Translation table base 0 */
+                                                    /* Bits (n+1)-31: Translation table base 0 */
+
 #define TTBR0_BASE_MASK(n)   (~_TTBR0_LOWER(n))
 
 /* Translation Table Base Register 1 (TTBR1) */
@@ -113,13 +118,14 @@
                                        /* Bit 2:  Reserved */
 #define TTBR1_RGN_SHIFT      (3)       /* Bits 3-4: Outer cacheable attributes for table walk */
 #define TTBR1_RGN_MASK       (3 << TTBR1_RGN_SHIFT)
-#  define TTBR1_RGN_NONE     (0 << TTBR1_RGN_SHIFT) /* Non-cacheable */
-#  define TTBR1_RGN_WBWA     (1 << TTBR1_RGN_SHIFT) /* Write-Back cached + Write-Allocate */
-#  define TTBR1_RGN_WT       (2 << TTBR1_RGN_SHIFT) /* Write-Through */
-#  define TTBR1_RGN_WB       (3 << TTBR1_RGN_SHIFT) /* Write-Back */
-#define TTBR1_NOS            (1 << 5)  /* Bit 5:  Not Outer Shareable bit */
-#define TTBR1_IRGN0          (1 << 6)  /* Bit 6:  Inner cacheability IRGN[0] (MP extensions) */
-                                       /* Bits 7-13: Reserved */
+#define TTBR1_RGN_NONE       (0 << TTBR1_RGN_SHIFT) /* Non-cacheable */
+#define TTBR1_RGN_WBWA       (1 << TTBR1_RGN_SHIFT) /* Write-Back cached + Write-Allocate */
+#define TTBR1_RGN_WT         (2 << TTBR1_RGN_SHIFT) /* Write-Through */
+#define TTBR1_RGN_WB         (3 << TTBR1_RGN_SHIFT) /* Write-Back */
+#define TTBR1_NOS            (1 << 5)               /* Bit 5:  Not Outer Shareable bit */
+#define TTBR1_IRGN0          (1 << 6)               /* Bit 6:  Inner cacheability IRGN[0] (MP extensions) */
+                                                    /* Bits 7-13: Reserved */
+
 #define TTBR1_BASE_SHIFT     (14)      /* Bits 14-31: Translation table base 1 */
 #define TTBR1_BASE_MASK      (0xffffc000)
 
@@ -127,14 +133,14 @@
 
 #define TTBCR_N_SHIFT        (0)       /* Bits 0-2: Boundary size of TTBR0 */
 #define TTBCR_N_MASK         (7 << TTBCR_N_SHIFT)
-#  define TTBCR_N_16KB       (0 << TTBCR_N_SHIFT) /* Reset value */
-#  define TTBCR_N_8KB        (1 << TTBCR_N_SHIFT)
-#  define TTBCR_N_4KB        (2 << TTBCR_N_SHIFT)
-#  define TTBCR_N_2KB        (3 << TTBCR_N_SHIFT)
-#  define TTBCR_N_1KB        (4 << TTBCR_N_SHIFT)
-#  define TTBCR_N_512B       (5 << TTBCR_N_SHIFT)
-#  define TTBCR_N_256B       (6 << TTBCR_N_SHIFT)
-#  define TTBCR_N_128B       (7 << TTBCR_N_SHIFT)
+#define TTBCR_N_16KB         (0 << TTBCR_N_SHIFT) /* Reset value */
+#define TTBCR_N_8KB          (1 << TTBCR_N_SHIFT)
+#define TTBCR_N_4KB          (2 << TTBCR_N_SHIFT)
+#define TTBCR_N_2KB          (3 << TTBCR_N_SHIFT)
+#define TTBCR_N_1KB          (4 << TTBCR_N_SHIFT)
+#define TTBCR_N_512B         (5 << TTBCR_N_SHIFT)
+#define TTBCR_N_256B         (6 << TTBCR_N_SHIFT)
+#define TTBCR_N_128B         (7 << TTBCR_N_SHIFT)
                                        /* Bit 3:  Reserved */
 #define TTBCR_PD0            (1 << 4)  /* Bit 4:  Translation table walk on a TLB miss w/TTBR0 */
 #define TTBCR_PD1            (1 << 5)  /* Bit 5:  Translation table walk on a TLB miss w/TTBR1 */
@@ -144,9 +150,9 @@
 
 #define DACR_SHIFT(n)        ((n) << 1) /* Domain n, n=0-15 */
 #define DACR_MASK(n)         (3 << DACR_SHIFT(n))
-#  define DACR_NONE(n)       (0 << DACR_SHIFT(n)) /* Any access generates a domain fault */
-#  define DACR_CLIENT(n)     (1 << DACR_SHIFT(n)) /* Accesses checked against permissions TLB */
-#  define DACR_MANAGER(n)    (3 << DACR_SHIFT(n)) /* Accesses are not checked */
+#define DACR_NONE(n)         (0 << DACR_SHIFT(n)) /* Any access generates a domain fault */
+#define DACR_CLIENT(n)       (1 << DACR_SHIFT(n)) /* Accesses checked against permissions TLB */
+#define DACR_MANAGER(n)      (3 << DACR_SHIFT(n)) /* Accesses are not checked */
 
 /* Data Fault Status Register (DFSR) */
 
@@ -222,6 +228,7 @@
 #define TLB_VA_MASK          (0xfffff000) /* Bits 12-31: Virtual address */
 
 /* Primary Region Remap Register (PRRR) */
+
 /* Normal Memory Remap Register (NMRR) */
 
 /* TLB Hitmap Register (TLBHR) */
@@ -234,7 +241,8 @@
 
 /* Context ID Register (CONTEXTIDR).  See cstlr.h */
 
-/* Translation Table Definitions ****************************************************/
+/* Translation Table Definitions ****************************************************************************/
+
 /* Hardware translation table definitions.  Only the "short descriptor format" is
  * supported.
  *
@@ -245,11 +253,11 @@
 
 #define PMD_TYPE_SHIFT       (0)         /* Bits: 1:0:  Type of mapping */
 #define PMD_TYPE_MASK        (3 << PMD_TYPE_SHIFT)
-#  define PMD_TYPE_FAULT     (0 << PMD_TYPE_SHIFT) /* None */
-#  define PMD_TYPE_PTE       (1 << PMD_TYPE_SHIFT) /* Page table */
-#  define PMD_TYPE_SECT      (2 << PMD_TYPE_SHIFT) /* Section or supersection */
-#  define PMD_TYPE_PXN       (3 << PMD_TYPE_SHIFT) /* PXN Section or supersection */
-                                        /* Bits 2-31: Depend on the mapping type */
+#define PMD_TYPE_FAULT       (0 << PMD_TYPE_SHIFT) /* None */
+#define PMD_TYPE_PTE         (1 << PMD_TYPE_SHIFT) /* Page table */
+#define PMD_TYPE_SECT        (2 << PMD_TYPE_SHIFT) /* Section or supersection */
+#define PMD_TYPE_PXN         (3 << PMD_TYPE_SHIFT) /* PXN Section or supersection */
+                                                   /* Bits 2-31: Depend on the mapping type */
 
 /* Level 1 Fault Translation Table Format.
  *
@@ -271,7 +279,7 @@
                                           /* Bit 4:  Should be zero (SBZ) */
 #define PMD_PTE_DOM_SHIFT    (5)          /* Bits 5-8: Domain */
 #define PMD_PTE_DOM_MASK     (15 << PMD_PTE_DOM_SHIFT)
-#  define PMD_PTE_DOM(n)     ((n) << PMD_PTE_DOM_SHIFT)
+#define PMD_PTE_DOM(n)       ((n) << PMD_PTE_DOM_SHIFT)
                                           /* Bit 9:  Not implemented */
 #define PMD_PTE_PADDR_MASK   (0xfffffc00) /* Bits 10-31: Page table base address */
 
@@ -300,13 +308,13 @@
 #define PMD_SECT_XN          (1 << 4)     /* Bit 4:  Execute-never bit */
 #define PMD_SECT_DOM_SHIFT   (5)          /* Bits 5-8: Domain */
 #define PMD_SECT_DOM_MASK    (15 << PMD_SECT_DOM_SHIFT)
-#  define PMD_SECT_DOM(n)    ((n) << PMD_SECT_DOM_SHIFT)
+#define PMD_SECT_DOM(n)      ((n) << PMD_SECT_DOM_SHIFT)
                                           /* Bit 9:  Implementation defined */
 #define PMD_SECT_AP_SHIFT    (10)         /* Bits 10-11: Access Permissions bits AP[0:1] */
 #define PMD_SECT_AP_MASK     (3 << PMD_SECT_AP_SHIFT)
-#  define PMD_SECT_AP0       (1 << PMD_SECT_AP_SHIFT) /* AP[0]:  Access permission bit 0 */
-#  define PMD_SECT_AP1       (2 << PMD_SECT_AP_SHIFT) /* AP[1]:  Access permission bit 1 */
-#define PMD_SECT_TEX_SHIFT   (12)         /* Bits 12-14: Memory region attribute bits */
+#define PMD_SECT_AP0         (1 << PMD_SECT_AP_SHIFT) /* AP[0]:  Access permission bit 0 */
+#define PMD_SECT_AP1         (2 << PMD_SECT_AP_SHIFT) /* AP[1]:  Access permission bit 1 */
+#define PMD_SECT_TEX_SHIFT   (12)                     /* Bits 12-14: Memory region attribute bits */
 #define PMD_SECT_TEX_MASK    (7 << PMD_SECT_TEX_SHIFT)
 #define PMD_SECT_AP2         (1 << 15)    /* Bit 15: AP[2]:  Access permission bit 2 */
 #define PMD_SECT_S           (1 << 16)    /* Bit 16: Shareable bit */
@@ -402,26 +410,29 @@
 
 #define PTE_TYPE_SHIFT       (0)          /* Bits: 1:0:  Type of mapping */
 #define PTE_TYPE_MASK        (3 << PTE_TYPE_SHIFT)
-#  define PTE_TYPE_FAULT     (0 << PTE_TYPE_SHIFT) /* None */
-#  define PTE_TYPE_LARGE     (1 << PTE_TYPE_SHIFT) /* 64Kb of memory */
-#  define PTE_TYPE_SMALL     (2 << PTE_TYPE_SHIFT) /*  4Kb of memory */
-#define PTE_B                (1 << 2)     /* Bit 2:  Bufferable bit */
-#define PTE_C                (1 << 3)     /* Bit 3:  Cacheable bit */
-#define PTE_AP_SHIFT         (4)          /* Bits 4-5: Access Permissions bits AP[0:1] */
+#define PTE_TYPE_FAULT       (0 << PTE_TYPE_SHIFT) /* None */
+#define PTE_TYPE_LARGE       (1 << PTE_TYPE_SHIFT) /* 64Kb of memory */
+#define PTE_TYPE_SMALL       (2 << PTE_TYPE_SHIFT) /*  4Kb of memory */
+#define PTE_B                (1 << 2)              /* Bit 2:  Bufferable bit */
+#define PTE_C                (1 << 3)              /* Bit 3:  Cacheable bit */
+#define PTE_AP_SHIFT         (4)                   /* Bits 4-5: Access Permissions bits AP[0:1] */
 #define PTE_AP_MASK          (3 << PTE_AP_SHIFT)
-#  define PTE_AP0            (1 << PTE_AP_SHIFT)   /* AP[0]:  Access permission bit 0 */
-#  define PTE_AP1            (2 << PTE_AP_SHIFT)   /* AP[1]:  Access permission bit 1 */
-                                          /* Bits 6-8: Depend on entry type */
-#define PTE_AP2              (1 << 9)     /* Bit 9: AP[2]:  Access permission bit 2 */
-#define PTE_S                (1 << 10)    /* Bit 10: Shareable bit */
-#define PTE_NG               (1 << 11)    /* Bit 11: Not global bit. */
-                                          /* Bits 12-31:Depend on entry type */
+#define PTE_AP0              (1 << PTE_AP_SHIFT)   /* AP[0]:  Access permission bit 0 */
+#define PTE_AP1              (2 << PTE_AP_SHIFT)   /* AP[1]:  Access permission bit 1 */
+                                                   /* Bits 6-8: Depend on entry type */
+#define PTE_AP2              (1 << 9)              /* Bit 9: AP[2]:  Access permission bit 2 */
+#define PTE_S                (1 << 10)             /* Bit 10: Shareable bit */
+#define PTE_NG               (1 << 11)             /* Bit 11: Not global bit. */
+                                                   /* Bits 12-31:Depend on entry type */
 
 /* Large page -- 64Kb */
-                                          /* Bits: 1:0:  Type of mapping */
-                                          /* Bit 2:  Bufferable bit */
-                                          /* Bit 3:  Cacheable bit */
-                                          /* Bits 4-5: Access Permissions bits AP[0:1] */
+
+/* Bits: 1:0:  Type of mapping
+ * Bit 2:  Bufferable bit
+ * Bit 3:  Cacheable bit
+ * Bits 4-5: Access Permissions bits AP[0:1]
+ */
+
 #define PTE_LARGE_TEX_SHIFT  (12)         /* Bits 12-14: Memory region attribute bits */
 #define PTE_LARGE_TEX_MASK   (7 << PTE_LARGE_TEX_SHIFT)
 #define PTE_LARGE_XN         (1 << 15)    /* Bit 15: Execute-never bit */
@@ -430,10 +441,12 @@
 
 /* Small page -- 4Kb */
 
-                                          /* Bits: 1:0:  Type of mapping */
-                                          /* Bit 2:  Bufferable bit */
-                                          /* Bit 3:  Cacheable bit */
-                                          /* Bits 4-5: Access Permissions bits AP[0:1] */
+/* Bits: 1:0:  Type of mapping
+ * Bit 2:  Bufferable bit
+ * Bit 3:  Cacheable bit
+ * Bits 4-5: Access Permissions bits AP[0:1]
+ */
+
 #define PTE_SMALL_FLAG_MASK  (0x0000003f) /* Bits 0-11: MMU flags (mostly) */
 #define PTE_SMALL_PADDR_MASK (0xfffff000) /* Bits 12-31: Small page base address, PA[31:12] */
 
@@ -571,8 +584,15 @@
 
 #define MMU_ROMFLAGS         (PMD_TYPE_SECT | PMD_SECT_AP_R1 | PMD_CACHEABLE | \
                               PMD_SECT_DOM(0))
+
+#ifdef CONFIG_SMP
+#define MMU_MEMFLAGS         (PMD_TYPE_SECT | PMD_SECT_AP_RW1 | PMD_CACHEABLE | \
+                              PMD_SECT_S | PMD_SECT_DOM(0))
+#else
 #define MMU_MEMFLAGS         (PMD_TYPE_SECT | PMD_SECT_AP_RW1 | PMD_CACHEABLE | \
                               PMD_SECT_DOM(0))
+#endif
+
 #define MMU_IOFLAGS          (PMD_TYPE_SECT | PMD_SECT_AP_RW1 | PMD_DEVICE | \
                               PMD_SECT_DOM(0) | PMD_SECT_XN)
 #define MMU_STRONGLY_ORDERED (PMD_TYPE_SECT | PMD_SECT_AP_RW1 | \
@@ -626,7 +646,7 @@
 
 #define PGTABLE_SIZE       0x00004000
 
-/* Virtual Page Table Location ******************************************************/
+/* Virtual Page Table Location ******************************************************************************/
 
 #ifdef CONFIG_PAGING
 /* Check if the virtual address of the page table has been defined. It
@@ -648,7 +668,7 @@
 
 #endif /* PGTABLE_BASE_VADDR */
 
-/* MMU flags ************************************************************************/
+/* MMU flags ************************************************************************************************/
 
 /* Create some friendly definitions to handle page table entries */
 
@@ -670,7 +690,7 @@
 
 #define PG_L1_PADDRMASK       PMD_SECT_PADDR_MASK
 
-/* Addresses of Memory Regions ******************************************************/
+/* Addresses of Memory Regions ******************************************************************************/
 
 /* We position the locked region PTEs at an offset into the first
  * L2 page table.  The L1 entry points to an 1Mb aligned virtual
@@ -720,7 +740,7 @@
 #define PG_L2_DATA_VADDR        (PG_L2_LOCKED_VADDR + PG_L2_TEXT_SIZE)
 #define PG_L2_DATA_SIZE         (4*PG_DATA_NPAGES)
 
-/* Page Table Info ******************************************************************/
+/* Page Table Info ******************************************************************************************/
 
 /* The number of pages in the in the page table (PG_PGTABLE_NPAGES).  We
  * position the page table PTEs just after the data section PTEs.
@@ -734,7 +754,7 @@
 #define PG_L2_PGTABLE_VADDR     (PG_L2_DATA_VADDR + PG_L2_DATA_SIZE)
 #define PG_L2_PGTABLE_SIZE      (4*PG_DATA_NPAGES)
 
-/* Vector Mapping *******************************************************************/
+/* Vector Mapping *******************************************************************************************/
 
 /* One page is required to map the vector table.  The vector table could lie
  * at virtual address zero (or at the start of RAM which is aliased to address
@@ -788,7 +808,7 @@
 #  error "Logic missing for high vectors in this case"
 #endif
 
-/* Page Usage ***********************************************************************/
+/* Page Usage ***********************************************************************************************/
 
 /* This is the total number of pages used in the text/data mapping: */
 
@@ -803,7 +823,7 @@
 #  error "Total pages required exceeds RAM size"
 #endif
 
-/* Page Management ******************************************************************/
+/* Page Management ******************************************************************************************/
 
 /* For page management purposes, the following summarize the "heap" of
  * free pages, operations on free pages and the L2 page table.
@@ -868,9 +888,9 @@
 
 #endif /* CONFIG_PAGING */
 
-/************************************************************************************
+/************************************************************************************************************
  * Public Types
- ************************************************************************************/
+ ************************************************************************************************************/
 
 #ifndef __ASSEMBLY__
 /* struct section_mapping_s describes the L1 mapping of a large region of memory
@@ -888,13 +908,13 @@ struct section_mapping_s
 };
 #endif
 
-/************************************************************************************
+/************************************************************************************************************
  * Assembly Macros
- ************************************************************************************/
+ ************************************************************************************************************/
 
 #ifdef __ASSEMBLY__
 
-/************************************************************************************
+/************************************************************************************************************
  * Name: cp15_disable_mmu
  *
  * Description:
@@ -903,15 +923,15 @@ struct section_mapping_s
  * Input Parameters:
  *   None
  *
- ************************************************************************************/
+ ************************************************************************************************************/
 
-	.macro	cp15_disable_mmu, scratch
-	mrc		p15, 0, \scratch, c1, c0, 0
-	bic		\scratch, \scratch, #1
-	mcr		p15, 0, \scratch, c1, c0, 0
-	.endm
+  .macro  cp15_disable_mmu, scratch
+  mrc  p15, 0, \scratch, c1, c0, 0
+  bic  \scratch, \scratch, #1
+  mcr  p15, 0, \scratch, c1, c0, 0
+  .endm
 
-/************************************************************************************
+/************************************************************************************************************
  * Name: cp15_invalidate_tlbs
  *
  * Description:
@@ -925,13 +945,13 @@ struct section_mapping_s
  * Input Parameters:
  *   None
  *
- ************************************************************************************/
+ ************************************************************************************************************/
 
-	.macro	cp15_invalidate_tlbs, scratch
-	mcr		p15, 0, \scratch, c8, c7, 0	/* TLBIALL */
-	.endm
+  .macro  cp15_invalidate_tlbs, scratch
+  mcr  p15, 0, \scratch, c8, c7, 0  /* TLBIALL */
+  .endm
 
-/************************************************************************************
+/************************************************************************************************************
  * Name: cp15_invalidate_tlb_bymva
  *
  * Description:
@@ -940,20 +960,20 @@ struct section_mapping_s
  * Input Parameters:
  *   vaddr - The virtual address to be invalidated
  *
- ************************************************************************************/
+ ************************************************************************************************************/
 
-	.macro	cp15_invalidate_tlb_bymva, vaddr
-	dsb
+  .macro  cp15_invalidate_tlb_bymva, vaddr
+  dsb
 #if defined(CONFIG_ARCH_CORTEXA8)
-	mcr		p15, 0, \vaddr, c8, c7, 1	/* TLBIMVA */
+  mcr  p15, 0, \vaddr, c8, c7, 1  /* TLBIMVA */
 #else
-	mcr		p15, 0, \vaddr, c8, c3, 3	/* TLBIMVAAIS */
+  mcr  p15, 0, \vaddr, c8, c3, 3  /* TLBIMVAAIS */
 #endif
-	dsb
-	isb
-	.endm
+  dsb
+  isb
+  .endm
 
-/************************************************************************************
+/************************************************************************************************************
  * Name: cp15_wrdacr
  *
  * Description:
@@ -962,21 +982,21 @@ struct section_mapping_s
  * Input Parameters:
  *   dacr - The new value of the DACR
  *
- ************************************************************************************/
+ ************************************************************************************************************/
 
-	.macro	cp15_wrdacr, dacr
-	mcr		p15, 0, \dacr, c3, c0, 0
-	nop
-	nop
-	nop
-	nop
-	nop
-	nop
-	nop
-	nop
-	.endm
+  .macro  cp15_wrdacr, dacr
+  mcr  p15, 0, \dacr, c3, c0, 0
+  nop
+  nop
+  nop
+  nop
+  nop
+  nop
+  nop
+  nop
+  .endm
 
-/************************************************************************************
+/************************************************************************************************************
  * Name: cp15_wrttb
  *
  * Description:
@@ -989,23 +1009,23 @@ struct section_mapping_s
  * Input Parameters:
  *   ttb - The new value of the TTBR0 register
  *
- ************************************************************************************/
+ ************************************************************************************************************/
 
-	.macro	cp15_wrttb, ttb, scratch
-	mcr		p15, 0, \ttb, c2, c0, 0
-	nop
-	nop
-	nop
-	nop
-	nop
-	nop
-	nop
-	nop
-	mov		\scratch, #0x0
-	mcr		p15, 0, \scratch, c2, c0, 2
-	.endm
+  .macro  cp15_wrttb, ttb, scratch
+  mcr  p15, 0, \ttb, c2, c0, 0
+  nop
+  nop
+  nop
+  nop
+  nop
+  nop
+  nop
+  nop
+  mov  \scratch, #0x0
+  mcr  p15, 0, \scratch, c2, c0, 2
+  .endm
 
-/************************************************************************************
+/************************************************************************************************************
  * Name: pg_l2map
  *
  * Description:
@@ -1013,11 +1033,11 @@ struct section_mapping_s
  *   written. This macro is used when CONFIG_PAGING is enable.  This case,
  *   it is used as follows:
  *
- *	ldr	r0, =PGTABLE_L2_BASE_PADDR	<-- Address in L2 table
- *	ldr	r1, =PG_LOCKED_PBASE		<-- Physical page memory address
- *	ldr	r2, =CONFIG_PAGING_NLOCKED	<-- number of pages
- *      ldr	r3, =MMUFLAGS			<-- L2 MMU flags
- *	pg_l2map r0, r1, r2, r3, r4
+ *  ldr  r0, =PGTABLE_L2_BASE_PADDR  <-- Address in L2 table
+ *  ldr  r1, =PG_LOCKED_PBASE        <-- Physical page memory address
+ *  ldr  r2, =CONFIG_PAGING_NLOCKED  <-- number of pages
+ *  ldr  r3, =MMUFLAGS               <-- L2 MMU flags
+ *  pg_l2map r0, r1, r2, r3, r4
  *
  * Input Parameters:
  *   l2 - Physical or virtual start address in the L2 page table, depending
@@ -1038,44 +1058,44 @@ struct section_mapping_s
  * - The L2 page tables have been zeroed prior to calling this function
  * - pg_l1span has been called to initialize the L1 table.
  *
- ************************************************************************************/
+ ************************************************************************************************************/
 
 #ifdef CONFIG_PAGING
-	.macro	pg_l2map, l2, ppage, npages, mmuflags, tmp
-	b		2f
+  .macro  pg_l2map, l2, ppage, npages, mmuflags, tmp
+  b    2f
 1:
-	/* Write the one L2 entries.  First,  get tmp = (ppage | mmuflags),
-	 * the value to write into the L2 PTE
-	 */
+  /* Write the one L2 entries.  First,  get tmp = (ppage | mmuflags),
+   * the value to write into the L2 PTE
+   */
 
-	orr		\tmp, \ppage, \mmuflags
+  orr  \tmp, \ppage, \mmuflags
 
-	/* Write value into table at the current table address
-	 * (and increment the L2 page table address by 4)
-	 */
+  /* Write value into table at the current table address
+   * (and increment the L2 page table address by 4)
+   */
 
-	str		\tmp, [\l2], #4
+  str  \tmp, [\l2], #4
 
-	/* Update the physical address that will correspond to the next
-	 * table entry.
-	 */
+  /* Update the physical address that will correspond to the next
+   * table entry.
+   */
 
-	add		\ppage, \ppage, #CONFIG_PAGING_PAGESIZE
+  add  \ppage, \ppage, #CONFIG_PAGING_PAGESIZE
 
-	/* Decrement the number of pages written */
+  /* Decrement the number of pages written */
 
-	sub		\npages, \npages, #1
+  sub  \npages, \npages, #1
 2:
-	/* Check if all of the pages have been written.  If not, then
-	 * loop and write the next PTE.
-	 */
+  /* Check if all of the pages have been written.  If not, then
+   * loop and write the next PTE.
+   */
 
-	cmp		\npages, #0
-	bgt		1b
-	.endm
+  cmp  \npages, #0
+  bgt  1b
+  .endm
 #endif /* CONFIG_PAGING */
 
-/************************************************************************************
+/************************************************************************************************************
  * Name: pg_l1span
  *
  * Description:
@@ -1083,12 +1103,12 @@ struct section_mapping_s
  *   entries will be written as  many as needed to span npages.  This macro is
  *   used when CONFIG_PAGING is enable.  In this case, it is used as follows:
  *
- *	ldr	r0, =PG_L1_PGTABLE_PADDR	<-- Address in the L1 table
- *	ldr	r1, =PG_L2_PGTABLE_PADDR	<-- Physical address of L2 page table
- *	ldr	r2, =PG_PGTABLE_NPAGES		<-- Total number of pages
- *	ldr	r3, =PG_PGTABLE_NPAGE1		<-- Number of pages in the first PTE
- *	ldr	r4, =MMU_L1_PGTABFLAGS		<-- L1 MMU flags
- *	pg_l1span r0, r1, r2, r3, r4, r4
+ *  ldr  r0, =PG_L1_PGTABLE_PADDR  <-- Address in the L1 table
+ *  ldr  r1, =PG_L2_PGTABLE_PADDR  <-- Physical address of L2 page table
+ *  ldr  r2, =PG_PGTABLE_NPAGES    <-- Total number of pages
+ *  ldr  r3, =PG_PGTABLE_NPAGE1    <-- Number of pages in the first PTE
+ *  ldr  r4, =MMU_L1_PGTABFLAGS    <-- L1 MMU flags
+ *  pg_l1span r0, r1, r2, r3, r4, r4
  *
  * Input Parameters (unmodified unless noted):
  *   l1 - Physical or virtual address in the L1 table to begin writing (modified)
@@ -1111,56 +1131,56 @@ struct section_mapping_s
  * - The MMU is not yet enabled
  * - The L2 page tables have been zeroed prior to calling this function
  *
- ************************************************************************************/
+ ************************************************************************************************************/
 
 #ifdef CONFIG_PAGING
-	.macro	pg_l1span, l1, l2, npages, ppage, mmuflags, tmp
-	b		2f
+  .macro  pg_l1span, l1, l2, npages, ppage, mmuflags, tmp
+  b    2f
 1:
-	/* Write the L1 table entry that refers to this (unmapped) small page
-	 * table.
-	 *
-	 * tmp = (l2table | mmuflags), the value to write into the page table
-	 */
+  /* Write the L1 table entry that refers to this (unmapped) small page
+   * table.
+   *
+   * tmp = (l2table | mmuflags), the value to write into the page table
+   */
 
-	orr		\tmp, \l2, \mmuflags
+  orr  \tmp, \l2, \mmuflags
 
-	/* Write the value into the L1 table at the correct offset.
-	 * (and increment the L1 table address by 4)
-	 */
+  /* Write the value into the L1 table at the correct offset.
+   * (and increment the L1 table address by 4)
+   */
 
-	str		\tmp, [\l1], #4
+  str  \tmp, [\l1], #4
 
-	/* Update the L2 page table address for the next L1 table entry. */
+  /* Update the L2 page table address for the next L1 table entry. */
 
-	add		\l2, \l2, #PT_SIZE  /* Next L2 page table start address */
+  add  \l2, \l2, #PT_SIZE  /* Next L2 page table start address */
 
-	/* Update the number of pages that we have account for (with
-	 * non-mappings).  NOTE that the first page may have fewer than
-	 * the maximum entries per page table.
-	 */
+  /* Update the number of pages that we have account for (with
+   * non-mappings).  NOTE that the first page may have fewer than
+   * the maximum entries per page table.
+   */
 
-	sub		\npages, \npages, \ppage
-	mov		\ppage, #PTE_NPAGES
+  sub  \npages, \npages, \ppage
+  mov  \ppage, #PTE_NPAGES
 2:
-	/* Check if all of the pages have been written.  If not, then
-	 * loop and write the next L1 entry.
-	 */
+  /* Check if all of the pages have been written.  If not, then
+   * loop and write the next L1 entry.
+   */
 
-	cmp		\npages, #0
-	bgt		1b
-	.endm
+  cmp  \npages, #0
+  bgt  1b
+  .endm
 
 #endif /* CONFIG_PAGING */
 #endif /* __ASSEMBLY__ */
 
-/************************************************************************************
+/************************************************************************************************************
  * Inline Functions
- ************************************************************************************/
+ ************************************************************************************************************/
 
 #ifndef __ASSEMBLY__
 
-/************************************************************************************
+/************************************************************************************************************
  * Name: cp15_disable_mmu
  *
  * Description:
@@ -1169,7 +1189,7 @@ struct section_mapping_s
  * Input Parameters:
  *   None
  *
- ************************************************************************************/
+ ************************************************************************************************************/
 
 static inline void cp15_disable_mmu(void)
 {
@@ -1184,7 +1204,7 @@ static inline void cp15_disable_mmu(void)
     );
 }
 
-/************************************************************************************
+/************************************************************************************************************
  * Name: cp15_invalidate_tlbs
  *
  * Description:
@@ -1198,7 +1218,7 @@ static inline void cp15_disable_mmu(void)
  * Input Parameters:
  *   None
  *
- ************************************************************************************/
+ ************************************************************************************************************/
 
 static inline void cp15_invalidate_tlbs(void)
 {
@@ -1211,7 +1231,7 @@ static inline void cp15_invalidate_tlbs(void)
     );
 }
 
-/************************************************************************************
+/************************************************************************************************************
  * Name: cp15_invalidate_tlb_bymva
  *
  * Description:
@@ -1220,7 +1240,7 @@ static inline void cp15_invalidate_tlbs(void)
  * Input Parameters:
  *   vaddr - The virtual address to be invalidated
  *
- ************************************************************************************/
+ ************************************************************************************************************/
 
 static inline void cp15_invalidate_tlb_bymva(uint32_t vaddr)
 {
@@ -1240,7 +1260,7 @@ static inline void cp15_invalidate_tlb_bymva(uint32_t vaddr)
     );
 }
 
-/************************************************************************************
+/************************************************************************************************************
  * Name: cp15_wrdacr
  *
  * Description:
@@ -1249,7 +1269,7 @@ static inline void cp15_invalidate_tlb_bymva(uint32_t vaddr)
  * Input Parameters:
  *   dacr - The new value of the DACR
  *
- ************************************************************************************/
+ ************************************************************************************************************/
 
 static inline void cp15_wrdacr(unsigned int dacr)
 {
@@ -1270,7 +1290,7 @@ static inline void cp15_wrdacr(unsigned int dacr)
     );
 }
 
-/************************************************************************************
+/************************************************************************************************************
  * Name: cp15_wrttb
  *
  * Description:
@@ -1283,7 +1303,7 @@ static inline void cp15_wrdacr(unsigned int dacr)
  * Input Parameters:
  *   ttb - The new value of the TTBR0 register
  *
- ************************************************************************************/
+ ************************************************************************************************************/
 
 static inline void cp15_wrttb(unsigned int ttb)
 {
@@ -1306,7 +1326,7 @@ static inline void cp15_wrttb(unsigned int ttb)
     );
 }
 
-/*************************************************************************************
+/************************************************************************************************************
  * Name: mmu_l1_getentry
  *
  * Description:
@@ -1315,12 +1335,12 @@ static inline void cp15_wrttb(unsigned int ttb)
  * Input Parameters:
  *   vaddr - The virtual address to be mapped.
  *
- ************************************************************************************/
+ ************************************************************************************************************/
 
 #ifndef CONFIG_ARCH_ROMPGTABLE
 static inline uint32_t mmu_l1_getentry(uint32_t vaddr)
 {
-  uint32_t *l1table = (uint32_t*)PGTABLE_BASE_VADDR;
+  uint32_t *l1table = (uint32_t *)PGTABLE_BASE_VADDR;
   uint32_t  index   = vaddr >> 20;
 
   /* Return the address of the page table entry */
@@ -1329,7 +1349,7 @@ static inline uint32_t mmu_l1_getentry(uint32_t vaddr)
 }
 #endif
 
-/*************************************************************************************
+/************************************************************************************************************
  * Name: mmu_l2_getentry
  *
  * Description:
@@ -1340,12 +1360,12 @@ static inline uint32_t mmu_l1_getentry(uint32_t vaddr)
  *   l2vaddr - The virtual address of the beginning of the L2 page table
  *   vaddr - The virtual address to be mapped.
  *
- ************************************************************************************/
+ ************************************************************************************************************/
 
 #ifndef CONFIG_ARCH_ROMPGTABLE
 static inline uint32_t mmu_l2_getentry(uint32_t l2vaddr, uint32_t vaddr)
 {
-  uint32_t *l2table  = (uint32_t*)l2vaddr;
+  uint32_t *l2table  = (uint32_t *)l2vaddr;
   uint32_t  index;
 
   /* The table divides a 1Mb address space up into 256 entries, each
@@ -1363,13 +1383,13 @@ static inline uint32_t mmu_l2_getentry(uint32_t l2vaddr, uint32_t vaddr)
 
 #endif /* __ASSEMBLY__ */
 
-/************************************************************************************
+/************************************************************************************************************
  * Public Data
- ************************************************************************************/
+ ************************************************************************************************************/
 
-/************************************************************************************
+/************************************************************************************************************
  * Public Function Prototypes
- ************************************************************************************/
+ ************************************************************************************************************/
 
 #ifndef __ASSEMBLY__
 #ifdef __cplusplus
@@ -1380,7 +1400,7 @@ extern "C"
 #define EXTERN extern
 #endif
 
-/************************************************************************************
+/************************************************************************************************************
  * Name: mmu_l1_setentry
  *
  * Description:
@@ -1394,13 +1414,13 @@ extern "C"
  *     boundary
  *   mmuflags - The MMU flags to use in the mapping.
  *
- ************************************************************************************/
+ ************************************************************************************************************/
 
 #ifndef CONFIG_ARCH_ROMPGTABLE
 void mmu_l1_setentry(uint32_t paddr, uint32_t vaddr, uint32_t mmuflags);
 #endif
 
-/****************************************************************************
+/************************************************************************************************************
  * Name: mmu_l1_restore
  *
  * Description:
@@ -1411,13 +1431,13 @@ void mmu_l1_setentry(uint32_t paddr, uint32_t vaddr, uint32_t mmuflags);
  *   vaddr - A virtual address to be mapped
  *   l1entry - The value to write into the page table entry
  *
- ****************************************************************************/
+ ************************************************************************************************************/
 
 #if !defined(CONFIG_ARCH_ROMPGTABLE) && defined(CONFIG_ARCH_ADDRENV)
 void mmu_l1_restore(uintptr_t vaddr, uint32_t l1entry);
 #endif
 
-/************************************************************************************
+/************************************************************************************************************
  * Name: mmu_l1_clrentry
  *
  * Description:
@@ -1427,13 +1447,13 @@ void mmu_l1_restore(uintptr_t vaddr, uint32_t l1entry);
  * Input Parameters:
  *   vaddr - A virtual address within the L1 address region to be unmapped.
  *
- ************************************************************************************/
+ ************************************************************************************************************/
 
 #if !defined (CONFIG_ARCH_ROMPGTABLE) && defined(CONFIG_ARCH_ADDRENV)
 #  define mmu_l1_clrentry(v) mmu_l1_restore(v,0)
 #endif
 
-/****************************************************************************
+/************************************************************************************************************
  * Name: mmu_l2_setentry
  *
  * Description:
@@ -1448,14 +1468,14 @@ void mmu_l1_restore(uintptr_t vaddr, uint32_t l1entry);
  *     address boundary
  *   mmuflags - The MMU flags to use in the mapping.
  *
- ****************************************************************************/
+ ************************************************************************************************************/
 
 #ifndef CONFIG_ARCH_ROMPGTABLE
 void mmu_l2_setentry(uint32_t l2vaddr, uint32_t paddr, uint32_t vaddr,
                      uint32_t mmuflags);
 #endif
 
-/****************************************************************************
+/************************************************************************************************************
  * Name: mmu_l1_map_region
  *
  * Description:
@@ -1465,13 +1485,13 @@ void mmu_l2_setentry(uint32_t l2vaddr, uint32_t paddr, uint32_t vaddr,
  * Input Parameters:
  *   mapping - Describes the mapping to be performed.
  *
- ****************************************************************************/
+ ************************************************************************************************************/
 
 #ifndef CONFIG_ARCH_ROMPGTABLE
 void mmu_l1_map_region(const struct section_mapping_s *mapping);
 #endif
 
-/****************************************************************************
+/************************************************************************************************************
  * Name: mmu_l1_map_regions
  *
  * Description:
@@ -1482,13 +1502,14 @@ void mmu_l1_map_region(const struct section_mapping_s *mapping);
  *   mappings - Describes the array of mappings to be performed.
  *   count    - The number of mappings to be performed.
  *
- ****************************************************************************/
+ ************************************************************************************************************/
+
 #ifndef CONFIG_ARCH_ROMPGTABLE
 void mmu_l1_map_regions(const struct section_mapping_s *mappings,
                         size_t count);
 #endif
 
-/****************************************************************************
+/************************************************************************************************************
  * Name: mmu_invalidate_region
  *
  * Description:
@@ -1498,7 +1519,7 @@ void mmu_l1_map_regions(const struct section_mapping_s *mappings,
  *   vaddr - The beginning of the region to invalidate.
  *   size  - The size of the region in bytes to be invalidated.
  *
- ****************************************************************************/
+ ************************************************************************************************************/
 
 #ifndef CONFIG_ARCH_ROMPGTABLE
 void mmu_invalidate_region(uint32_t vstart, size_t size);

arch/arm/src/armv7-a/smp.h

@@ -58,7 +58,6 @@
 #define SMP_STACK_MASK       7
 #define SMP_STACK_SIZE       ((CONFIG_SMP_IDLETHREAD_STACKSIZE + 7) & ~7)
 #define SMP_STACK_WORDS      (SMP_STACK_SIZE >> 2)
-#define SMP_STACK_TOP        (SMP_STACK_SIZE - 8)
 
 /****************************************************************************
  * Public Data
@@ -122,9 +121,9 @@ void __cpu3_start(void);
  *
  * Description:
  *   Continues the C-level initialization started by the assembly language
- *   __cpu[n]_start function.  At a minimum, this function needs to initialize
- *   interrupt handling and, perhaps, wait on WFI for arm_cpu_start() to
- *   issue an SGI.
+ *   __cpu[n]_start function.  At a minimum, this function needs to
+ *   initialize interrupt handling and, perhaps, wait on WFI for
+ *   arm_cpu_start() to issue an SGI.
  *
  *   This function must be provided by the each ARMv7-A MCU and implement
  *   MCU-specific initialization logic.

arch/arm/src/armv7-m/arm_assert.c

@@ -244,7 +244,7 @@ static void up_dumpstate(void)
    * stack?
    */
 
-  if (sp <= istackbase && sp > istackbase - istacksize)
+  if (sp < istackbase && sp > istackbase - istacksize)
     {
       /* Yes.. dump the interrupt stack */
 

arch/arm/src/armv7-m/gnu/arm_exception.S

@@ -67,7 +67,7 @@
    * no privileged task has run.
    */
 
-#  if defined(CONFIG_BUILD_PROTECTED) && CONFIG_ARCH_INTERRUPTSTACK < 4
+#  if defined(CONFIG_BUILD_PROTECTED) && CONFIG_ARCH_INTERRUPTSTACK < 8
 #    error Interrupt stack must be used with high priority interrupts in kernel mode
 #  endif
 
@@ -197,7 +197,7 @@ exception_common:
 	 * here prohibits nested interrupts without some additional logic!
 	 */
 
-	setintstack	r2, r3
+	setintstack	r2, r3				/* SP = IRQ stack top */
 
 #else
 	/* Otherwise, we will re-use the interrupted thread's stack.  That may
@@ -321,7 +321,7 @@ exception_common:
 	.bss
 	.global	g_intstackalloc
 	.global	g_intstackbase
-	.align	8
+	.balign	8
 g_intstackalloc:
 	.skip	((CONFIG_ARCH_INTERRUPTSTACK + 4) & ~7)
 g_intstackbase:

arch/arm/src/armv7-m/gnu/arm_lazyexception.S

@@ -50,7 +50,7 @@
    * nested interrupt, the interrupt stack if no privileged task has run.
    */
 
-#  if defined(CONFIG_BUILD_PROTECTED) && CONFIG_ARCH_INTERRUPTSTACK < 4
+#  if defined(CONFIG_BUILD_PROTECTED) && CONFIG_ARCH_INTERRUPTSTACK < 8
 #    error Interrupt stack must be used with high priority interrupts in kernel mode
 #  endif
 
@@ -192,7 +192,7 @@ exception_common:
 	 * here prohibits nested interrupts without some additional logic!
 	 */
 
-	setintstack	r2, r3
+	setintstack	r2, r3				/* SP = IRQ stack top */
 
 #else
 	/* Otherwise, we will re-use the interrupted thread's stack.  That may
@@ -340,7 +340,7 @@ exception_common:
 	.bss
 	.global	g_intstackalloc
 	.global	g_intstackbase
-	.align	8
+	.balign	8
 g_intstackalloc:
 	.skip	((CONFIG_ARCH_INTERRUPTSTACK + 4) & ~7)
 g_intstackbase:

arch/arm/src/armv7-r/arm_assert.c

@@ -195,7 +195,7 @@ static void up_dumpstate(void)
   uint32_t sp   = arm_getsp();
   uint32_t ustackbase;
   uint32_t ustacksize;
-#if CONFIG_ARCH_INTERRUPTSTACK > 3
+#if CONFIG_ARCH_INTERRUPTSTACK > 7
   uint32_t istackbase;
   uint32_t istacksize;
 #endif
@@ -214,11 +214,11 @@ static void up_dumpstate(void)
 
   _alert("Current sp: %08x\n", sp);
 
-#if CONFIG_ARCH_INTERRUPTSTACK > 3
+#if CONFIG_ARCH_INTERRUPTSTACK > 7
   /* Get the limits on the interrupt stack memory */
 
   istackbase = (uint32_t)&g_intstackbase;
-  istacksize = (CONFIG_ARCH_INTERRUPTSTACK & ~3);
+  istacksize = (CONFIG_ARCH_INTERRUPTSTACK & ~7);
 
   /* Show interrupt stack info */
 
@@ -253,7 +253,7 @@ static void up_dumpstate(void)
     }
 #endif
 
-#if CONFIG_ARCH_INTERRUPTSTACK > 3
+#if CONFIG_ARCH_INTERRUPTSTACK > 7
   /* Does the current stack pointer lie within the interrupt stack? */
 
   if (sp > istackbase - istacksize && sp < istackbase)
@@ -262,13 +262,6 @@ static void up_dumpstate(void)
 
       _alert("Interrupt Stack\n", sp);
       up_stackdump(sp, istackbase);
-
-      /* Extract the user stack pointer which should lie
-       * at the base of the interrupt stack.
-       */
-
-      sp = g_intstackbase;
-      _alert("User sp: %08x\n", sp);
     }
   else if (CURRENT_REGS)
     {
@@ -277,6 +270,17 @@ static void up_dumpstate(void)
     }
 #endif
 
+  /* Extract the user stack pointer if we are in an interrupt handler.
+   * If we are not in an interrupt handler.  Then sp is the user stack
+   * pointer (and the above range check should have failed).
+   */
+
+  if (CURRENT_REGS)
+    {
+      sp = CURRENT_REGS[REG_R13];
+      _alert("User sp: %08x\n", sp);
+    }
+
   /* Dump the user stack if the stack pointer lies within the allocated user
    * stack memory.
    */

arch/arm/src/armv7-r/arm_vectors.S

@@ -179,9 +179,9 @@ arm_vectorirq:
 	mov		fp, #0					/* Init frame pointer */
 	mov		r0, sp					/* Get r0=xcp */
 
-#if CONFIG_ARCH_INTERRUPTSTACK > 3
+#if CONFIG_ARCH_INTERRUPTSTACK > 7
 	ldr		sp, .Lirqstackbase		/* SP = interrupt stack base */
-	str		r0, [sp]				/* Save the user stack pointer */
+	str		r0, [sp, #-4]!			/* Save the xcp address at SP-4 then update SP */
 	mov		r4, sp					/* Save the SP in a preserved register */
 	bic		sp, sp, #7				/* Force 8-byte alignment */
 	bl		arm_decodeirq			/* Call the handler */
@@ -232,7 +232,7 @@ arm_vectorirq:
 
 .Lirqtmp:
 	.word	g_irqtmp
-#if CONFIG_ARCH_INTERRUPTSTACK > 3
+#if CONFIG_ARCH_INTERRUPTSTACK > 7
 .Lirqstackbase:
 	.word	g_intstackbase
 #endif
@@ -890,9 +890,9 @@ arm_vectorfiq:
 	mov		fp, #0					/* Init frame pointer */
 	mov		r0, sp					/* Get r0=xcp */
 
-#if CONFIG_ARCH_INTERRUPTSTACK > 3
+#if CONFIG_ARCH_INTERRUPTSTACK > 7
 	ldr		sp, .Lfiqstackbase		/* SP = interrupt stack base */
-	str		r0, [sp]				/* Save the user stack pointer */
+	str		r0, [sp, #-4]!			/* Save the xcp address at SP-4 then update SP */
 	mov		r4, sp					/* Save the SP in a preserved register */
 	bic		sp, sp, #7				/* Force 8-byte alignment */
 	bl		arm_decodefiq			/* Call the handler */
@@ -943,7 +943,7 @@ arm_vectorfiq:
 
 .Lfiqtmp:
 	.word	g_fiqtmp
-#if CONFIG_ARCH_INTERRUPTSTACK > 3
+#if CONFIG_ARCH_INTERRUPTSTACK > 7
 .Lfiqstackbase:
 	.word	g_intstackbase
 #endif
@@ -957,9 +957,9 @@ arm_vectorfiq:
  *  Name: g_intstackalloc/g_intstackbase
  ************************************************************************************/
 
-#if CONFIG_ARCH_INTERRUPTSTACK > 3
+#if CONFIG_ARCH_INTERRUPTSTACK > 7
 	.bss
-	.align	4
+	.balign	8
 
 	.globl	g_intstackalloc
 	.type	g_intstackalloc, object
@@ -967,11 +967,11 @@ arm_vectorfiq:
 	.type	g_intstackbase, object
 
 g_intstackalloc:
-	.skip	((CONFIG_ARCH_INTERRUPTSTACK & ~3) - 4)
+	.skip	((CONFIG_ARCH_INTERRUPTSTACK + 4) & ~7)
 g_intstackbase:
 	.skip	4
 	.size	g_intstackbase, 4
-	.size	g_intstackalloc, (CONFIG_ARCH_INTERRUPTSTACK & ~3)
+	.size	g_intstackalloc, (CONFIG_ARCH_INTERRUPTSTACK & ~7)
 
-#endif /* CONFIG_ARCH_INTERRUPTSTACK > 3 */
+#endif /* CONFIG_ARCH_INTERRUPTSTACK > 7 */
 	.end

arch/arm/src/armv8-m/arm_assert.c

@@ -244,7 +244,7 @@ static void up_dumpstate(void)
    * stack?
    */
 
-  if (sp <= istackbase && sp > istackbase - istacksize)
+  if (sp < istackbase && sp > istackbase - istacksize)
     {
       /* Yes.. dump the interrupt stack */
 

arch/arm/src/armv8-m/arm_exception.S

@@ -67,7 +67,7 @@
    * no privileged task has run.
    */
 
-#  if defined(CONFIG_BUILD_PROTECTED) && CONFIG_ARCH_INTERRUPTSTACK < 4
+#  if defined(CONFIG_BUILD_PROTECTED) && CONFIG_ARCH_INTERRUPTSTACK < 8
 #    error Interrupt stack must be used with high priority interrupts in kernel mode
 #  endif
 
@@ -355,7 +355,7 @@ exception_common:
 	.bss
 	.global	g_intstackalloc
 	.global	g_intstackbase
-	.align	8
+	.balign	8
 g_intstackalloc:
 	.skip	((CONFIG_ARCH_INTERRUPTSTACK + 4) & ~7)
 g_intstackbase:

arch/arm/src/armv8-m/arm_lazyexception.S

@@ -50,7 +50,7 @@
    * nested interrupt, the interrupt stack if no privileged task has run.
    */
 
-#  if defined(CONFIG_BUILD_PROTECTED) && CONFIG_ARCH_INTERRUPTSTACK < 4
+#  if defined(CONFIG_BUILD_PROTECTED) && CONFIG_ARCH_INTERRUPTSTACK < 8
 #    error Interrupt stack must be used with high priority interrupts in kernel mode
 #  endif
 
@@ -373,7 +373,7 @@ exception_common:
 	.bss
 	.global	g_intstackalloc
 	.global	g_intstackbase
-	.align	8
+	.balign	8
 g_intstackalloc:
 	.skip	((CONFIG_ARCH_INTERRUPTSTACK + 4) & ~7)
 g_intstackbase:

arch/arm/src/c5471/c5471_vectors.S

@@ -162,7 +162,7 @@ arm_vectorirq:
 
 #if CONFIG_ARCH_INTERRUPTSTACK > 3
 	ldr	sp, .Lirqstackbase	/* SP = interrupt stack base */
-	str	r1, [sp]		/* Save the user stack pointer */
+	str	r1, [sp, #-4]!		/* Save the xcp address at SP-4 then update SP */
 	bl	arm_doirq		/* Call the handler */
 	ldr	sp, [sp]		/* Restore the user stack pointer */
 #else
@@ -471,13 +471,13 @@ arm_vectoraddrexcptn:
 
 #if CONFIG_ARCH_INTERRUPTSTACK > 3
 	.bss
-	.align	4
+	.balign	4
 	.global	g_intstackalloc
 	.global	g_intstackbase
 	.type	g_intstackalloc, object
 	.type	g_intstackbase, object
 g_intstackalloc:
-	.skip	((CONFIG_ARCH_INTERRUPTSTACK & ~3) - 4)
+	.skip	(CONFIG_ARCH_INTERRUPTSTACK & ~3)
 g_intstackbase:
 	.skip	4
 	.size	g_intstackbase, 4

arch/arm/src/common/arm_checkstack.c

@@ -55,17 +55,31 @@
 
 #ifdef CONFIG_STACK_COLORATION
 
+/****************************************************************************
+ * Pre-processor Macros
+ ****************************************************************************/
+
+/* 32bit alignment macros */
+
+#define INT32_ALIGN_MASK    (3)
+#define INT32_ALIGN_DOWN(a) ((a) & ~INT32_ALIGN_MASK)
+#define INT32_ALIGN_UP(a)   (((a) + INT32_ALIGN_MASK) & ~INT32_ALIGN_MASK)
+
 /****************************************************************************
  * Private Function Prototypes
  ****************************************************************************/
 
-static size_t do_stackcheck(uintptr_t alloc, size_t size);
+static size_t do_stackcheck(FAR void *stackbase, size_t nbytes);
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
 
 /****************************************************************************
  * Name: do_stackcheck
  *
  * Description:
- *   Determine (approximately) how much stack has been used be searching the
+ *   Determine (approximately) how much stack has been used by searching the
  *   stack memory for a high water mark.  That is, the deepest level of the
  *   stack that clobbered some recognizable marker in the stack memory.
  *
@@ -78,26 +92,26 @@ static size_t do_stackcheck(uintptr_t alloc, size_t size);
  *
  ****************************************************************************/
 
-static size_t do_stackcheck(uintptr_t alloc, size_t size)
+static size_t do_stackcheck(FAR void *stackbase, size_t nbytes)
 {
-  FAR uintptr_t start;
-  FAR uintptr_t end;
+  uintptr_t start;
+  uintptr_t end;
   FAR uint32_t *ptr;
   size_t mark;
 
-  if (size == 0)
+  if (nbytes == 0)
     {
       return 0;
     }
 
-  /* Get aligned addresses of the top and bottom of the stack */
+  /* Take extra care that we do not check outside the stack boundaries */
 
-  start = alloc & ~3;
-  end   = (alloc + size + 3) & ~3;
+  start = INT32_ALIGN_UP((uintptr_t)stackbase);
+  end   = INT32_ALIGN_DOWN((uintptr_t)stackbase + nbytes);
 
   /* Get the adjusted size based on the top and bottom of the stack */
 
-  size  = end - start;
+  nbytes  = end - start;
 
   /* The ARM uses a push-down stack:  the stack grows toward lower addresses
    * in memory.  We need to start at the lowest address in the stack memory
@@ -105,7 +119,7 @@ static size_t do_stackcheck(uintptr_t alloc, size_t size)
    * that does not have the magic value is the high water mark.
    */
 
-  for (ptr = (FAR uint32_t *)start, mark = (size >> 2);
+  for (ptr = (FAR uint32_t *)start, mark = (nbytes >> 2);
        *ptr == STACK_COLOR && mark > 0;
        ptr++, mark--);
 
@@ -126,7 +140,7 @@ static size_t do_stackcheck(uintptr_t alloc, size_t size)
       int j;
 
       ptr = (FAR uint32_t *)start;
-      for (i = 0; i < size; i += 4 * 64)
+      for (i = 0; i < nbytes; i += 4 * 64)
         {
           for (j = 0; j < 64; j++)
             {
@@ -157,6 +171,39 @@ static size_t do_stackcheck(uintptr_t alloc, size_t size)
  * Public Functions
  ****************************************************************************/
 
+/****************************************************************************
+ * Name: arm_stack_color
+ *
+ * Description:
+ *   Write a well know value into the stack
+ *
+ ****************************************************************************/
+
+void arm_stack_color(FAR void *stackbase, size_t nbytes)
+{
+  uintptr_t start;
+  uintptr_t end;
+  size_t nwords;
+  FAR uint32_t *ptr;
+
+  /* Take extra care that we do not write outside the stack boundaries */
+
+  start = INT32_ALIGN_UP((uintptr_t)stackbase);
+  end   = INT32_ALIGN_DOWN((uintptr_t)stackbase + nbytes);
+
+  /* Get the adjusted size based on the top and bottom of the stack */
+
+  nwords = (end - start) >> 2;
+  ptr  = (FAR uint32_t *)start;
+
+  /* Set the entire stack to the coloration value */
+
+  while (nwords-- > 0)
+    {
+      *ptr++ = STACK_COLOR;
+    }
+}
+
 /****************************************************************************
  * Name: up_check_stack and friends
  *
@@ -175,8 +222,8 @@ static size_t do_stackcheck(uintptr_t alloc, size_t size)
 
 size_t up_check_tcbstack(FAR struct tcb_s *tcb)
 {
-  return do_stackcheck((uintptr_t)tcb->adj_stack_ptr - tcb->adj_stack_size,
-      tcb->adj_stack_size);
+  return do_stackcheck((FAR void *)((uintptr_t)tcb->adj_stack_ptr -
+      tcb->adj_stack_size), tcb->adj_stack_size);
 }
 
 ssize_t up_check_tcbstack_remain(FAR struct tcb_s *tcb)
@@ -198,17 +245,17 @@ ssize_t up_check_stack_remain(void)
 size_t up_check_intstack(void)
 {
 #ifdef CONFIG_SMP
-  return do_stackcheck(arm_intstack_base(),
-                       (CONFIG_ARCH_INTERRUPTSTACK & ~3));
+  return do_stackcheck((FAR void *)arm_intstack_alloc(),
+                        INT32_ALIGN_DOWN(CONFIG_ARCH_INTERRUPTSTACK));
 #else
-  return do_stackcheck((uintptr_t)&g_intstackalloc,
-                       (CONFIG_ARCH_INTERRUPTSTACK & ~3));
+  return do_stackcheck((FAR void *)&g_intstackalloc,
+                        INT32_ALIGN_DOWN(CONFIG_ARCH_INTERRUPTSTACK));
 #endif
 }
 
 size_t up_check_intstack_remain(void)
 {
-  return (CONFIG_ARCH_INTERRUPTSTACK & ~3) - up_check_intstack();
+  return INT32_ALIGN_DOWN(CONFIG_ARCH_INTERRUPTSTACK) - up_check_intstack();
 }
 #endif
 

arch/arm/src/common/arm_createstack.c

@@ -58,6 +58,12 @@
 #define STACK_ALIGN_DOWN(a) ((a) & ~STACK_ALIGN_MASK)
 #define STACK_ALIGN_UP(a)   (((a) + STACK_ALIGN_MASK) & ~STACK_ALIGN_MASK)
 
+/* 32bit alignment macros */
+
+#define INT32_ALIGN_MASK    (3)
+#define INT32_ALIGN_DOWN(a) ((a) & ~INT32_ALIGN_MASK)
+#define INT32_ALIGN_UP(a)   (((a) + INT32_ALIGN_MASK) & ~INT32_ALIGN_MASK)
+
 /****************************************************************************
  * Public Functions
  ****************************************************************************/
@@ -103,10 +109,12 @@
 int up_create_stack(FAR struct tcb_s *tcb, size_t stack_size, uint8_t ttype)
 {
   size_t alloc_size;
+  size_t tls_size;
 
-  /* Add the size of the TLS information structure and align */
+  /* Add the size of the TLS information structure and align. */
 
-  alloc_size = STACK_ALIGN_UP(stack_size + sizeof(struct tls_info_s));
+  tls_size   = INT32_ALIGN_UP(sizeof(struct tls_info_s));
+  alloc_size = STACK_ALIGN_UP(stack_size + tls_size);
 
 #ifdef CONFIG_TLS_ALIGNED
   /* The allocated stack size must not exceed the maximum possible for the
@@ -117,10 +125,11 @@ int up_create_stack(FAR struct tcb_s *tcb, size_t stack_size, uint8_t ttype)
   if (alloc_size > TLS_MAXSTACK)
     {
       alloc_size = TLS_MAXSTACK;
-      stack_size = alloc_size - sizeof(struct tls_info_s);
     }
 #endif
 
+  stack_size = alloc_size - tls_size;
+
   /* Is there already a stack allocated of a different size? */
 
   if (tcb->stack_alloc_ptr && tcb->adj_stack_size != stack_size)
@@ -209,7 +218,7 @@ int up_create_stack(FAR struct tcb_s *tcb, size_t stack_size, uint8_t ttype)
 
       /* Initialize the TLS data structure */
 
-      memset(tcb->stack_alloc_ptr, 0, sizeof(struct tls_info_s));
+      memset(tcb->stack_alloc_ptr, 0, tls_size);
 
 #ifdef CONFIG_STACK_COLORATION
       /* If stack debug is enabled, then fill the stack with a
@@ -227,29 +236,3 @@ int up_create_stack(FAR struct tcb_s *tcb, size_t stack_size, uint8_t ttype)
 
   return ERROR;
 }
-
-/****************************************************************************
- * Name: arm_stack_color
- *
- * Description:
- *   Write a well know value into the stack
- *
- ****************************************************************************/
-
-#ifdef CONFIG_STACK_COLORATION
-void arm_stack_color(FAR void *stackbase, size_t nbytes)
-{
-  /* Take extra care that we do not write outsize the stack boundaries */
-
-  uint32_t *stkptr = (uint32_t *)(((uintptr_t)stackbase + 3) & ~3);
-  uintptr_t stkend = (((uintptr_t)stackbase + nbytes) & ~3);
-  size_t    nwords = (stkend - (uintptr_t)stackbase) >> 2;
-
-  /* Set the entire stack to the coloration value */
-
-  while (nwords-- > 0)
-    {
-      *stkptr++ = STACK_COLOR;
-    }
-}
-#endif

arch/arm/src/common/arm_initialize.c

@@ -62,13 +62,17 @@
 static inline void up_color_intstack(void)
 {
 #ifdef CONFIG_SMP
-  uint32_t *ptr = (uint32_t *)arm_intstack_base();
+  uint32_t *ptr = (uint32_t *)arm_intstack_alloc();
 #else
   uint32_t *ptr = (uint32_t *)&g_intstackalloc;
 #endif
   ssize_t size;
 
+#ifdef CONFIG_SMP
+  for (size = ((CONFIG_ARCH_INTERRUPTSTACK & ~3) * CONFIG_SMP_NCPUS);
+#else
   for (size = (CONFIG_ARCH_INTERRUPTSTACK & ~3);
+#endif
        size > 0;
        size -= sizeof(uint32_t))
     {

arch/arm/src/common/arm_interruptcontext.c

@@ -60,12 +60,6 @@
 bool up_interrupt_context(void)
 {
 #ifdef CONFIG_SMP
-  /* REVISIT:  Currently up_irq_save() will not disable the Software
-   * Generated Interrupts (SGIs) for the case of ARMv7-A architecture using
-   * the GIC.  So this will not be sufficient in that case, at least not
-   * until we add support for the ICCMPR.
-   */
-
   irqstate_t flags = up_irq_save();
 #endif
 

arch/arm/src/common/arm_usestack.c

@@ -53,6 +53,12 @@
 #define STACK_ALIGN_DOWN(a) ((a) & ~STACK_ALIGN_MASK)
 #define STACK_ALIGN_UP(a)   (((a) + STACK_ALIGN_MASK) & ~STACK_ALIGN_MASK)
 
+/* 32bit alignment macros */
+
+#define INT32_ALIGN_MASK    (3)
+#define INT32_ALIGN_DOWN(a) ((a) & ~INT32_ALIGN_MASK)
+#define INT32_ALIGN_UP(a)   (((a) + INT32_ALIGN_MASK) & ~INT32_ALIGN_MASK)
+
 /****************************************************************************
  * Public Functions
  ****************************************************************************/
@@ -87,12 +93,16 @@
 
 int up_use_stack(struct tcb_s *tcb, void *stack, size_t stack_size)
 {
+  size_t tls_size;
+
 #ifdef CONFIG_TLS_ALIGNED
   /* Make certain that the user provided stack is properly aligned */
 
   DEBUGASSERT(((uintptr_t)stack & TLS_STACK_MASK) == 0);
 #endif
 
+  tls_size = INT32_ALIGN_UP(sizeof(struct tls_info_s));
+
   /* Is there already a stack allocated? */
 
   if (tcb->stack_alloc_ptr)
@@ -125,7 +135,7 @@ int up_use_stack(struct tcb_s *tcb, void *stack, size_t stack_size)
 
   /* Offset by tls_size */
 
-  stack = (FAR void *)((uintptr_t)stack + sizeof(struct tls_info_s));
+  stack = (FAR void *)((uintptr_t)stack + tls_size);
 
   /* Is there enough room for at least TLS ? */
 
@@ -138,7 +148,7 @@ int up_use_stack(struct tcb_s *tcb, void *stack, size_t stack_size)
 
   /* Initialize the TLS data structure */
 
-  memset(tcb->stack_alloc_ptr, 0, sizeof(struct tls_info_s));
+  memset(tcb->stack_alloc_ptr, 0, tls_size);
 
 #ifdef CONFIG_STACK_COLORATION
   /* If stack debug is enabled, then fill the stack with a

arch/arm/src/cxd56xx/chip.h

@@ -42,6 +42,10 @@
 
 #include <nuttx/config.h>
 
+#ifndef __ASSEMBLY__
+#  include <nuttx/arch.h>
+#endif
+
 /* Include the chip capabilities file */
 
 #include <arch/cxd56xx/chip.h>
@@ -50,4 +54,35 @@
 
 #include "hardware/cxd5602_memorymap.h"
 
+#if defined(CONFIG_SMP) && CONFIG_ARCH_INTERRUPTSTACK > 7
+#  include "cxd56_cpuindex.h"
+#  include "cxd56_irq.h"
+#endif
+
+/****************************************************************************
+ * Macro Definitions
+ ****************************************************************************/
+
+#ifdef __ASSEMBLY__
+
+/****************************************************************************
+ * Name: setintstack
+ *
+ * Description:
+ *   Set the current stack pointer to the  "top" the correct interrupt stack
+ *   for the current CPU.
+ *
+ ****************************************************************************/
+
+#if defined(CONFIG_SMP) && CONFIG_ARCH_INTERRUPTSTACK > 7
+  .macro  setintstack, tmp1, tmp2
+  ldr \tmp1, =CXD56_ADSP_PID
+  ldr \tmp1, [\tmp1, 0]
+  sub \tmp1, 2                   /* tmp1 = getreg32(CXD56_ADSP_PID) - 2 */
+  ldr \tmp2, =g_cpu_intstack_top
+  ldr sp, [\tmp2, \tmp1, lsl #2] /* sp = g_cpu_intstack_top[tmp1] */
+  .endm
+#endif /* CONFIG_SMP && CONFIG_ARCH_INTERRUPTSTACK > 7 */
+
+#endif /* __ASSEMBLY__  */
 #endif /* __ARCH_ARM_SRC_CXD56XX_CHIP_H */

arch/arm/src/cxd56xx/cxd56_cpuindex.c

@@ -42,15 +42,10 @@
 #include <nuttx/arch.h>
 
 #include "arm_arch.h"
+#include "cxd56_cpuindex.h"
 
 #ifdef CONFIG_SMP
 
-/****************************************************************************
- * Pre-processor Definitions
- ****************************************************************************/
-
-#define CXD56_ADSP_PID 0x0e002040  /* APP_DSP Processor ID */
-
 /****************************************************************************
  * Public Functions
  ****************************************************************************/

arch/arm/src/cxd56xx/cxd56_cpuindex.h

@@ -0,0 +1,30 @@
+/****************************************************************************
+ * arch/arm/src/cxd56xx/cxd56_cpuindex.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_CXD56XX_CXD56_CPUINDEX_H
+#define __ARCH_ARM_SRC_CXD56XX_CXD56_CPUINDEX_H
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+#define CXD56_ADSP_PID 0x0e002040  /* APP_DSP Processor ID */
+
+#endif /* __ARCH_ARM_SRC_CXD56XX_CXD56_CPUINDEX_H */

arch/arm/src/cxd56xx/cxd56_cpupause.c

@@ -210,6 +210,13 @@ bool up_cpu_pausereq(int cpu)
 
 int up_cpu_paused(int cpu)
 {
+  /* Fistly, check if this IPI is to enable/disable IRQ */
+
+  if (handle_irqreq(cpu))
+    {
+      return OK;
+    }
+
   FAR struct tcb_s *tcb = this_task();
 
   /* Update scheduler parameters */
@@ -283,13 +290,6 @@ int arm_pause_handler(int irq, void *c, FAR void *arg)
 
   putreg32(0, CXD56_CPU_P2_INT + (4 * cpu));
 
-  /* Check if this IPI is to enable/disable IRQ */
-
-  if (handle_irqreq(cpu))
-    {
-      return OK;
-    }
-
   /* Check for false alarms.  Such false could occur as a consequence of
    * some deadlock breaking logic that might have already serviced the SG2
    * interrupt by calling up_cpu_paused.

arch/arm/src/cxd56xx/cxd56_irq.c

@@ -72,6 +72,10 @@
 
 #define INTC_EN(n) (CXD56_INTC_BASE + 0x10 + (((n) >> 5) << 2))
 
+#if defined(CONFIG_SMP) && CONFIG_ARCH_INTERRUPTSTACK > 7
+#  define INTSTACK_ALLOC (CONFIG_SMP_NCPUS * INTSTACK_SIZE)
+#endif
+
 /****************************************************************************
  * Public Data
  ****************************************************************************/
@@ -97,6 +101,36 @@ static volatile int8_t g_cpu_for_irq[CXD56_IRQ_NIRQS];
 extern void up_send_irqreq(int idx, int irq, int cpu);
 #endif
 
+#if defined(CONFIG_SMP) && CONFIG_ARCH_INTERRUPTSTACK > 7
+/* In the SMP configuration, we will need custom interrupt stacks.
+ * These definitions provide the aligned stack allocations.
+ */
+
+static uint64_t g_intstack_alloc[INTSTACK_ALLOC >> 3];
+
+/* These definitions provide the "top" of the push-down stacks. */
+
+const uint32_t g_cpu_intstack_top[CONFIG_SMP_NCPUS] =
+{
+  (uint32_t)g_intstack_alloc + INTSTACK_SIZE,
+#if CONFIG_SMP_NCPUS > 1
+  (uint32_t)g_intstack_alloc + (2 * INTSTACK_SIZE),
+#if CONFIG_SMP_NCPUS > 2
+  (uint32_t)g_intstack_alloc + (3 * INTSTACK_SIZE),
+#if CONFIG_SMP_NCPUS > 3
+  (uint32_t)g_intstack_alloc + (4 * INTSTACK_SIZE),
+#if CONFIG_SMP_NCPUS > 4
+  (uint32_t)g_intstack_alloc + (5 * INTSTACK_SIZE),
+#if CONFIG_SMP_NCPUS > 5
+  (uint32_t)g_intstack_alloc + (6 * INTSTACK_SIZE),
+#endif /* CONFIG_SMP_NCPUS > 5 */
+#endif /* CONFIG_SMP_NCPUS > 4 */
+#endif /* CONFIG_SMP_NCPUS > 3 */
+#endif /* CONFIG_SMP_NCPUS > 2 */
+#endif /* CONFIG_SMP_NCPUS > 1 */
+};
+#endif /* defined(CONFIG_SMP) && CONFIG_ARCH_INTERRUPTSTACK > 7 */
+
 /* This is the address of the  exception vector table (determined by the
  * linker script).
  */
@@ -604,3 +638,35 @@ int up_prioritize_irq(int irq, int priority)
   return OK;
 }
 #endif
+
+/****************************************************************************
+ * Name: arm_intstack_base
+ *
+ * Description:
+ *   Return a pointer to the "base" the correct interrupt stack allocation
+ *   for the current CPU. NOTE: Here, the base means "top" of the stack
+ *
+ ****************************************************************************/
+
+#if defined(CONFIG_SMP) && CONFIG_ARCH_INTERRUPTSTACK > 7
+uintptr_t arm_intstack_base(void)
+{
+  return g_cpu_intstack_top[up_cpu_index()];
+}
+#endif
+
+/****************************************************************************
+ * Name: arm_intstack_alloc
+ *
+ * Description:
+ *   Return a pointer to the "alloc" the correct interrupt stack allocation
+ *   for the current CPU.
+ *
+ ****************************************************************************/
+
+#if defined(CONFIG_SMP) && CONFIG_ARCH_INTERRUPTSTACK > 7
+uintptr_t arm_intstack_alloc(void)
+{
+  return g_cpu_intstack_top[up_cpu_index()] - INTSTACK_SIZE;
+}
+#endif

arch/arm/src/cxd56xx/cxd56_irq.h

@@ -48,6 +48,12 @@
  * Pre-processor Definitions
  ****************************************************************************/
 
+/* The size of one interrupt stack.  This is the configured value aligned
+ * the 8-bytes as required by the ARM EABI.
+ */
+
+#define INTSTACK_SIZE  (CONFIG_ARCH_INTERRUPTSTACK & ~7)
+
 /****************************************************************************
  * Public Types
  ****************************************************************************/
@@ -67,14 +73,15 @@ extern "C"
 #define EXTERN extern
 #endif
 
-/****************************************************************************
- * Inline Functions
- ****************************************************************************/
-
 /****************************************************************************
  * Public Functions Prototypes
  ****************************************************************************/
 
+#if defined(CONFIG_SMP) && CONFIG_ARCH_INTERRUPTSTACK > 7
+EXTERN uintptr_t arm_intstack_base(void);
+EXTERN uintptr_t arm_intstack_alloc(void);
+#endif
+
 #undef EXTERN
 #if defined(__cplusplus)
 }

arch/arm/src/cxd56xx/cxd56_serial.c

@@ -778,8 +778,6 @@ static int up_ioctl(FAR struct file *filep, int cmd, unsigned long arg)
 
           flags = spin_lock_irqsave();
 
-          cfsetispeed(termiosp, priv->baud);
-
           termiosp->c_cflag = ((priv->parity != 0) ? PARENB : 0) |
                               ((priv->parity == 1) ? PARODD : 0) |
 #ifdef CONFIG_SERIAL_OFLOWCONTROL
@@ -790,6 +788,8 @@ static int up_ioctl(FAR struct file *filep, int cmd, unsigned long arg)
 #endif
                               ((priv->stopbits2) ? CSTOPB : 0);
 
+          cfsetispeed(termiosp, priv->baud);
+
           switch (priv->bits)
             {
               case 5:

arch/arm/src/efm32/efm32_serial.c

@@ -68,7 +68,9 @@
 /****************************************************************************
  * Pre-processor Definitions
  ****************************************************************************/
-/* Some sanity checks *******************************************************/
+
+/* Some sanity checks */
+
 /* Is there at least one UART enabled and configured as a RS-232 device? */
 
 #ifndef HAVE_UART_DEVICE
@@ -81,8 +83,9 @@
 
 #ifdef USE_SERIALDRIVER
 
-/* Which UART with be ttyS0/console and which tty1-4?  The console will always
- * be ttyS0.  If there is no console then will use the lowest numbered UART.
+/* Which UART with be ttyS0/console and which tty1-4?  The console will
+ * always be ttyS0.  If there is no console then will use the lowest
+ * numbered UART.
  */
 
 /* First pick the console and ttys0.  This could be any of USART0-2 or
@@ -240,7 +243,8 @@ struct efm32_usart_s
  * Private Function Prototypes
  ****************************************************************************/
 
-static inline uint32_t efm32_serialin(struct efm32_usart_s *priv, int offset);
+static inline uint32_t efm32_serialin(struct efm32_usart_s *priv,
+                                      int offset);
 static inline void efm32_serialout(struct efm32_usart_s *priv, int offset,
                                    uint32_t value);
 static inline void efm32_setuartint(struct efm32_usart_s *priv);
@@ -331,18 +335,18 @@ static struct efm32_usart_s g_usart0priv =
 
 static struct uart_dev_s g_usart0port =
 {
-  .recv      =
-  {
-    .size    = CONFIG_USART0_RXBUFSIZE,
-    .buffer  = g_usart0rxbuffer,
-  },
-  .xmit      =
-  {
-    .size    = CONFIG_USART0_TXBUFSIZE,
-    .buffer  = g_usart0txbuffer,
-   },
-  .ops       = &g_uart_ops,
-  .priv      = &g_usart0priv,
+  .recv        =
+    {
+      .size    = CONFIG_USART0_RXBUFSIZE,
+      .buffer  = g_usart0rxbuffer,
+    },
+  .xmit        =
+    {
+      .size    = CONFIG_USART0_TXBUFSIZE,
+      .buffer  = g_usart0txbuffer,
+    },
+  .ops         = &g_uart_ops,
+  .priv        = &g_usart0priv,
 };
 #endif
 
@@ -367,18 +371,18 @@ static struct efm32_usart_s g_usart1priv =
 
 static struct uart_dev_s g_usart1port =
 {
-  .recv      =
-  {
-    .size    = CONFIG_USART1_RXBUFSIZE,
-    .buffer  = g_usart1rxbuffer,
-  },
-  .xmit      =
-  {
-    .size    = CONFIG_USART1_TXBUFSIZE,
-    .buffer  = g_usart1txbuffer,
-   },
-  .ops       = &g_uart_ops,
-  .priv      = &g_usart1priv,
+  .recv        =
+    {
+      .size    = CONFIG_USART1_RXBUFSIZE,
+      .buffer  = g_usart1rxbuffer,
+    },
+  .xmit        =
+    {
+      .size    = CONFIG_USART1_TXBUFSIZE,
+      .buffer  = g_usart1txbuffer,
+    },
+  .ops         = &g_uart_ops,
+  .priv        = &g_usart1priv,
 };
 #endif
 
@@ -403,18 +407,18 @@ static struct efm32_usart_s g_usart2priv =
 
 static struct uart_dev_s g_usart2port =
 {
-  .recv     =
-  {
-    .size   = CONFIG_USART2_RXBUFSIZE,
-    .buffer = g_usart2rxbuffer,
-  },
-  .xmit     =
-  {
-    .size   = CONFIG_USART2_TXBUFSIZE,
-    .buffer = g_usart2txbuffer,
-   },
-  .ops      = &g_uart_ops,
-  .priv     = &g_usart2priv,
+  .recv       =
+    {
+      .size   = CONFIG_USART2_RXBUFSIZE,
+      .buffer = g_usart2rxbuffer,
+    },
+  .xmit       =
+    {
+      .size   = CONFIG_USART2_TXBUFSIZE,
+      .buffer = g_usart2txbuffer,
+    },
+  .ops        = &g_uart_ops,
+  .priv       = &g_usart2priv,
 };
 #endif
 
@@ -439,18 +443,18 @@ static struct efm32_usart_s g_uart0priv =
 
 static struct uart_dev_s g_uart0port =
 {
-  .recv      =
-  {
-    .size    = CONFIG_UART0_RXBUFSIZE,
-    .buffer  = g_uart0rxbuffer,
-  },
-  .xmit      =
-  {
-    .size    = CONFIG_UART0_TXBUFSIZE,
-    .buffer  = g_uart0txbuffer,
-   },
-  .ops       = &g_uart_ops,
-  .priv      = &g_uart0priv,
+  .recv        =
+    {
+      .size    = CONFIG_UART0_RXBUFSIZE,
+      .buffer  = g_uart0rxbuffer,
+    },
+  .xmit        =
+    {
+      .size    = CONFIG_UART0_TXBUFSIZE,
+      .buffer  = g_uart0txbuffer,
+    },
+  .ops         = &g_uart_ops,
+  .priv        = &g_uart0priv,
 };
 #endif
 
@@ -475,18 +479,18 @@ static struct efm32_usart_s g_uart1priv =
 
 static struct uart_dev_s g_uart1port =
 {
-  .recv     =
-  {
-    .size   = CONFIG_UART1_RXBUFSIZE,
-    .buffer = g_uart1rxbuffer,
-  },
-  .xmit     =
-  {
-    .size   = CONFIG_UART1_TXBUFSIZE,
-    .buffer = g_uart1txbuffer,
-   },
-  .ops      = &g_uart_ops,
-  .priv     = &g_uart1priv,
+  .recv       =
+    {
+      .size   = CONFIG_UART1_RXBUFSIZE,
+      .buffer = g_uart1rxbuffer,
+    },
+  .xmit       =
+    {
+      .size   = CONFIG_UART1_TXBUFSIZE,
+      .buffer = g_uart1txbuffer,
+    },
+  .ops        = &g_uart_ops,
+  .priv       = &g_uart1priv,
 };
 #endif
 
@@ -530,7 +534,9 @@ static void efm32_restoreuartint(struct efm32_usart_s *priv, uint32_t ien)
 {
   irqstate_t flags;
 
-  /* Re-enable/re-disable interrupts corresponding to the state of bits in ien */
+  /* Re-enable/re-disable interrupts corresponding to the state of bits in
+   * ien
+   */
 
   flags     = enter_critical_section();
   priv->ien = ien;
@@ -624,14 +630,15 @@ static void efm32_shutdown(struct uart_dev_s *dev)
  * Name: efm32_attach
  *
  * Description:
- *   Configure the UART to operation in interrupt driven mode.  This method is
- *   called when the serial port is opened.  Normally, this is just after the
+ *   Configure the UART to operation in interrupt driven mode.  This method
+ *   is called when the serial port is opened.  Normally, this is just after
  *   the setup() method is called, however, the serial console may operate in
  *   a non-interrupt driven mode during the boot phase.
  *
- *   RX and TX interrupts are not enabled when by the attach method (unless the
- *   hardware supports multiple levels of interrupt enabling).  The RX and TX
- *   interrupts are not enabled until the txint() and rxint() methods are called.
+ *   RX and TX interrupts are not enabled when by the attach method (unless
+ *   the hardware supports multiple levels of interrupt enabling).  The RX
+ *   and TX interrupts are not enabled until the txint() and rxint() methods
+ *   are called.
  *
  ****************************************************************************/
 
@@ -668,8 +675,8 @@ static int efm32_attach(struct uart_dev_s *dev)
  *
  * Description:
  *   Detach UART interrupts.  This method is called when the serial port is
- *   closed normally just before the shutdown method is called.  The exception
- *   is the serial console which is never shutdown.
+ *   closed normally just before the shutdown method is called.  The
+ *   exception is the serial console which is never shutdown.
  *
  ****************************************************************************/
 
@@ -839,8 +846,6 @@ static int efm32_ioctl(struct file *filep, int cmd, unsigned long arg)
             break;
           }
 
-        cfsetispeed(termiosp, priv->config->baud);
-
         /* Note that since we only support 8/9 bit modes and
          * there is no way to report 9-bit mode, we always claim 8.
          */
@@ -848,6 +853,8 @@ static int efm32_ioctl(struct file *filep, int cmd, unsigned long arg)
         termiosp->c_cflag = CS8;
 
         /* TODO: PARENB, PARODD, CSTOPB, CCTS_IFLOW, CCTS_OFLOW */
+
+        cfsetispeed(termiosp, priv->config->baud);
       }
       break;
 
@@ -979,8 +986,8 @@ static void efm32_rxint(struct uart_dev_s *dev, bool enable)
   flags = enter_critical_section();
   if (enable)
     {
-      /* Receive an interrupt when their is anything in the Rx data register (or an Rx
-       * timeout occurs).
+      /* Receive an interrupt when their is anything in the Rx data register
+       * (or an RX timeout occurs).
        */
 
 #ifndef CONFIG_SUPPRESS_SERIAL_INTS
@@ -1011,7 +1018,8 @@ static bool efm32_rxavailable(struct uart_dev_s *dev)
 
   /* Return true if the receive data is available (RXDATAV). */
 
-  return (efm32_serialin(priv, EFM32_USART_STATUS_OFFSET) & USART_STATUS_RXDATAV) != 0;
+  return (efm32_serialin(priv, EFM32_USART_STATUS_OFFSET) & \
+          USART_STATUS_RXDATAV) != 0;
 }
 
 /****************************************************************************
@@ -1085,7 +1093,8 @@ static bool efm32_txready(struct uart_dev_s *dev)
    * buffer is half-full or empty.
    */
 
-  return (efm32_serialin(priv, EFM32_USART_STATUS_OFFSET) & USART_STATUS_TXBL) != 0;
+  return (efm32_serialin(priv, EFM32_USART_STATUS_OFFSET) & \
+          USART_STATUS_TXBL) != 0;
 }
 
 /****************************************************************************
@@ -1104,7 +1113,8 @@ static bool efm32_txempty(struct uart_dev_s *dev)
    * data is available in the transmit buffer.
    */
 
-  return (efm32_serialin(priv, EFM32_USART_STATUS_OFFSET) & USART_STATUS_TXC) != 0;
+  return (efm32_serialin(priv, EFM32_USART_STATUS_OFFSET) & \
+          USART_STATUS_TXC) != 0;
 }
 
 /****************************************************************************
@@ -1118,8 +1128,8 @@ static bool efm32_txempty(struct uart_dev_s *dev)
  *   Performs the low level UART initialization early in debug so that the
  *   serial console will be available during bootup.  This must be called
  *   before arm_serialinit.  NOTE:  This function depends on GPIO pin
- *   configuration performed in efm32_consoleinit() and main clock iniialization
- *   performed in efm32_clkinitialize().
+ *   configuration performed in efm32_consoleinit() and main clock
+ *   iniialization performed in efm32_clkinitialize().
  *
  ****************************************************************************/
 

arch/arm/src/imx6/Make.defs

@@ -117,6 +117,10 @@ endif
 
 CMN_CSRCS += arm_cache.c
 
+ifeq ($(CONFIG_ARCH_L2CACHE),y)
+CMN_CSRCS += arm_l2cc_pl310.c
+endif
+
 ifeq ($(CONFIG_ARCH_FPU),y)
 CMN_ASRCS += arm_savefpu.S arm_restorefpu.S
 CMN_CSRCS += arm_copyarmstate.c

arch/arm/src/imx6/chip.h

@@ -61,22 +61,11 @@
 
 #define CHIP_MPCORE_VBASE IMX_ARMMP_VSECTION
 
-/****************************************************************************
- * Public Types
- ****************************************************************************/
+/* arch/arm/src/armv7-a/l2cc_pl310.h includes this file and expects it
+ * to provide the address of the L2CC-PL310 implementation.
+ */
 
-/****************************************************************************
- * Public Data
- ****************************************************************************/
-
-#ifdef __ASSEMBLY__
-
-#if defined(CONFIG_SMP) && CONFIG_ARCH_INTERRUPTSTACK > 7
-	.globl	g_irqstack_top
-	.globl	g_fiqstack_top
-#endif /* CONFIG_SMP && CONFIG_ARCH_INTERRUPTSTACK > 7 */
-
-#endif /* __ASSEMBLY__ */
+#define L2CC_VBASE IMX_PL310_VBASE
 
 /****************************************************************************
  * Macro Definitions
@@ -84,7 +73,7 @@
 
 #ifdef __ASSEMBLY__
 
-/***************************************************************************
+/****************************************************************************
  * Name: cpuindex
  *
  * Description:
@@ -93,30 +82,30 @@
  ****************************************************************************/
 
 #if defined(CONFIG_SMP) && CONFIG_ARCH_INTERRUPTSTACK > 7
-	.macro	cpuindex, index
-	mrc		p15, 0, \index, c0, c0, 5	/* Read the MPIDR */
-	and		\index, \index, #3			/* Bits 0-1=CPU ID */
-	.endm
+  .macro  cpuindex, index
+  mrc  p15, 0, \index, c0, c0, 5  /* Read the MPIDR */
+  and  \index, \index, #3         /* Bits 0-1=CPU ID */
+  .endm
 #endif
 
-/***************************************************************************
+/****************************************************************************
  * Name: setirqstack
  *
  * Description:
  *   Set the current stack pointer to the  -"top" of the IRQ interrupt
  *   stack for the current CPU.
  *
- ***************************************************************************/
+ ****************************************************************************/
 
 #if defined(CONFIG_SMP) && CONFIG_ARCH_INTERRUPTSTACK > 7
-	.macro	setirqstack, tmp1, tmp2
-	mrc		p15, 0, \tmp1, c0, c0, 5	/* tmp1=MPIDR */
-	and		\tmp1, \tmp1, #3			/* Bits 0-1=CPU ID */
-	ldr		\tmp2, =g_irqstack_top		/* tmp2=Array of IRQ stack pointers */
-	lsls	\tmp1, \tmp1, #2			/* tmp1=Array byte offset */
-	add		\tmp2, \tmp2, \tmp1			/* tmp2=Offset address into array */
-	ldr		sp, [\tmp2, #0]				/* sp=Address in stack allocation */
-	.endm
+  .macro  setirqstack, tmp1, tmp2
+  mrc  p15, 0, \tmp1, c0, c0, 5  /* tmp1=MPIDR */
+  and  \tmp1, \tmp1, #3          /* Bits 0-1=CPU ID */
+  ldr  \tmp2, =g_irqstack_top    /* tmp2=Array of IRQ stack pointers */
+  lsls \tmp1, \tmp1, #2          /* tmp1=Array byte offset */
+  add  \tmp2, \tmp2, \tmp1       /* tmp2=Offset address into array */
+  ldr  sp, [\tmp2, #0]           /* sp=Address in stack allocation */
+  .endm
 #endif
 
 /****************************************************************************
@@ -129,67 +118,16 @@
  ****************************************************************************/
 
 #if defined(CONFIG_SMP) && CONFIG_ARCH_INTERRUPTSTACK > 7
-	.macro	setfiqstack, tmp1, tmp2
-	mrc		p15, 0, \tmp1, c0, c0, 5	/* tmp1=MPIDR */
-	and		\tmp1, \tmp1, #3			/* Bits 0-1=CPU ID */
-	ldr		\tmp2, =g_fiqstack_top		/* tmp2=Array of FIQ stack pointers */
-	lsls	\tmp1, \tmp1, #2			/* tmp1=Array byte offset */
-	add		\tmp2, \tmp2, \tmp1			/* tmp2=Offset address into array */
-	ldr		sp, [\tmp2, #0]				/* sp=Address in stack allocation */
-	.endm
+  .macro  setfiqstack, tmp1, tmp2
+  mrc  p15, 0, \tmp1, c0, c0, 5  /* tmp1=MPIDR */
+  and  \tmp1, \tmp1, #3          /* Bits 0-1=CPU ID */
+  ldr  \tmp2, =g_fiqstack_top    /* tmp2=Array of FIQ stack pointers */
+  lsls \tmp1, \tmp1, #2          /* tmp1=Array byte offset */
+  add  \tmp2, \tmp2, \tmp1       /* tmp2=Offset address into array */
+  ldr  sp, [\tmp2, #0]           /* sp=Address in stack allocation */
+  .endm
 #endif
 
 #endif /* __ASSEMBLY__ */
 
-/****************************************************************************
- * Inline Functions
- ****************************************************************************/
-
-#ifndef __ASSEMBLY__
-
-/****************************************************************************
- * Name: arm_intstack_base
- *
- * Description:
- *   Return a pointer to the "base" the correct interrupt stack allocation
- *   for the  current CPU.
- *
- ****************************************************************************/
-
-#if defined(CONFIG_SMP) && CONFIG_ARCH_INTERRUPTSTACK > 7
-static inline uintptr_t arm_intstack_base(void)
-{
-  uintptr_t base = (uintptr_t)g_irqstack_alloc;
-#if CONFIG_SMP_NCPUS > 1
-  uint32_t cpu = up_cpu_index();
-
-  base += cpu * INTSTACK_SIZE;
-#endif
-
-  return base;
-}
-#endif
-
-/****************************************************************************
- * Name: arm_intstack_top
- *
- * Description:
- *   Return a pointer to the "top" the correct interrupt stack for the
- *   current CPU.
- *
- ****************************************************************************/
-
-#if defined(CONFIG_SMP) && CONFIG_ARCH_INTERRUPTSTACK > 7
-static inline uintptr_t arm_intstack_top(void)
-{
-  return arm_intstack_base() + INTSTACK_SIZE;
-}
-#endif
-
-#endif /* !__ASSEMBLY__ */
-
-/****************************************************************************
- * Public Functions
- ****************************************************************************/
-
 #endif /* __ARCH_ARM_SRC_IMX6_CHIP_H */

arch/arm/src/imx6/imx_irq.c

@@ -90,13 +90,13 @@ uintptr_t g_irqstack_top[CONFIG_SMP_NCPUS] =
 {
   (uintptr_t)g_irqstack_alloc + INTSTACK_SIZE,
 #if CONFIG_SMP_NCPUS > 1
-  (uintptr_t)g_irqstack_alloc + 2 * INTSTACK_SIZE,
+  (uintptr_t)g_irqstack_alloc + (2 * INTSTACK_SIZE),
 #endif
 #if CONFIG_SMP_NCPUS > 2
-  (uintptr_t)g_irqstack_alloc + 3 * INTSTACK_SIZE,
+  (uintptr_t)g_irqstack_alloc + (3 * INTSTACK_SIZE),
 #endif
 #if CONFIG_SMP_NCPUS > 3
-  (uintptr_t)g_irqstack_alloc + 4 * INTSTACK_SIZE
+  (uintptr_t)g_irqstack_alloc + (4 * INTSTACK_SIZE)
 #endif
 };
 
@@ -186,3 +186,35 @@ void up_irqinitialize(void)
   up_irq_enable();
 #endif
 }
+
+/****************************************************************************
+ * Name: arm_intstack_base
+ *
+ * Description:
+ *   Return a pointer to the "base" the correct interrupt stack allocation
+ *   for the current CPU. NOTE: Here, the base means "top" of the stack
+ *
+ ****************************************************************************/
+
+#if defined(CONFIG_SMP) && CONFIG_ARCH_INTERRUPTSTACK > 7
+uintptr_t arm_intstack_base(void)
+{
+  return g_irqstack_top[up_cpu_index()];
+}
+#endif
+
+/****************************************************************************
+ * Name: arm_intstack_alloc
+ *
+ * Description:
+ *   Return a pointer to the "alloc" the correct interrupt stack allocation
+ *   for the current CPU.
+ *
+ ****************************************************************************/
+
+#if defined(CONFIG_SMP) && CONFIG_ARCH_INTERRUPTSTACK > 7
+uintptr_t arm_intstack_alloc(void)
+{
+  return g_irqstack_top[up_cpu_index()] - INTSTACK_SIZE;
+}
+#endif

arch/arm/src/imx6/imx_irq.h

@@ -67,25 +67,15 @@ extern "C"
 #define EXTERN extern
 #endif
 
-#if defined(CONFIG_SMP) && CONFIG_ARCH_INTERRUPTSTACK > 7
-/* In the SMP configuration, we will need custom IRQ and FIQ stacks.
- * These definitions provide the aligned stack allocations.
- */
-
-EXTERN uint64_t g_irqstack_alloc[];
-EXTERN uint64_t g_fiqstack_alloc[];
-
-/* These are arrays that point to the top of each interrupt stack */
-
-EXTERN uintptr_t g_irqstack_top[CONFIG_SMP_NCPUS];
-EXTERN uintptr_t g_irqstack_top[CONFIG_SMP_NCPUS];
-
-#endif /* CONFIG_SMP && CONFIG_ARCH_INTERRUPTSTACK > 7 */
-
 /****************************************************************************
  * Public Function Prototypes
  ****************************************************************************/
 
+#if defined(CONFIG_SMP) && CONFIG_ARCH_INTERRUPTSTACK > 7
+EXTERN uintptr_t arm_intstack_base(void);
+EXTERN uintptr_t arm_intstack_alloc(void);
+#endif
+
 #undef EXTERN
 #if defined(__cplusplus)
 }

arch/arm/src/imxrt/imxrt_serial.c

@@ -321,29 +321,29 @@
 
 struct imxrt_uart_s
 {
-  uint32_t uartbase;    /* Base address of UART registers */
-  uint32_t baud;        /* Configured baud */
-  uint32_t ie;          /* Saved enabled interrupts */
-  uint8_t  irq;         /* IRQ associated with this UART */
-  uint8_t  parity;      /* 0=none, 1=odd, 2=even */
-  uint8_t  bits;        /* Number of bits (7 or 8) */
+  uint32_t uartbase;        /* Base address of UART registers */
+  uint32_t baud;            /* Configured baud */
+  uint32_t ie;              /* Saved enabled interrupts */
+  uint8_t  irq;             /* IRQ associated with this UART */
+  uint8_t  parity;          /* 0=none, 1=odd, 2=even */
+  uint8_t  bits;            /* Number of bits (7 or 8) */
 #if defined(CONFIG_SERIAL_RS485CONTROL) || defined(CONFIG_SERIAL_IFLOWCONTROL)
-  uint8_t  inviflow:1;  /* Invert RTS sense */
+  uint8_t  inviflow:1;      /* Invert RTS sense */
   const uint32_t rts_gpio;  /* U[S]ART RTS GPIO pin configuration */
 #endif
 #ifdef CONFIG_SERIAL_OFLOWCONTROL
   const uint32_t cts_gpio;  /* U[S]ART CTS GPIO pin configuration */
 #endif
 
-  uint8_t  stopbits2:1; /* 1: Configure with 2 stop bits vs 1 */
+  uint8_t  stopbits2:1;     /* 1: Configure with 2 stop bits vs 1 */
 #ifdef CONFIG_SERIAL_IFLOWCONTROL
-  uint8_t  iflow:1;     /* input flow control (RTS) enabled */
+  uint8_t  iflow:1;         /* input flow control (RTS) enabled */
 #endif
 #ifdef CONFIG_SERIAL_OFLOWCONTROL
-  uint8_t  oflow:1;     /* output flow control (CTS) enabled */
+  uint8_t  oflow:1;         /* output flow control (CTS) enabled */
 #endif
 #ifdef CONFIG_SERIAL_RS485CONTROL
-  uint8_t rs485mode:1;  /* We are in RS485 (RTS on TX) mode */
+  uint8_t rs485mode:1;      /* We are in RS485 (RTS on TX) mode */
 #endif
 };
 
@@ -855,8 +855,8 @@ static inline uint32_t imxrt_serialin(struct imxrt_uart_s *priv,
  * Name: imxrt_serialout
  ****************************************************************************/
 
-static inline void imxrt_serialout(struct imxrt_uart_s *priv, uint32_t offset,
-                                   uint32_t value)
+static inline void imxrt_serialout(struct imxrt_uart_s *priv,
+                                   uint32_t offset, uint32_t value)
 {
   putreg32(value, priv->uartbase + offset);
 }
@@ -949,11 +949,13 @@ static int imxrt_setup(struct uart_dev_s *dev)
 
   ret = imxrt_lpuart_configure(priv->uartbase, &config);
 
-  priv->ie = imxrt_serialin(priv, IMXRT_LPUART_CTRL_OFFSET) & LPUART_ALL_INTS;
+  priv->ie = imxrt_serialin(priv, IMXRT_LPUART_CTRL_OFFSET) & \
+             LPUART_ALL_INTS;
   return ret;
 
 #else
-  priv->ie = imxrt_serialin(priv, IMXRT_LPUART_CTRL_OFFSET) & LPUART_ALL_INTS;
+  priv->ie = imxrt_serialin(priv, IMXRT_LPUART_CTRL_OFFSET) & \
+             LPUART_ALL_INTS;
   return OK;
 #endif
 }
@@ -1155,10 +1157,6 @@ static int imxrt_ioctl(struct file *filep, int cmd, unsigned long arg)
             break;
           }
 
-        /* Return baud */
-
-        cfsetispeed(termiosp, priv->baud);
-
         /* Return parity */
 
         termiosp->c_cflag = ((priv->parity != 0) ? PARENB : 0) |
@@ -1176,6 +1174,10 @@ static int imxrt_ioctl(struct file *filep, int cmd, unsigned long arg)
 #ifdef CONFIG_SERIAL_IFLOWCONTROL
         termiosp->c_cflag |= ((priv->iflow) ? CRTS_IFLOW : 0);
 #endif
+        /* Return baud */
+
+        cfsetispeed(termiosp, priv->baud);
+
         /* Return number of bits */
 
         switch (priv->bits)
@@ -1327,7 +1329,9 @@ static int imxrt_ioctl(struct file *filep, int cmd, unsigned long arg)
         stat   = imxrt_serialin(priv, IMXRT_LPUART_STAT_OFFSET);
         regval = ctrl;
 
-        /* {R|T}XINV bit field can only be written when the receiver is disabled (RE=0). */
+        /* {R|T}XINV bit field can only be written when the receiver
+         * is disabled (RE=0).
+         */
 
         regval &= ~LPUART_CTRL_RE;
 

arch/arm/src/kinetis/kinetis_serial.c

@@ -76,7 +76,8 @@
  * Pre-processor Definitions
  ****************************************************************************/
 
-/* Some sanity checks *******************************************************/
+/* Some sanity checks */
+
 /* Is there at least one UART enabled and configured as a RS-232 device? */
 
 #ifndef HAVE_UART_DEVICE
@@ -502,27 +503,26 @@ static struct up_dev_s g_uart0priv =
   .rxdma_reqsrc   = KINETIS_DMA_REQUEST_SRC_UART0_RX,
   .rxfifo         = g_uart0rxfifo,
 #endif
-
 };
 
 static uart_dev_t g_uart0port =
 {
-  .recv     =
-  {
-    .size   = CONFIG_UART0_RXBUFSIZE,
-    .buffer = g_uart0rxbuffer,
-  },
-  .xmit     =
-  {
-    .size   = CONFIG_UART0_TXBUFSIZE,
-    .buffer = g_uart0txbuffer,
-   },
+  .recv       =
+    {
+      .size   = CONFIG_UART0_RXBUFSIZE,
+      .buffer = g_uart0rxbuffer,
+    },
+  .xmit       =
+    {
+      .size   = CONFIG_UART0_TXBUFSIZE,
+      .buffer = g_uart0txbuffer,
+    },
 #ifdef CONFIG_KINETIS_UART0_RXDMA
-  .ops      = &g_uart_dma_ops,
+  .ops        = &g_uart_dma_ops,
 #else
-  .ops      = &g_uart_ops,
+  .ops        = &g_uart_ops,
 #endif
-  .priv     = &g_uart0priv,
+  .priv       = &g_uart0priv,
 };
 #endif
 
@@ -557,22 +557,22 @@ static struct up_dev_s g_uart1priv =
 
 static uart_dev_t g_uart1port =
 {
-  .recv     =
-  {
-    .size   = CONFIG_UART1_RXBUFSIZE,
-    .buffer = g_uart1rxbuffer,
-  },
-  .xmit     =
-  {
-    .size   = CONFIG_UART1_TXBUFSIZE,
-    .buffer = g_uart1txbuffer,
-   },
+  .recv       =
+    {
+      .size   = CONFIG_UART1_RXBUFSIZE,
+      .buffer = g_uart1rxbuffer,
+    },
+  .xmit       =
+    {
+      .size   = CONFIG_UART1_TXBUFSIZE,
+      .buffer = g_uart1txbuffer,
+    },
 #ifdef CONFIG_KINETIS_UART1_RXDMA
-  .ops      = &g_uart_dma_ops,
+  .ops        = &g_uart_dma_ops,
 #else
-  .ops      = &g_uart_ops,
+  .ops        = &g_uart_ops,
 #endif
-  .priv     = &g_uart1priv,
+  .priv       = &g_uart1priv,
 };
 #endif
 
@@ -607,22 +607,22 @@ static struct up_dev_s g_uart2priv =
 
 static uart_dev_t g_uart2port =
 {
-  .recv     =
-  {
-    .size   = CONFIG_UART2_RXBUFSIZE,
-    .buffer = g_uart2rxbuffer,
-  },
-  .xmit     =
-  {
-    .size   = CONFIG_UART2_TXBUFSIZE,
-    .buffer = g_uart2txbuffer,
-   },
+  .recv       =
+    {
+      .size   = CONFIG_UART2_RXBUFSIZE,
+      .buffer = g_uart2rxbuffer,
+    },
+  .xmit       =
+    {
+      .size   = CONFIG_UART2_TXBUFSIZE,
+      .buffer = g_uart2txbuffer,
+    },
 #ifdef CONFIG_KINETIS_UART2_RXDMA
-  .ops      = &g_uart_dma_ops,
+  .ops        = &g_uart_dma_ops,
 #else
-  .ops      = &g_uart_ops,
+  .ops        = &g_uart_ops,
 #endif
-  .priv     = &g_uart2priv,
+  .priv       = &g_uart2priv,
 };
 #endif
 
@@ -657,22 +657,22 @@ static struct up_dev_s g_uart3priv =
 
 static uart_dev_t g_uart3port =
 {
-  .recv     =
-  {
-    .size   = CONFIG_UART3_RXBUFSIZE,
-    .buffer = g_uart3rxbuffer,
-  },
-  .xmit     =
-  {
-    .size   = CONFIG_UART3_TXBUFSIZE,
-    .buffer = g_uart3txbuffer,
-   },
+  .recv       =
+    {
+      .size   = CONFIG_UART3_RXBUFSIZE,
+      .buffer = g_uart3rxbuffer,
+    },
+  .xmit       =
+    {
+      .size   = CONFIG_UART3_TXBUFSIZE,
+      .buffer = g_uart3txbuffer,
+    },
 #ifdef CONFIG_KINETIS_UART3_RXDMA
-  .ops      = &g_uart_dma_ops,
+  .ops        = &g_uart_dma_ops,
 #else
-  .ops      = &g_uart_ops,
+  .ops        = &g_uart_ops,
 #endif
-  .priv     = &g_uart3priv,
+  .priv       = &g_uart3priv,
 };
 #endif
 
@@ -707,22 +707,22 @@ static struct up_dev_s g_uart4priv =
 
 static uart_dev_t g_uart4port =
 {
-  .recv     =
-  {
-    .size   = CONFIG_UART4_RXBUFSIZE,
-    .buffer = g_uart4rxbuffer,
-  },
-  .xmit     =
-  {
-    .size   = CONFIG_UART4_TXBUFSIZE,
-    .buffer = g_uart4txbuffer,
-   },
+  .recv       =
+    {
+      .size   = CONFIG_UART4_RXBUFSIZE,
+      .buffer = g_uart4rxbuffer,
+    },
+  .xmit       =
+    {
+      .size   = CONFIG_UART4_TXBUFSIZE,
+      .buffer = g_uart4txbuffer,
+    },
 #ifdef CONFIG_KINETIS_UART4_RXDMA
-  .ops      = &g_uart_dma_ops,
+  .ops        = &g_uart_dma_ops,
 #else
-  .ops      = &g_uart_ops,
+  .ops        = &g_uart_ops,
 #endif
-  .priv     = &g_uart4priv,
+  .priv       = &g_uart4priv,
 };
 #endif
 
@@ -757,22 +757,22 @@ static struct up_dev_s g_uart5priv =
 
 static uart_dev_t g_uart5port =
 {
-  .recv     =
-  {
-    .size   = CONFIG_UART5_RXBUFSIZE,
-    .buffer = g_uart5rxbuffer,
-  },
-  .xmit     =
-  {
-    .size   = CONFIG_UART5_TXBUFSIZE,
-    .buffer = g_uart5txbuffer,
-   },
+  .recv       =
+    {
+      .size   = CONFIG_UART5_RXBUFSIZE,
+      .buffer = g_uart5rxbuffer,
+    },
+  .xmit       =
+    {
+      .size   = CONFIG_UART5_TXBUFSIZE,
+      .buffer = g_uart5txbuffer,
+    },
 #ifdef CONFIG_KINETIS_UART5_RXDMA
-  .ops      = &g_uart_dma_ops,
+  .ops        = &g_uart_dma_ops,
 #else
-  .ops      = &g_uart_ops,
+  .ops        = &g_uart_ops,
 #endif
-  .priv     = &g_uart5priv,
+  .priv       = &g_uart5priv,
 };
 #endif
 
@@ -793,7 +793,8 @@ static inline uint8_t up_serialin(struct up_dev_s *priv, int offset)
  * Name: up_serialout
  ****************************************************************************/
 
-static inline void up_serialout(struct up_dev_s *priv, int offset, uint8_t value)
+static inline void up_serialout(struct up_dev_s *priv, int offset,
+                                uint8_t value)
 {
   putreg8(value, priv->uartbase + offset);
 }
@@ -807,7 +808,9 @@ static void up_setuartint(struct up_dev_s *priv)
   irqstate_t flags;
   uint8_t regval;
 
-  /* Re-enable/re-disable interrupts corresponding to the state of bits in ie */
+  /* Re-enable/re-disable interrupts corresponding to the state of bits in
+   * ie
+   */
 
   flags    = enter_critical_section();
   regval   = up_serialin(priv, KINETIS_UART_C2_OFFSET);
@@ -825,7 +828,9 @@ static void up_restoreuartint(struct up_dev_s *priv, uint8_t ie)
 {
   irqstate_t flags;
 
-  /* Re-enable/re-disable interrupts corresponding to the state of bits in ie */
+  /* Re-enable/re-disable interrupts corresponding to the state of bits in
+   * ie
+   */
 
   flags    = enter_critical_section();
   priv->ie = ie & UART_C2_ALLINTS;
@@ -952,23 +957,25 @@ static int up_dma_setup(struct uart_dev_s *dev)
         }
     }
 
-  /* Acquire the DMA channel.*/
+  /* Acquire the DMA channel. */
 
   rxdma = kinetis_dmachannel(priv->rxdma_reqsrc,
                              priv->uartbase + KINETIS_UART_D_OFFSET,
                              KINETIS_DMA_DATA_SZ_8BIT,
                              KINETIS_DMA_DIRECTION_PERIPHERAL_TO_MEMORY);
   if (rxdma == NULL)
-  {
-    return -EBUSY;
-  }
+    {
+      return -EBUSY;
+    }
 
   /* Configure for circular DMA reception into the RX FIFO */
 
   kinetis_dmasetup(rxdma, (uint32_t)priv->rxfifo, RXDMA_BUFFER_SIZE,
                    SERIAL_DMA_CONTROL_WORD);
 
-  /* Reset our DMA shadow pointer to match the address just programmed above. */
+  /* Reset our DMA shadow pointer to match the address just programmed
+   * above.
+   */
 
   priv->rxdmanext = 0;
 
@@ -1045,14 +1052,15 @@ static void up_dma_shutdown(struct uart_dev_s *dev)
  * Name: up_attach
  *
  * Description:
- *   Configure the UART to operation in interrupt driven mode.  This method is
- *   called when the serial port is opened.  Normally, this is just after the
- *   the setup() method is called, however, the serial console may operate in
- *   a non-interrupt driven mode during the boot phase.
+ *   Configure the UART to operation in interrupt driven mode.  This method
+ *   is called when the serial port is opened.  Normally, this is just after
+ *   the the setup() method is called, however, the serial console may
+ *   operate in a non-interrupt driven mode during the boot phase.
  *
- *   RX and TX interrupts are not enabled when by the attach method (unless the
- *   hardware supports multiple levels of interrupt enabling).  The RX and TX
- *   interrupts are not enabled until the txint() and rxint() methods are called.
+ *   RX and TX interrupts are not enabled when by the attach method (unless
+ *   the hardware supports multiple levels of interrupt enabling).  The RX
+ *   and TX interrupts are not enabled until the txint() and rxint() methods
+ *   are called.
  *
  ****************************************************************************/
 
@@ -1089,8 +1097,8 @@ static int up_attach(struct uart_dev_s *dev)
  *
  * Description:
  *   Detach UART interrupts.  This method is called when the serial port is
- *   closed normally just before the shutdown method is called.  The exception
- *   is the serial console which is never shutdown.
+ *   closed normally just before the shutdown method is called.  The
+ *   exception is the serial console which is never shutdown.
  *
  ****************************************************************************/
 
@@ -1305,7 +1313,7 @@ static int up_ioctl(struct file *filep, int cmd, unsigned long arg)
       {
         if ((arg & SER_SINGLEWIRE_PULLUP) != 0)
           {
-            ret = -EINVAL; // Not supported
+            ret = -EINVAL; /* Not supported */
             break;
           }
 
@@ -1341,11 +1349,9 @@ static int up_ioctl(struct file *filep, int cmd, unsigned long arg)
             break;
           }
 
-        cfsetispeed(termiosp, priv->baud);
-
-        /* Note: CSIZE only supports 5-8 bits. The driver only support 8/9 bit
-         * modes and therefore is no way to report 9-bit mode, we always claim
-         * 8 bit mode.
+        /* Note: CSIZE only supports 5-8 bits. The driver only support
+         * 8/9 bit modes and therefore is no way to report 9-bit mode, we
+         * always claim 8 bit mode.
          */
 
         termiosp->c_cflag =
@@ -1360,6 +1366,8 @@ static int up_ioctl(struct file *filep, int cmd, unsigned long arg)
 #  endif
           CS8;
 
+        cfsetispeed(termiosp, priv->baud);
+
         /* TODO: CCTS_IFLOW, CCTS_OFLOW */
       }
       break;
@@ -1666,8 +1674,8 @@ static void up_rxint(struct uart_dev_s *dev, bool enable)
   flags = enter_critical_section();
   if (enable)
     {
-      /* Receive an interrupt when their is anything in the Rx data register (or an Rx
-       * timeout occurs).
+      /* Receive an interrupt when their is anything in the Rx data register
+       * (or an RX timeout occurs).
        */
 
 #ifndef CONFIG_SUPPRESS_SERIAL_INTS
@@ -1935,7 +1943,8 @@ static bool up_txempty(struct uart_dev_s *dev)
 
   /* Return true if the transmit buffer/fifo is "empty." */
 
-  return (up_serialin(priv, KINETIS_UART_SFIFO_OFFSET) & UART_SFIFO_TXEMPT) != 0;
+  return (up_serialin(priv, KINETIS_UART_SFIFO_OFFSET) & \
+          UART_SFIFO_TXEMPT) != 0;
 }
 #endif
 
@@ -2042,26 +2051,26 @@ unsigned int kinetis_uart_serialinit(unsigned int first)
 
   /* Register all UARTs */
 
-  devname[(sizeof(devname)/sizeof(devname[0]))-2] = '0' + first++;
+  devname[(sizeof(devname) / sizeof(devname[0]))-2] = '0' + first++;
   uart_register(devname, &TTYS0_DEV);
 #ifdef TTYS1_DEV
-  devname[(sizeof(devname)/sizeof(devname[0]))-2] = '0' + first++;
+  devname[(sizeof(devname) / sizeof(devname[0]))-2] = '0' + first++;
   uart_register(devname, &TTYS1_DEV);
 #endif
 #ifdef TTYS2_DEV
-  devname[(sizeof(devname)/sizeof(devname[0]))-2] = '0' + first++;
+  devname[(sizeof(devname) / sizeof(devname[0]))-2] = '0' + first++;
   uart_register(devname, &TTYS2_DEV);
 #endif
 #ifdef TTYS3_DEV
-  devname[(sizeof(devname)/sizeof(devname[0]))-2] = '0' + first++;
+  devname[(sizeof(devname) / sizeof(devname[0]))-2] = '0' + first++;
   uart_register(devname, &TTYS3_DEV);
 #endif
 #ifdef TTYS4_DEV
-  devname[(sizeof(devname)/sizeof(devname[0]))-2] = '0' + first++;
+  devname[(sizeof(devname) / sizeof(devname[0]))-2] = '0' + first++;
   uart_register(devname, &TTYS4_DEV);
 #endif
 #ifdef TTYS5_DEV
-  devname[(sizeof(devname)/sizeof(devname[0]))-2] = '0' + first++;
+  devname[(sizeof(devname) / sizeof(devname[0]))-2] = '0' + first++;
   uart_register(devname, &TTYS5_DEV);
 #endif
   return first;

arch/arm/src/lc823450/chip.h

@@ -55,18 +55,6 @@
  * Public Types
  ****************************************************************************/
 
-/****************************************************************************
- * Public Data
- ****************************************************************************/
-
-#ifdef __ASSEMBLY__
-
-#if defined(CONFIG_SMP) && CONFIG_ARCH_INTERRUPTSTACK > 7
-  .globl  g_instack_alloc
-#endif /* CONFIG_SMP && CONFIG_ARCH_INTERRUPTSTACK > 7 */
-
-#endif /* __ASSEMBLY__ */
-
 /****************************************************************************
  * Macro Definitions
  ****************************************************************************/
@@ -84,77 +72,12 @@
 
 #if defined(CONFIG_SMP) && CONFIG_ARCH_INTERRUPTSTACK > 7
   .macro  setintstack, tmp1, tmp2
-#if CONFIG_SMP_NCPUS > 1
-  ldr	 \tmp1, =CORE_COREID
-  ldr  \tmp1, [\tmp1, 0]     /* \tmp = getreg32(coreid_reg) */
-  and  \tmp1, \tmp1, 1       /* \tmp = COREID */
-  cmp  \tmp1, #0
-  bne  1f
-  ldr  \tmp1, =g_cpu0_instack_base
-  ldr  sp, [\tmp1, 0]        /* sp = getreg32(g_cpu0_instack_base) */
-  b    2f
-1:
-  ldr  \tmp1, =g_cpu1_instack_base
-  ldr  sp, [\tmp1, 0]        /* sp = getreg32(g_cpu1_instack_base) */
-2:
-#else
-  ldr  \tmp1, =g_cpu0_instack_base
-  ldr  sp, [\tmp1, 0]        /* sp = getreg32(g_cpu0_instack_base) */
-#endif
+  ldr \tmp1, =CORE_COREID
+  ldr \tmp1, [\tmp1, 0]          /* tmp1 = getreg32(CORE_COREID)  */
+  ldr \tmp2, =g_cpu_intstack_top
+  ldr sp, [\tmp2, \tmp1, lsl #2] /* sp = g_cpu_intstack_top[tmp1] */
   .endm
 #endif /* CONFIG_SMP && CONFIG_ARCH_INTERRUPTSTACK > 7 */
 
 #endif /* __ASSEMBLY__  */
-
-/****************************************************************************
- * Inline Functions
- ****************************************************************************/
-
-#ifndef __ASSEMBLY__
-
-#ifdef __cplusplus
-#define EXTERN extern "C"
-extern "C"
-{
-#else
-#define EXTERN extern
-#endif
-
-/****************************************************************************
- * Name: arm_intstack_base
- *
- * Description:
- *   Set the current stack pointer to the "base" the correct interrupt stack
- *   allocation for the current CPU.
- *
- ****************************************************************************/
-
-#if defined(CONFIG_SMP) && CONFIG_ARCH_INTERRUPTSTACK > 7
-static inline uintptr_t arm_intstack_base(void)
-{
-  uintptr_t base = (uintptr_t)g_instack_alloc;
-#if CONFIG_SMP_NCPUS > 1
-  uint32_t coreid = getreg32(CORE_COREID);
-
-  if ((coreid & CORE_COREID_ID) != 0)
-    {
-      base += INTSTACK_SIZE;
-    }
-#endif
-
-  return base;
-}
-#endif
-
-/****************************************************************************
- * Public Function Prototypes
- ****************************************************************************/
-
-#if defined(__cplusplus)
-}
-#endif
-#undef EXTERN
-
-#endif /* !__ASSEMBLY__ */
-
 #endif /* _ARCH_ARM_SRC_LC823450_CHIP_H */

arch/arm/src/lc823450/lc823450_irq.c

@@ -89,17 +89,17 @@ volatile uint32_t *g_current_regs[1];
  * These definitions provide the aligned stack allocations.
  */
 
-uint64_t g_instack_alloc[INTSTACK_ALLOC >> 3];
+uint64_t g_intstack_alloc[INTSTACK_ALLOC >> 3];
 
 /* These definitions provide the "top" of the push-down stacks. */
 
-const uint32_t g_cpu0_instack_base =
-  (uint32_t)g_instack_alloc + INTSTACK_SIZE;
-
+const uint32_t g_cpu_intstack_top[CONFIG_SMP_NCPUS] =
+{
+  (uint32_t)g_intstack_alloc + INTSTACK_SIZE,
 #if CONFIG_SMP_NCPUS > 1
-const uint32_t g_cpu1_instack_base =
-  (uint32_t)g_instack_alloc + 2 * INTSTACK_SIZE;
-#endif
+  (uint32_t)g_intstack_alloc + (2 * INTSTACK_SIZE),
+#endif /* CONFIG_SMP_NCPUS > 1 */
+};
 #endif
 
 /****************************************************************************
@@ -470,16 +470,6 @@ void up_irqinitialize(void)
   putreg32(0xffffffff, NVIC_IRQ0_31_CLEAR);
   putreg32(0xffffffff, NVIC_IRQ32_63_CLEAR);
 
-  /* Colorize the interrupt stack for debug purposes */
-
-#if defined(CONFIG_STACK_COLORATION) && CONFIG_ARCH_INTERRUPTSTACK > 3
-    {
-      size_t intstack_size = (CONFIG_ARCH_INTERRUPTSTACK & ~3);
-      arm_stack_color((FAR void *)((uintptr_t)&g_intstackbase -
-                      intstack_size), intstack_size);
-    }
-#endif
-
   /* The standard location for the vector table is at the beginning of FLASH
    * at address 0x0800:0000.  If we are using the STMicro DFU bootloader,
    * then the vector table will be offset to a different location in FLASH
@@ -869,3 +859,35 @@ int lc823450_irq_register(int irq, struct lc823450_irq_ops *ops)
   return OK;
 }
 #endif /* CONFIG_LC823450_VIRQ */
+
+/****************************************************************************
+ * Name: arm_intstack_base
+ *
+ * Description:
+ *   Return a pointer to the "base" the correct interrupt stack allocation
+ *   for the current CPU. NOTE: Here, the base means "top" of the stack
+ *
+ ****************************************************************************/
+
+#if defined(CONFIG_SMP) && CONFIG_ARCH_INTERRUPTSTACK > 7
+uintptr_t arm_intstack_base(void)
+{
+  return g_cpu_intstack_top[up_cpu_index()];
+}
+#endif
+
+/****************************************************************************
+ * Name: arm_intstack_alloc
+ *
+ * Description:
+ *   Return a pointer to the "alloc" the correct interrupt stack allocation
+ *   for the current CPU.
+ *
+ ****************************************************************************/
+
+#if defined(CONFIG_SMP) && CONFIG_ARCH_INTERRUPTSTACK > 7
+uintptr_t arm_intstack_alloc(void)
+{
+  return g_cpu_intstack_top[up_cpu_index()] - INTSTACK_SIZE;
+}
+#endif

arch/arm/src/lc823450/lc823450_irq.h

@@ -67,26 +67,15 @@ extern "C"
 #define EXTERN extern
 #endif
 
-#if defined(CONFIG_SMP) && CONFIG_ARCH_INTERRUPTSTACK > 7
-/* In the SMP configuration, we will need two custom interrupt stacks.
- * These definitions provide the aligned stack allocations.
- */
-
-EXTERN uint64_t g_instack_alloc[];
-
-/* These definitions provide the "top" of the push-down stacks. */
-
-EXTERN const uint32_t g_cpu0_instack_base;
-#if CONFIG_SMP_NCPUS > 1
-EXTERN const uint32_t g_cpu1_instack_base;
-#endif
-
-#endif /* CONFIG_SMP && CONFIG_ARCH_INTERRUPTSTACK > 7 */
-
 /****************************************************************************
  * Public Function Prototypes
  ****************************************************************************/
 
+#if defined(CONFIG_SMP) && CONFIG_ARCH_INTERRUPTSTACK > 7
+EXTERN uintptr_t arm_intstack_base(void);
+EXTERN uintptr_t arm_intstack_alloc(void);
+#endif
+
 #undef EXTERN
 #if defined(__cplusplus)
 }

arch/arm/src/lc823450/lc823450_serial.c

@@ -757,8 +757,6 @@ static int up_ioctl(struct file *filep, int cmd, unsigned long arg)
               break;
             }
 
-          cfsetispeed(termiosp, priv->baud);
-
           /* Note that since we only support 8/9 bit modes and
            * there is no way to report 9-bit mode, we always claim 8.
            */
@@ -773,6 +771,8 @@ static int up_ioctl(struct file *filep, int cmd, unsigned long arg)
                               ((priv->iflow) ? CRTS_IFLOW : 0) |
 #endif
                               CS8;
+
+          cfsetispeed(termiosp, priv->baud);
         }
         break;
 

arch/arm/src/lpc17xx_40xx/lpc17_40_serial.c

@@ -479,9 +479,10 @@ static uart_dev_t g_uart3port =
 #  endif
 #endif /* HAVE_CONSOLE */
 
-/************************************************************************************
+/****************************************************************************
+
  * Inline Functions
- ************************************************************************************/
+ ****************************************************************************/
 
 /****************************************************************************
  * Name: up_serialin
@@ -496,7 +497,8 @@ static inline uint32_t up_serialin(struct up_dev_s *priv, int offset)
  * Name: up_serialout
  ****************************************************************************/
 
-static inline void up_serialout(struct up_dev_s *priv, int offset, uint32_t value)
+static inline void up_serialout(struct up_dev_s *priv, int offset,
+                                uint32_t value)
 {
   putreg32(value, priv->uartbase + offset);
 }
@@ -671,7 +673,8 @@ void up_setbaud(uintptr_t uartbase, uint32_t basefreq, uint32_t baud)
 
   /* Then save the fractional divider values */
 
-  putreg32((mul << UART_FDR_MULVAL_SHIFT) | (divadd << UART_FDR_DIVADDVAL_SHIFT),
+  putreg32((mul << UART_FDR_MULVAL_SHIFT) | \
+           (divadd << UART_FDR_DIVADDVAL_SHIFT),
            uartbase + LPC17_40_UART_FDR_OFFSET);
 }
 #  ifdef LPC176x
@@ -685,13 +688,14 @@ static inline uint32_t lpc17_40_uartcclkdiv(uint32_t baud)
 }
 #  endif
 #else
-/************************************************************************************
+
+/****************************************************************************
  * Name: lpc17_40_uartcclkdiv
  *
  * Description:
- *   Select a CCLK divider to produce the UART PCLK.  The strategy is to select the
- *   smallest divisor that results in an solution within range of the 16-bit
- *   DLM and DLL divisor:
+ *   Select a CCLK divider to produce the UART PCLK.  The strategy is to
+ *   select the smallest divisor that results in an solution within range of
+ *   the 16-bit DLM and DLL divisor:
  *
  *     PCLK = CCLK / divisor
  *     BAUD = PCLK / (16 * DL)
@@ -702,14 +706,15 @@ static inline uint32_t lpc17_40_uartcclkdiv(uint32_t baud)
  *
  *     PCLK = CCLK / divisor
  *
- *   For the LPC178x/40xx, the PCLK is determined by the global divisor setting in
- *   the PLKSEL register (and, in that case, this function is not needed).
+ *   For the LPC178x/40xx, the PCLK is determined by the global divisor
+ *   setting in the PLKSEL register (and, in that case, this function is not
+ *   needed).
  *
- *   NOTE:  This is an inline function.  If a typical optimization level is used and
- *   a constant is provided for the desired frequency, then most of the following
- *   logic will be optimized away.
+ *   NOTE:  This is an inline function.  If a typical optimization level is
+ *   used and a constant is provided for the desired frequency, then most of
+ *   the following logic will be optimized away.
  *
- ************************************************************************************/
+ ****************************************************************************/
 
 #  ifdef LPC176x
 static inline uint32_t lpc17_40_uartcclkdiv(uint32_t baud)
@@ -719,13 +724,14 @@ static inline uint32_t lpc17_40_uartcclkdiv(uint32_t baud)
    *   BAUD = PCLK / (16 * DL), or
    *   DL   = PCLK / BAUD / 16
    *
-   * Where for the LPC176x the PCLK is determined by the UART-specific divisor in
-   * PCLKSEL0 or PCLKSEL1:
+   * Where for the LPC176x the PCLK is determined by the UART-specific
+   * divisor in PCLKSEL0 or PCLKSEL1:
    *
    *   PCLK = CCLK / divisor
    *
-   * And for the LPC178x/40xx, the PCLK is determined by the global divisor setting in
-   * the PLKSEL register (and, in that case, this function is not needed).
+   * And for the LPC178x/40xx, the PCLK is determined by the global divisor
+   * setting in the PLKSEL register (and, in that case, this function is not
+   * needed).
    */
 
   /* Calculate and optimal PCLKSEL0/1 divisor.
@@ -799,23 +805,25 @@ static inline uint32_t lpc17_40_uartcclkdiv(uint32_t baud)
 }
 #  endif /* LPC176x */
 #endif /* CONFIG_LPC17_40_UART_USE_FRACTIONAL_DIVIDER */
-/************************************************************************************
+
+/****************************************************************************
  * Name: lpc17_40_uart0config, uart1config, uart2config, and uart3config
  *
  * Description:
- *   Configure the UART.  UART0/1/2/3 peripherals are configured using the following
- *   registers:
+ *   Configure the UART.  UART0/1/2/3 peripherals are configured using the
+ *   following registers:
  *
  *   1. Power: In the PCONP register, set bits PCUART0/1/2/3.
  *      On reset, UART0 and UART 1 are enabled (PCUART0 = 1 and PCUART1 = 1)
  *      and UART2/3 are disabled (PCUART1 = 0 and PCUART3 = 0).
  *   2. Peripheral clock: In the PCLKSEL0 register, select PCLK_UART0 and
- *      PCLK_UART1; in the PCLKSEL1 register, select PCLK_UART2 and PCLK_UART3.
+ *      PCLK_UART1; in the PCLKSEL1 register, select PCLK_UART2 and
+ *      PCLK_UART3.
  *   3. Pins: Select UART pins through the PINSEL registers and pin modes
  *      through the PINMODE registers. UART receive pins should not have
  *      pull-down resistors enabled.
  *
- ************************************************************************************/
+ ****************************************************************************/
 
 #ifdef CONFIG_LPC17_40_UART0
 static inline void lpc17_40_uart0config(void)
@@ -966,7 +974,7 @@ static inline void lpc17_40_uart3config(void)
 };
 #endif
 
-/************************************************************************************
+/****************************************************************************
  * Name: lpc17_40_uartdl
  *
  * Description:
@@ -975,7 +983,7 @@ static inline void lpc17_40_uart3config(void)
  *     BAUD = PCLK / (16 * DL), or
  *     DL   = PCLK / BAUD / 16
  *
- ************************************************************************************/
+ ****************************************************************************/
 
 #ifndef CONFIG_LPC17_40_UART_USE_FRACTIONAL_DIVIDER
 #  ifdef LPC176x
@@ -1082,7 +1090,8 @@ static int up_setup(struct uart_dev_s *dev)
    */
 
   up_serialout(priv, LPC17_40_UART_FDR_OFFSET,
-              (1 << UART_FDR_MULVAL_SHIFT) + (0 << UART_FDR_DIVADDVAL_SHIFT));
+               (1 << UART_FDR_MULVAL_SHIFT) + \
+               (0 << UART_FDR_DIVADDVAL_SHIFT));
 #endif
 
   /* Enter DLAB=1 */
@@ -1119,7 +1128,8 @@ static int up_setup(struct uart_dev_s *dev)
   if (priv->uartbase == LPC17_40_UART1_BASE)
     {
 #if defined(CONFIG_UART1_IFLOWCONTROL) && defined(CONFIG_UART1_OFLOWCONTROL)
-      up_serialout(priv, LPC17_40_UART_MCR_OFFSET, (UART_MCR_RTSEN | UART_MCR_CTSEN));
+      up_serialout(priv, LPC17_40_UART_MCR_OFFSET,
+                   (UART_MCR_RTSEN | UART_MCR_CTSEN));
 #elif defined(CONFIG_UART1_IFLOWCONTROL)
       up_serialout(priv, LPC17_40_UART_MCR_OFFSET, UART_MCR_RTSEN);
 #else
@@ -1150,14 +1160,15 @@ static void up_shutdown(struct uart_dev_s *dev)
  * Name: up_attach
  *
  * Description:
- *   Configure the UART to operation in interrupt driven mode.  This method is
- *   called when the serial port is opened.  Normally, this is just after the
+ *   Configure the UART to operation in interrupt driven mode.  This method
+ *   is called when the serial port is opened.  Normally, this is just after
  *   the setup() method is called, however, the serial console may operate in
  *   a non-interrupt driven mode during the boot phase.
  *
- *   RX and TX interrupts are not enabled when by the attach method (unless the
- *   hardware supports multiple levels of interrupt enabling).  The RX and TX
- *   interrupts are not enabled until the txint() and rxint() methods are called.
+ *   RX and TX interrupts are not enabled when by the attach method (unless
+ *   the hardware supports multiple levels of interrupt enabling).  The RX
+ *   and TX interrupts are not enabled until the txint() and rxint() methods
+ *   are called.
  *
  ****************************************************************************/
 
@@ -1186,8 +1197,8 @@ static int up_attach(struct uart_dev_s *dev)
  *
  * Description:
  *   Detach UART interrupts.  This method is called when the serial port is
- *   closed normally just before the shutdown method is called.  The exception is
- *   the serial console which is never shutdown.
+ *   closed normally just before the shutdown method is called.  The
+ *   exception is the serial console which is never shutdown.
  *
  ****************************************************************************/
 
@@ -1391,8 +1402,6 @@ static int up_ioctl(struct file *filep, int cmd, unsigned long arg)
          * that only one speed is supported.
          */
 
-        /* Get the c_speed field in the termios struct */
-
         priv->baud = cfgetispeed(termiosp);
 
         /* TODO: Re-calculate the optimal CCLK divisor for the new baud and
@@ -1400,14 +1409,16 @@ static int up_ioctl(struct file *filep, int cmd, unsigned long arg)
          */
 
 #  ifdef CONFIG_LPC17_40_UART_USE_FRACTIONAL_DIVIDER
-        up_setbaud(priv->uartbase, LPC17_40_CCLK / priv->cclkdiv, priv->baud);
+        up_setbaud(priv->uartbase, LPC17_40_CCLK / \
+                   priv->cclkdiv, priv->baud);
 #  else
 #    if 0 /* ifdef LPC176x */
         priv->cclkdiv = lpc17_40_uartcclkdiv(priv->baud);
 #    endif
-        /* DLAB open latch */
-
-        /* REVISIT:  Shouldn't we just call up_setup() to do all of the following? */
+        /* DLAB open latch
+         * REVISIT: Shouldn't we just call up_setup() to do all of the
+         *          following?
+         */
 
         lcr = getreg32(priv->uartbase + LPC17_40_UART_LCR_OFFSET);
         up_serialout(priv, LPC17_40_UART_LCR_OFFSET, (lcr | UART_LCR_DLAB));
@@ -1558,7 +1569,8 @@ static void up_txint(struct uart_dev_s *dev, bool enable)
 static bool up_txready(struct uart_dev_s *dev)
 {
   struct up_dev_s *priv = (struct up_dev_s *)dev->priv;
-  return ((up_serialin(priv, LPC17_40_UART_LSR_OFFSET) & UART_LSR_THRE) != 0);
+  return ((up_serialin(priv, LPC17_40_UART_LSR_OFFSET) & \
+          UART_LSR_THRE) != 0);
 }
 
 /****************************************************************************
@@ -1572,7 +1584,8 @@ static bool up_txready(struct uart_dev_s *dev)
 static bool up_txempty(struct uart_dev_s *dev)
 {
   struct up_dev_s *priv = (struct up_dev_s *)dev->priv;
-  return ((up_serialin(priv, LPC17_40_UART_LSR_OFFSET) & UART_LSR_THRE) != 0);
+  return ((up_serialin(priv, LPC17_40_UART_LSR_OFFSET) & \
+          UART_LSR_THRE) != 0);
 }
 
 /****************************************************************************

arch/arm/src/nrf52/nrf52_serial.c

@@ -475,12 +475,6 @@ static int nrf52_ioctl(struct file *filep, int cmd, unsigned long arg)
               break;
             }
 
-          /* Get baud */
-
-          cfsetispeed(termiosp, config->baud);
-
-          /* Get flags */
-
           termiosp->c_cflag = ((config->parity != 0) ? PARENB : 0)
                               | ((config->parity == 1) ? PARODD : 0)
                               | ((config->stopbits2) ? CSTOPB : 0) |
@@ -492,6 +486,8 @@ static int nrf52_ioctl(struct file *filep, int cmd, unsigned long arg)
 #endif
                               CS8;
 
+          cfsetispeed(termiosp, config->baud);
+
           break;
         }
 

arch/arm/src/nuc1xx/nuc_serial.c

@@ -160,7 +160,7 @@ static struct nuc_dev_s g_uart0priv =
   .irq            = NUC_IRQ_UART0,
   .parity         = CONFIG_UART0_PARITY,
   .bits           = CONFIG_UART0_BITS,
-  .depth          = (UART0_FIFO_DEPTH-1),
+  .depth          = (UART0_FIFO_DEPTH - 1),
   .stopbits2      = CONFIG_UART0_2STOP,
 };
 
@@ -191,24 +191,24 @@ static struct nuc_dev_s g_uart1priv =
   .irq            = NUC_IRQ_UART1,
   .parity         = CONFIG_UART1_PARITY,
   .bits           = CONFIG_UART1_BITS,
-  .depth          = (UART1_FIFO_DEPTH-1),
+  .depth          = (UART1_FIFO_DEPTH - 1),
   .stopbits2      = CONFIG_UART1_2STOP,
 };
 
 static uart_dev_t g_uart1port =
 {
-  .recv     =
-  {
-    .size   = CONFIG_UART1_RXBUFSIZE,
-    .buffer = g_uart1rxbuffer,
-  },
-  .xmit     =
-  {
-    .size   = CONFIG_UART1_TXBUFSIZE,
-    .buffer = g_uart1txbuffer,
-  },
-  .ops      = &g_uart_ops,
-  .priv     = &g_uart1priv,
+  .recv       =
+    {
+      .size   = CONFIG_UART1_RXBUFSIZE,
+      .buffer = g_uart1rxbuffer,
+    },
+  .xmit       =
+    {
+      .size   = CONFIG_UART1_TXBUFSIZE,
+      .buffer = g_uart1txbuffer,
+    },
+  .ops        = &g_uart_ops,
+  .priv       = &g_uart1priv,
 };
 #endif /* CONFIG_NUC_UART1 */
 
@@ -222,24 +222,24 @@ static struct nuc_dev_s g_uart2priv =
   .irq            = NUC_IRQ_UART2,
   .parity         = CONFIG_UART2_PARITY,
   .bits           = CONFIG_UART2_BITS,
-  .depth          = (UART2_FIFO_DEPTH-1),
+  .depth          = (UART2_FIFO_DEPTH - 1),
   .stopbits2      = CONFIG_UART2_2STOP,
 };
 
 static uart_dev_t g_uart2port =
 {
-  .recv     =
-  {
-    .size   = CONFIG_UART2_RXBUFSIZE,
-    .buffer = g_uart2rxbuffer,
-  },
-  .xmit     =
-  {
-    .size   = CONFIG_UART2_TXBUFSIZE,
-    .buffer = g_uart2txbuffer,
-  },
-  .ops      = &g_uart_ops,
-  .priv     = &g_uart2priv,
+  .recv       =
+    {
+      .size   = CONFIG_UART2_RXBUFSIZE,
+      .buffer = g_uart2rxbuffer,
+    },
+  .xmit       =
+    {
+      .size   = CONFIG_UART2_TXBUFSIZE,
+      .buffer = g_uart2txbuffer,
+    },
+  .ops        = &g_uart_ops,
+  .priv       = &g_uart2priv,
 };
 #endif /* CONFIG_NUC_UART2 */
 
@@ -276,7 +276,9 @@ static uart_dev_t g_uart2port =
 #  endif
 #endif
 
-/* Pick ttys1.  This could be any two of UART0-2 excluding the console UART. */
+/* Pick ttys1.  This could be any two of UART0-2 excluding the console
+ * UART.
+ */
 
 #if defined(CONFIG_NUC_UART0) && !defined(UART0_ASSIGNED)
 #  define TTYS1_DEV           g_uart0port /* UART0 is ttyS1 */
@@ -319,7 +321,8 @@ static inline uint32_t up_serialin(struct nuc_dev_s *priv, int offset)
  * Name: up_serialout
  ****************************************************************************/
 
-static inline void up_serialout(struct nuc_dev_s *priv, int offset, uint32_t value)
+static inline void up_serialout(struct nuc_dev_s *priv, int offset,
+                                uint32_t value)
 {
   putreg32(value, priv->uartbase + offset);
 }
@@ -525,6 +528,7 @@ static int up_setup(struct uart_dev_s *dev)
   priv->ier = up_serialin(priv, NUC_UART_IER_OFFSET);
 
   /* Enable Flow Control in the Modem Control Register */
+
   /* Not implemented */
 
 #endif /* CONFIG_SUPPRESS_UART_CONFIG */
@@ -549,14 +553,15 @@ static void up_shutdown(struct uart_dev_s *dev)
  * Name: up_attach
  *
  * Description:
- *   Configure the UART to operation in interrupt driven mode.  This method is
- *   called when the serial port is opened.  Normally, this is just after the
- *   the setup() method is called, however, the serial console may operate in
- *   a non-interrupt driven mode during the boot phase.
+ *   Configure the UART to operation in interrupt driven mode.  This method
+ *   is called when the serial port is opened.  Normally, this is just after
+ *   the setup() method is called, however, the serial console may operate
+ *   in a non-interrupt driven mode during the boot phase.
  *
- *   RX and TX interrupts are not enabled when by the attach method (unless the
- *   hardware supports multiple levels of interrupt enabling).  The RX and TX
- *   interrupts are not enabled until the txint() and rxint() methods are called.
+ *   RX and TX interrupts are not enabled when by the attach method (unless
+ *   the hardware supports multiple levels of interrupt enabling).  The RX
+ *   and TX interrupts are not enabled until the txint() and rxint() methods
+ *   are called.
  *
  ****************************************************************************/
 
@@ -585,8 +590,8 @@ static int up_attach(struct uart_dev_s *dev)
  *
  * Description:
  *   Detach UART interrupts.  This method is called when the serial port is
- *   closed normally just before the shutdown method is called.  The exception is
- *   the serial console which is never shutdown.
+ *   closed normally just before the shutdown method is called.  The
+ *   exception is the serial console which is never shutdown.
  *
  ****************************************************************************/
 
@@ -632,11 +637,12 @@ static int up_interrupt(int irq, void *context,  void *arg)
 
        isr = up_serialin(priv, NUC_UART_ISR_OFFSET);
 
-      /* Check if the RX FIFO is empty.  Check if an RX timeout occur.  These affect
-       * some later decisions.
+      /* Check if the RX FIFO is empty.  Check if an RX timeout occur.
+       * These affect some later decisions.
        */
 
-      rxfe = ((up_serialin(priv, NUC_UART_FSR_OFFSET) & UART_FSR_RX_EMPTY) != 0);
+      rxfe = ((up_serialin(priv, NUC_UART_FSR_OFFSET) & \
+              UART_FSR_RX_EMPTY) != 0);
       rxto = ((isr & UART_ISR_TOUT_INT) != 0);
 
       /* Check if the RX FIFO is filled to the threshold value OR if the RX
@@ -676,7 +682,8 @@ static int up_interrupt(int irq, void *context,  void *arg)
        * data in the RX FIFO when we entered the interrupt handler?
        */
 
-      else if ((priv->ier & (UART_IER_RTO_IEN | UART_IER_RDA_IEN)) == UART_IER_RDA_IEN && !rxfe)
+      else if ((priv->ier & (UART_IER_RTO_IEN | UART_IER_RDA_IEN)) == \
+               UART_IER_RDA_IEN && !rxfe)
         {
           /* We are receiving data and the RX timeout is not enabled.
            * Set the RX FIFO threshold so that RX interrupts will only be
@@ -700,7 +707,9 @@ static int up_interrupt(int irq, void *context,  void *arg)
 
       if ((isr & UART_ISR_MODEM_INT) != 0)
         {
-          /* Cleared by setting the DCTSF bit in the modem control register (MCR) */
+          /* Cleared by setting the DCTSF bit in the modem control register
+           * (MCR)
+           */
 
          regval = up_serialin(priv, NUC_UART_MCR_OFFSET);
          up_serialout(priv, NUC_UART_MCR_OFFSET, regval | UART_MSR_DCTSF);
@@ -797,8 +806,6 @@ static int up_ioctl(struct file *filep, int cmd, unsigned long arg)
          * that only one speed is supported.
          */
 
-        /* Get the c_speed field in the termios struct */
-
         priv->baud = cfgetispeed(termiosp);
 
         /* Reset the baud */

arch/arm/src/s32k1xx/s32k1xx_serial.c

@@ -154,29 +154,29 @@
 
 struct s32k1xx_uart_s
 {
-  uint32_t uartbase;    /* Base address of UART registers */
-  uint32_t baud;        /* Configured baud */
-  uint32_t ie;          /* Saved enabled interrupts */
-  uint8_t  irq;         /* IRQ associated with this UART */
-  uint8_t  parity;      /* 0=none, 1=odd, 2=even */
-  uint8_t  bits;        /* Number of bits (7 or 8) */
+  uint32_t uartbase;        /* Base address of UART registers */
+  uint32_t baud;            /* Configured baud */
+  uint32_t ie;              /* Saved enabled interrupts */
+  uint8_t  irq;             /* IRQ associated with this UART */
+  uint8_t  parity;          /* 0=none, 1=odd, 2=even */
+  uint8_t  bits;            /* Number of bits (7 or 8) */
 #if defined(CONFIG_SERIAL_RS485CONTROL) || defined(CONFIG_SERIAL_IFLOWCONTROL)
-  uint8_t  inviflow:1;  /* Invert RTS sense */
+  uint8_t  inviflow:1;      /* Invert RTS sense */
   const uint32_t rts_gpio;  /* U[S]ART RTS GPIO pin configuration */
 #endif
 #ifdef CONFIG_SERIAL_OFLOWCONTROL
   const uint32_t cts_gpio;  /* U[S]ART CTS GPIO pin configuration */
 #endif
 
-  uint8_t  stopbits2:1; /* 1: Configure with 2 stop bits vs 1 */
+  uint8_t  stopbits2:1;     /* 1: Configure with 2 stop bits vs 1 */
 #ifdef CONFIG_SERIAL_IFLOWCONTROL
-  uint8_t  iflow:1;     /* input flow control (RTS) enabled */
+  uint8_t  iflow:1;         /* input flow control (RTS) enabled */
 #endif
 #ifdef CONFIG_SERIAL_OFLOWCONTROL
-  uint8_t  oflow:1;     /* output flow control (CTS) enabled */
+  uint8_t  oflow:1;         /* output flow control (CTS) enabled */
 #endif
 #ifdef CONFIG_SERIAL_RS485CONTROL
-  uint8_t rs485mode:1;  /* We are in RS485 (RTS on TX) mode */
+  uint8_t rs485mode:1;      /* We are in RS485 (RTS on TX) mode */
 #endif
 };
 
@@ -340,18 +340,18 @@ static struct s32k1xx_uart_s g_uart1priv =
 
 static struct uart_dev_s g_uart1port =
 {
-  .recv         =
-  {
-    .size       = CONFIG_LPUART1_RXBUFSIZE,
-    .buffer     = g_uart1rxbuffer,
-  },
-  .xmit         =
-  {
-    .size       = CONFIG_LPUART1_TXBUFSIZE,
-    .buffer     = g_uart1txbuffer,
-   },
-  .ops          = &g_uart_ops,
-  .priv         = &g_uart1priv,
+  .recv           =
+    {
+      .size       = CONFIG_LPUART1_RXBUFSIZE,
+      .buffer     = g_uart1rxbuffer,
+    },
+  .xmit           =
+    {
+      .size       = CONFIG_LPUART1_TXBUFSIZE,
+      .buffer     = g_uart1txbuffer,
+    },
+  .ops            = &g_uart_ops,
+  .priv           = &g_uart1priv,
 };
 #endif
 
@@ -387,18 +387,18 @@ static struct s32k1xx_uart_s g_uart2priv =
 
 static struct uart_dev_s g_uart2port =
 {
-  .recv         =
-  {
-    .size       = CONFIG_LPUART2_RXBUFSIZE,
-    .buffer     = g_uart2rxbuffer,
-  },
-  .xmit         =
-  {
-    .size       = CONFIG_LPUART2_TXBUFSIZE,
-    .buffer     = g_uart2txbuffer,
-  },
-  .ops          = &g_uart_ops,
-  .priv         = &g_uart2priv,
+  .recv           =
+    {
+      .size       = CONFIG_LPUART2_RXBUFSIZE,
+      .buffer     = g_uart2rxbuffer,
+    },
+  .xmit           =
+    {
+      .size       = CONFIG_LPUART2_TXBUFSIZE,
+      .buffer     = g_uart2txbuffer,
+    },
+  .ops            = &g_uart_ops,
+  .priv           = &g_uart2priv,
 };
 #endif
 
@@ -428,8 +428,8 @@ static inline uint32_t s32k1xx_serialin(struct s32k1xx_uart_s *priv,
  * Name: s32k1xx_serialout
  ****************************************************************************/
 
-static inline void s32k1xx_serialout(struct s32k1xx_uart_s *priv, uint32_t offset,
-                                   uint32_t value)
+static inline void s32k1xx_serialout(struct s32k1xx_uart_s *priv,
+                                     uint32_t offset, uint32_t value)
 {
   putreg32(value, priv->uartbase + offset);
 }
@@ -439,7 +439,7 @@ static inline void s32k1xx_serialout(struct s32k1xx_uart_s *priv, uint32_t offse
  ****************************************************************************/
 
 static inline void s32k1xx_disableuartint(struct s32k1xx_uart_s *priv,
-                                        uint32_t *ie)
+                                          uint32_t *ie)
 {
   irqstate_t flags;
   uint32_t regval;
@@ -496,9 +496,10 @@ static int s32k1xx_setup(struct uart_dev_s *dev)
   struct s32k1xx_uart_s *priv = (struct s32k1xx_uart_s *)dev->priv;
 #ifndef CONFIG_SUPPRESS_LPUART_CONFIG
   struct uart_config_s config =
-  {
-    0
-  };
+    {
+      0
+    };
+
   int ret;
 
   /* Configure the UART */
@@ -522,11 +523,13 @@ static int s32k1xx_setup(struct uart_dev_s *dev)
 
   ret = s32k1xx_lpuart_configure(priv->uartbase, &config);
 
-  priv->ie = s32k1xx_serialin(priv, S32K1XX_LPUART_CTRL_OFFSET) & LPUART_ALL_INTS;
+  priv->ie = s32k1xx_serialin(priv, S32K1XX_LPUART_CTRL_OFFSET) & \
+             LPUART_ALL_INTS;
   return ret;
 
 #else
-  priv->ie = s32k1xx_serialin(priv, S32K1XX_LPUART_CTRL_OFFSET) & LPUART_ALL_INTS;
+  priv->ie = s32k1xx_serialin(priv, S32K1XX_LPUART_CTRL_OFFSET) & \
+             LPUART_ALL_INTS;
   return OK;
 #endif
 }
@@ -651,12 +654,14 @@ static int s32k1xx_interrupt(int irq, void *context, FAR void *arg)
 
       if ((usr & LPUART_STAT_OR) != 0)
         {
-          s32k1xx_serialout(priv, S32K1XX_LPUART_STAT_OFFSET, LPUART_STAT_OR);
+          s32k1xx_serialout(priv, S32K1XX_LPUART_STAT_OFFSET,
+                            LPUART_STAT_OR);
         }
 
       if ((usr & LPUART_STAT_FE) != 0)
         {
-          s32k1xx_serialout(priv, S32K1XX_LPUART_STAT_OFFSET, LPUART_STAT_FE);
+          s32k1xx_serialout(priv, S32K1XX_LPUART_STAT_OFFSET,
+                            LPUART_STAT_FE);
         }
 
       /* Handle incoming, receive bytes */
@@ -727,10 +732,6 @@ static int s32k1xx_ioctl(struct file *filep, int cmd, unsigned long arg)
             break;
           }
 
-        /* Return baud */
-
-        cfsetispeed(termiosp, priv->baud);
-
         /* Return parity */
 
         termiosp->c_cflag = ((priv->parity != 0) ? PARENB : 0) |
@@ -748,6 +749,10 @@ static int s32k1xx_ioctl(struct file *filep, int cmd, unsigned long arg)
 #ifdef CONFIG_SERIAL_IFLOWCONTROL
         termiosp->c_cflag |= ((priv->iflow) ? CRTS_IFLOW : 0);
 #endif
+        /* Return baud */
+
+        cfsetispeed(termiosp, priv->baud);
+
         /* Return number of bits */
 
         switch (priv->bits)
@@ -894,7 +899,9 @@ static int s32k1xx_ioctl(struct file *filep, int cmd, unsigned long arg)
         stat   = s32k1xx_serialin(priv, S32K1XX_LPUART_STAT_OFFSET);
         regval = ctrl;
 
-        /* {R|T}XINV bit field can only be written when the receiver is disabled (RE=0). */
+        /* {R|T}XINV bit field can only be written when the receiver is
+        * disabled (RE=0).
+        */
 
         regval &= ~LPUART_CTRL_RE;
 
@@ -1125,32 +1132,29 @@ static void up_pm_notify(struct pm_callback_s *cb, int domain,
       case(PM_NORMAL):
         {
           /* Logic for PM_NORMAL goes here */
-
         }
         break;
 
       case(PM_IDLE):
         {
           /* Logic for PM_IDLE goes here */
-
         }
         break;
 
       case(PM_STANDBY):
         {
           /* Logic for PM_STANDBY goes here */
-
         }
         break;
 
       case(PM_SLEEP):
         {
           /* Logic for PM_SLEEP goes here */
-
         }
         break;
 
       default:
+
         /* Should not get here */
 
         break;

arch/arm/src/sam34/sam_serial.c

@@ -109,7 +109,9 @@
 #  define HAVE_USART
 #endif
 
-/* Hardware flow control requires using the PDC or DMAC channel for reception */
+/* Hardware flow control requires using the PDC or DMAC channel for
+ * reception
+ */
 
 #ifdef CONFIG_SERIAL_IFLOWCONTROL
 #  warning PDC or DMAC support is required for RTS hardware flow control
@@ -180,9 +182,13 @@
 
 #ifdef USE_SERIALDRIVER
 
-/* Which UART/USART with be tty0/console and which tty1? tty2? tty3? tty4? tty5? */
+/* Which UART/USART with be tty0/console and which tty1? tty2? tty3?
+ * tty4? tty5?
+ */
 
-/* First pick the console and ttys0.  This could be any of UART0-1, USART0-3 */
+/* First pick the console and ttys0.  This could be any of UART0-1,
+ * USART0-3
+ */
 
 #if defined(CONFIG_UART0_SERIAL_CONSOLE)
 #    define CONSOLE_DEV         g_uart0port  /* UART0 is console */
@@ -230,7 +236,9 @@
 #  endif
 #endif
 
-/* Pick ttys1.  This could be any of UART0-1, USART0-3 excluding the console UART. */
+/* Pick ttys1.  This could be any of UART0-1, USART0-3 excluding the
+ * console UART.
+ */
 
 #if defined(CONFIG_SAM34_UART0) && !defined(UART0_ASSIGNED)
 #  define TTYS1_DEV           g_uart0port  /* UART0 is ttyS1 */
@@ -573,18 +581,18 @@ static struct up_dev_s g_usart2priv =
 
 static uart_dev_t g_usart2port =
 {
-  .recv     =
-  {
-    .size   = CONFIG_USART2_RXBUFSIZE,
-    .buffer = g_usart2rxbuffer,
-  },
-  .xmit     =
-  {
-    .size   = CONFIG_USART2_TXBUFSIZE,
-    .buffer = g_usart2txbuffer,
-   },
-  .ops      = &g_uart_ops,
-  .priv     = &g_usart2priv,
+  .recv       =
+    {
+      .size   = CONFIG_USART2_RXBUFSIZE,
+      .buffer = g_usart2rxbuffer,
+    },
+  .xmit       =
+    {
+      .size   = CONFIG_USART2_TXBUFSIZE,
+      .buffer = g_usart2txbuffer,
+    },
+  .ops        = &g_uart_ops,
+  .priv       = &g_usart2priv,
 };
 #endif
 
@@ -606,18 +614,18 @@ static struct up_dev_s g_usart3priv =
 
 static uart_dev_t g_usart3port =
 {
-  .recv     =
-  {
-    .size   = CONFIG_USART3_RXBUFSIZE,
-    .buffer = g_usart3rxbuffer,
-  },
-  .xmit     =
-  {
-    .size   = CONFIG_USART3_TXBUFSIZE,
-    .buffer = g_usart3txbuffer,
-   },
-  .ops      = &g_uart_ops,
-  .priv     = &g_usart3priv,
+  .recv       =
+    {
+      .size   = CONFIG_USART3_RXBUFSIZE,
+      .buffer = g_usart3rxbuffer,
+    },
+  .xmit       =
+    {
+      .size   = CONFIG_USART3_TXBUFSIZE,
+      .buffer = g_usart3txbuffer,
+    },
+  .ops        = &g_uart_ops,
+  .priv       = &g_usart3priv,
 };
 #endif
 
@@ -638,7 +646,8 @@ static inline uint32_t up_serialin(struct up_dev_s *priv, int offset)
  * Name: up_serialout
  ****************************************************************************/
 
-static inline void up_serialout(struct up_dev_s *priv, int offset, uint32_t value)
+static inline void up_serialout(struct up_dev_s *priv, int offset,
+                                uint32_t value)
 {
   putreg32(value, priv->usartbase + offset);
 }
@@ -713,7 +722,8 @@ static int up_setup(struct uart_dev_s *dev)
   /* "Setting the USART to operate with hardware handshaking is performed by
    *  writing the USART_MODE field in the Mode Register (US_MR) to the value
    *  0x2. ... Using this mode requires using the PDC or DMAC channel for
-   *  reception. The transmitter can handle hardware handshaking in any case."
+   *  reception. The transmitter can handle hardware handshaking in any
+   *  case."
    */
 
   if (priv->flowc)
@@ -812,7 +822,7 @@ static int up_setup(struct uart_dev_s *dev)
    * for lower USART clocks.
    */
 
-  regval  = (SAM_USART_CLOCK + (priv->baud << 3))/(priv->baud << 4);
+  regval  = (SAM_USART_CLOCK + (priv->baud << 3)) / (priv->baud << 4);
   up_serialout(priv, SAM_UART_BRGR_OFFSET, regval);
 
   /* Enable receiver & transmitter */
@@ -853,14 +863,15 @@ static void up_shutdown(struct uart_dev_s *dev)
  * Name: up_attach
  *
  * Description:
- *   Configure the USART to operation in interrupt driven mode.  This method is
- *   called when the serial port is opened.  Normally, this is just after the
+ *   Configure the USART to operation in interrupt driven mode.  This method
+ *   is called when the serial port is opened.  Normally, this is just after
  *   the setup() method is called, however, the serial console may operate in
  *   a non-interrupt driven mode during the boot phase.
  *
- *   RX and TX interrupts are not enabled when by the attach method (unless the
- *   hardware supports multiple levels of interrupt enabling).  The RX and TX
- *   interrupts are not enabled until the txint() and rxint() methods are called.
+ *   RX and TX interrupts are not enabled when by the attach method (unless
+ *   the hardware supports multiple levels of interrupt enabling).  The RX
+ *   and TX interrupts are not enabled until the txint() and rxint() methods
+ *   are called.
  *
  ****************************************************************************/
 
@@ -880,6 +891,7 @@ static int up_attach(struct uart_dev_s *dev)
 
       up_enable_irq(priv->irq);
     }
+
   return ret;
 }
 
@@ -888,8 +900,8 @@ static int up_attach(struct uart_dev_s *dev)
  *
  * Description:
  *   Detach USART interrupts.  This method is called when the serial port is
- *   closed normally just before the shutdown method is called.  The exception
- *   is the serial console which is never shutdown.
+ *   closed normally just before the shutdown method is called.  The
+ *   exception is the serial console which is never shutdown.
  *
  ****************************************************************************/
 
@@ -933,14 +945,16 @@ static int up_interrupt(int irq, void *context, void *arg)
     {
       handled = false;
 
-      /* Get the UART/USART status (we are only interested in the unmasked interrupts). */
+      /* Get the UART/USART status (we are only interested in the unmasked
+       * interrupts).
+       */
 
       priv->sr = up_serialin(priv, SAM_UART_SR_OFFSET);  /* Save for error reporting */
       imr      = up_serialin(priv, SAM_UART_IMR_OFFSET); /* Interrupt mask */
-      pending  = priv->sr & imr;                        /* Mask out disabled interrupt sources */
+      pending  = priv->sr & imr;                         /* Mask out disabled interrupt sources */
 
-      /* Handle an incoming, receive byte.  RXRDY: At least one complete character
-       * has been received and US_RHR has not yet been read.
+      /* Handle an incoming, receive byte.  RXRDY: At least one complete
+       * character has been received and US_RHR has not yet been read.
        */
 
       if ((pending & UART_INT_RXRDY) != 0)
@@ -1013,10 +1027,6 @@ static int up_ioctl(struct file *filep, int cmd, unsigned long arg)
             break;
           }
 
-        /* Return baud */
-
-        cfsetispeed(termiosp, priv->baud);
-
         /* Return parity */
 
         termiosp->c_cflag = ((priv->parity != 0) ? PARENB : 0) |
@@ -1031,6 +1041,10 @@ static int up_ioctl(struct file *filep, int cmd, unsigned long arg)
 #if defined(CONFIG_SERIAL_IFLOWCONTROL) || defined(CONFIG_SERIAL_OFLOWCONTROL)
         termiosp->c_cflag |= (priv->flowc) ? (CCTS_OFLOW | CRTS_IFLOW): 0;
 #endif
+        /* Return baud */
+
+        cfsetispeed(termiosp, priv->baud);
+
         /* Return number of bits */
 
         switch (priv->bits)
@@ -1206,8 +1220,8 @@ static void up_rxint(struct uart_dev_s *dev, bool enable)
 
   if (enable)
     {
-      /* Receive an interrupt when their is anything in the Rx data register (or an Rx
-       * timeout occurs).
+      /* Receive an interrupt when their is anything in the Rx data register
+       * (or an RX timeout occurs).
        */
 
 #ifndef CONFIG_SUPPRESS_SERIAL_INTS

arch/arm/src/sama5/sam_flexcom_serial.c

@@ -486,7 +486,9 @@ static inline void flexus_serialout(struct flexus_dev_s *priv, int offset,
 static inline void flexus_restoreusartint(struct flexus_dev_s *priv,
                                           uint32_t imr)
 {
-  /* Restore the previous interrupt state (assuming all interrupts disabled) */
+  /* Restore the previous interrupt state (assuming all interrupts
+   * disabled)
+   */
 
   flexus_serialout(priv, SAM_FLEXUS_IER_OFFSET, imr);
 }
@@ -547,7 +549,9 @@ static int flexus_interrupt(int irq, void *context, FAR void *arg)
     {
       handled = false;
 
-      /* Get the UART/USART status (we are only interested in the unmasked interrupts). */
+      /* Get the UART/USART status (we are only interested in the unmasked
+       * interrupts).
+       */
 
       priv->sr = flexus_serialin(priv, SAM_FLEXUS_CSR_OFFSET); /* Save for error reporting */
       imr      = flexus_serialin(priv, SAM_FLEXUS_IMR_OFFSET); /* Interrupt mask */
@@ -820,10 +824,6 @@ static int flexus_ioctl(struct file *filep, int cmd, unsigned long arg)
             break;
           }
 
-        /* Return baud */
-
-        cfsetispeed(termiosp, priv->baud);
-
         /* Return parity */
 
         termiosp->c_cflag = ((priv->parity != 0) ? PARENB : 0) |
@@ -838,6 +838,10 @@ static int flexus_ioctl(struct file *filep, int cmd, unsigned long arg)
 #if defined(CONFIG_SERIAL_IFLOWCONTROL) || defined(CONFIG_SERIAL_OFLOWCONTROL)
         termiosp->c_cflag |= (priv->flowc) ? (CCTS_OFLOW | CRTS_IFLOW): 0;
 #endif
+        /* Return baud */
+
+        cfsetispeed(termiosp, priv->baud);
+
         /* Return number of bits */
 
         switch (priv->bits)

arch/arm/src/sama5/sam_serial.c

@@ -185,7 +185,9 @@
 #  endif
 #endif
 
-/* Pick ttyS1.  This could be any of UART0-4, USART0-4 excluding the console UART. */
+/* Pick ttyS1.  This could be any of UART0-4, USART0-4 excluding the
+ * console UART.
+ */
 
 #if defined(CONFIG_SAMA5_UART0) && !defined(UART0_ASSIGNED)
 #  define TTYS1_DEV           g_uart0port  /* UART0 is ttyS1 */
@@ -908,7 +910,9 @@ static inline void up_serialout(struct up_dev_s *priv, int offset,
 
 static inline void up_restoreusartint(struct up_dev_s *priv, uint32_t imr)
 {
-  /* Restore the previous interrupt state (assuming all interrupts disabled) */
+  /* Restore the previous interrupt state (assuming all interrupts
+   * disabled)
+   */
 
   up_serialout(priv, SAM_UART_IER_OFFSET, imr);
 }
@@ -969,7 +973,9 @@ static int up_interrupt(int irq, void *context, FAR void *arg)
     {
       handled = false;
 
-      /* Get the UART/USART status (we are only interested in the unmasked interrupts). */
+      /* Get the UART/USART status (we are only interested in the unmasked
+       * interrupts).
+       */
 
       priv->sr = up_serialin(priv, SAM_UART_SR_OFFSET);  /* Save for error reporting */
       imr      = up_serialin(priv, SAM_UART_IMR_OFFSET); /* Interrupt mask */
@@ -1270,10 +1276,6 @@ static int up_ioctl(struct file *filep, int cmd, unsigned long arg)
             break;
           }
 
-        /* Return baud */
-
-        cfsetispeed(termiosp, priv->baud);
-
         /* Return parity */
 
         termiosp->c_cflag = ((priv->parity != 0) ? PARENB : 0) |
@@ -1288,6 +1290,10 @@ static int up_ioctl(struct file *filep, int cmd, unsigned long arg)
 #if defined(CONFIG_SERIAL_IFLOWCONTROL) || defined(CONFIG_SERIAL_OFLOWCONTROL)
         termiosp->c_cflag |= (priv->flowc) ? (CCTS_OFLOW | CRTS_IFLOW): 0;
 #endif
+        /* Return baud */
+
+        cfsetispeed(termiosp, priv->baud);
+
         /* Return number of bits */
 
         switch (priv->bits)

arch/arm/src/samd2l2/sam_i2c_master.c

@@ -998,7 +998,7 @@ static int sam_i2c_transfer(FAR struct i2c_master_s *dev,
 
   /* Initiate the message transfer */
 
-  ret = -BUSY;
+  ret = -EBUSY;
 
   /* Initiate the transfer.  The rest will be handled from interrupt logic.
    * Interrupts must be disabled to prevent re-entrance from the interrupt

arch/arm/src/samv7/sam_serial.c

@@ -71,7 +71,9 @@
 
 /* Which UART/USART with be tty0/console and which tty1-7? */
 
-/* First pick the console and ttys0.  This could be any of UART0-4, USART0-2 */
+/* First pick the console and ttys0.  This could be any of UART0-4,
+ * USART0-2
+ */
 
 #if defined(CONFIG_UART0_SERIAL_CONSOLE)
 #    define CONSOLE_DEV         g_uart0port  /* UART0 is console */
@@ -653,18 +655,18 @@ static struct sam_dev_s g_usart2priv =
 
 static uart_dev_t g_usart2port =
 {
-  .recv     =
-  {
-    .size   = CONFIG_USART2_RXBUFSIZE,
-    .buffer = g_usart2rxbuffer,
-  },
-  .xmit     =
-  {
-    .size   = CONFIG_USART2_TXBUFSIZE,
-    .buffer = g_usart2txbuffer,
-   },
-  .ops      = &g_uart_ops,
-  .priv     = &g_usart2priv,
+  .recv       =
+    {
+      .size   = CONFIG_USART2_RXBUFSIZE,
+      .buffer = g_usart2rxbuffer,
+    },
+  .xmit       =
+    {
+      .size   = CONFIG_USART2_TXBUFSIZE,
+      .buffer = g_usart2txbuffer,
+    },
+  .ops        = &g_uart_ops,
+  .priv       = &g_usart2priv,
 };
 #endif
 
@@ -685,7 +687,8 @@ static inline uint32_t sam_serialin(struct sam_dev_s *priv, int offset)
  * Name: sam_serialout
  ****************************************************************************/
 
-static inline void sam_serialout(struct sam_dev_s *priv, int offset, uint32_t value)
+static inline void sam_serialout(struct sam_dev_s *priv, int offset,
+                                 uint32_t value)
 {
   putreg32(value, priv->usartbase + offset);
 }
@@ -696,7 +699,9 @@ static inline void sam_serialout(struct sam_dev_s *priv, int offset, uint32_t va
 
 static inline void sam_restoreusartint(struct sam_dev_s *priv, uint32_t imr)
 {
-  /* Restore the previous interrupt state (assuming all interrupts disabled) */
+  /* Restore the previous interrupt state (assuming all interrupts
+   * disabled)
+   */
 
   sam_serialout(priv, SAM_UART_IER_OFFSET, imr);
 }
@@ -759,7 +764,8 @@ static int sam_setup(struct uart_dev_s *dev)
   /* "Setting the USART to operate with hardware handshaking is performed by
    *  writing the USART_MODE field in the Mode Register (US_MR) to the value
    *  0x2. ... Using this mode requires using the PDC or DMAC channel for
-   *  reception. The transmitter can handle hardware handshaking in any case."
+   *  reception. The transmitter can handle hardware handshaking in any
+   *  case."
    */
 
   if (priv->flowc)
@@ -921,14 +927,15 @@ static void sam_shutdown(struct uart_dev_s *dev)
  * Name: sam_attach
  *
  * Description:
- *   Configure the USART to operation in interrupt driven mode.  This method is
- *   called when the serial port is opened.  Normally, this is just after the
+ *   Configure the USART to operation in interrupt driven mode.  This method
+ *   is called when the serial port is opened.  Normally, this is just after
  *   the setup() method is called, however, the serial console may operate in
  *   a non-interrupt driven mode during the boot phase.
  *
- *   RX and TX interrupts are not enabled when by the attach method (unless the
- *   hardware supports multiple levels of interrupt enabling).  The RX and TX
- *   interrupts are not enabled until the txint() and rxint() methods are called.
+ *   RX and TX interrupts are not enabled when by the attach method (unless
+ *   the hardware supports multiple levels of interrupt enabling).  The RX
+ *   and TX interrupts are not enabled until the txint() and rxint() methods
+ *   are called.
  *
  ****************************************************************************/
 
@@ -957,8 +964,8 @@ static int sam_attach(struct uart_dev_s *dev)
  *
  * Description:
  *   Detach USART interrupts.  This method is called when the serial port is
- *   closed normally just before the shutdown method is called.  The exception
- *   is the serial console which is never shutdown.
+ *   closed normally just before the shutdown method is called.  The
+ *   exception is the serial console which is never shutdown.
  *
  ****************************************************************************/
 
@@ -1001,14 +1008,16 @@ static int sam_interrupt(int irq, void *context, FAR void *arg)
     {
       handled = false;
 
-      /* Get the UART/USART status (we are only interested in the unmasked interrupts). */
+      /* Get the UART/USART status (we are only interested in the unmasked
+       * interrupts).
+       */
 
       priv->sr = sam_serialin(priv, SAM_UART_SR_OFFSET);
       imr      = sam_serialin(priv, SAM_UART_IMR_OFFSET);
       pending  = priv->sr & imr;
 
-      /* Handle an incoming, receive byte.  RXRDY: At least one complete character
-       * has been received and US_RHR has not yet been read.
+      /* Handle an incoming, receive byte.  RXRDY: At least one complete
+       * character has been received and US_RHR has not yet been read.
        */
 
       if ((pending & UART_INT_RXRDY) != 0)
@@ -1081,10 +1090,6 @@ static int sam_ioctl(struct file *filep, int cmd, unsigned long arg)
             break;
           }
 
-        /* Return baud */
-
-        cfsetispeed(termiosp, priv->baud);
-
         /* Return parity */
 
         termiosp->c_cflag = ((priv->parity != 0) ? PARENB : 0) |
@@ -1099,6 +1104,10 @@ static int sam_ioctl(struct file *filep, int cmd, unsigned long arg)
 #if defined(CONFIG_SERIAL_IFLOWCONTROL) || defined(CONFIG_SERIAL_OFLOWCONTROL)
         termiosp->c_cflag |= (priv->flowc) ? (CCTS_OFLOW | CRTS_IFLOW): 0;
 #endif
+        /* Return baud */
+
+        cfsetispeed(termiosp, priv->baud);
+
         /* Return number of bits */
 
         switch (priv->bits)
@@ -1274,8 +1283,8 @@ static void sam_rxint(struct uart_dev_s *dev, bool enable)
 
   if (enable)
     {
-      /* Receive an interrupt when their is anything in the Rx data register (or an Rx
-       * timeout occurs).
+      /* Receive an interrupt when their is anything in the Rx data register
+       * (or an RX timeout occurs).
        */
 
 #ifndef CONFIG_SUPPRESS_SERIAL_INTS

arch/arm/src/stm32/stm32_serial.c

@@ -2019,8 +2019,6 @@ static int up_ioctl(struct file *filep, int cmd, unsigned long arg)
             break;
           }
 
-        cfsetispeed(termiosp, priv->baud);
-
         /* Note that since we only support 8/9 bit modes and
          * there is no way to report 9-bit mode, we always claim 8.
          */
@@ -2037,6 +2035,8 @@ static int up_ioctl(struct file *filep, int cmd, unsigned long arg)
 #endif
           CS8;
 
+        cfsetispeed(termiosp, priv->baud);
+
         /* TODO: CCTS_IFLOW, CCTS_OFLOW */
       }
       break;

arch/arm/src/stm32f7/stm32_serial.c

@@ -2568,8 +2568,6 @@ static int up_ioctl(struct file *filep, int cmd, unsigned long arg)
             break;
           }
 
-        cfsetispeed(termiosp, priv->baud);
-
         /* Note that since we only support 8/9 bit modes and
          * there is no way to report 9-bit mode, we always claim 8.
          */
@@ -2586,6 +2584,8 @@ static int up_ioctl(struct file *filep, int cmd, unsigned long arg)
 #endif
           CS8;
 
+        cfsetispeed(termiosp, priv->baud);
+
         /* TODO: CCTS_IFLOW, CCTS_OFLOW */
       }
       break;

arch/arm/src/stm32h7/stm32_otghost.c

@@ -1231,7 +1231,7 @@ static void stm32_chan_wakeup(FAR struct stm32_usbhost_s *priv,
  ****************************************************************************/
 
 static int stm32_ctrlchan_alloc(FAR struct stm32_usbhost_s *priv,
-                                uint8_t epno, uint8_t funcaddr
+                                uint8_t epno, uint8_t funcaddr,
                                 uint8_t speed,
                                 FAR struct stm32_ctrlinfo_s *ctrlep)
 {
@@ -4237,6 +4237,7 @@ static int stm32_epalloc(FAR struct usbhost_driver_s *drvr,
 static int stm32_epfree(FAR struct usbhost_driver_s *drvr, usbhost_ep_t ep)
 {
   FAR struct stm32_usbhost_s *priv = (FAR struct stm32_usbhost_s *)drvr;
+  int ret;
 
   DEBUGASSERT(priv);
 

arch/arm/src/stm32h7/stm32_serial.c

@@ -1670,8 +1670,6 @@ static int up_ioctl(struct file *filep, int cmd, unsigned long arg)
             break;
           }
 
-        cfsetispeed(termiosp, priv->baud);
-
         /* Note that since we only support 8/9 bit modes and
          * there is no way to report 9-bit mode, we always claim 8.
          */
@@ -1688,6 +1686,8 @@ static int up_ioctl(struct file *filep, int cmd, unsigned long arg)
 #endif
           CS8;
 
+        cfsetispeed(termiosp, priv->baud);
+
         /* TODO: CCTS_IFLOW, CCTS_OFLOW */
       }
       break;

arch/arm/src/stm32l4/stm32l4_can.c

@@ -72,6 +72,7 @@
  ****************************************************************************/
 
 /* Delays *******************************************************************/
+
 /* Time out for INAK bit */
 
 #define INAK_TIMEOUT 65535
@@ -162,9 +163,12 @@ static bool stm32l4can_txempty(FAR struct can_dev_s *dev);
 /* CAN interrupt handling */
 
 static int  stm32l4can_rxinterrupt(int irq, FAR void *context, int rxmb);
-static int  stm32l4can_rx0interrupt(int irq, FAR void *context, FAR void *arg);
-static int  stm32l4can_rx1interrupt(int irq, FAR void *context, FAR void *arg);
-static int  stm32l4can_txinterrupt(int irq, FAR void *context, FAR void *arg);
+static int  stm32l4can_rx0interrupt(int irq, FAR void *context,
+                                    FAR void *arg);
+static int  stm32l4can_rx1interrupt(int irq, FAR void *context,
+                                    FAR void *arg);
+static int  stm32l4can_txinterrupt(int irq, FAR void *context,
+                                   FAR void *arg);
 
 /* Initialization */
 
@@ -272,7 +276,7 @@ static uint32_t stm32l4can_vgetreg(uint32_t addr)
         {
           /* Yes.. then show how many times the value repeated */
 
-          caninfo("[repeats %d more times]\n", count-3);
+          caninfo("[repeats %d more times]\n", count - 3);
         }
 
       /* Save the new address, value, and count */
@@ -293,7 +297,8 @@ static uint32_t stm32l4can_getreg(FAR struct stm32l4_can_s *priv, int offset)
   return stm32l4can_vgetreg(priv->base + offset);
 }
 
-static uint32_t stm32l4can_getfreg(FAR struct stm32l4_can_s *priv, int offset)
+static uint32_t stm32l4can_getfreg(FAR struct stm32l4_can_s *priv,
+                                   int offset)
 {
   return stm32l4can_vgetreg(priv->fbase + offset);
 }
@@ -304,7 +309,8 @@ static uint32_t stm32l4can_getreg(FAR struct stm32l4_can_s *priv, int offset)
   return getreg32(priv->base + offset);
 }
 
-static uint32_t stm32l4can_getfreg(FAR struct stm32l4_can_s *priv, int offset)
+static uint32_t stm32l4can_getfreg(FAR struct stm32l4_can_s *priv,
+                                   int offset)
 {
   return getreg32(priv->fbase + offset);
 }
@@ -815,11 +821,14 @@ static int stm32l4can_ioctl(FAR struct can_dev_s *dev, int cmd,
 
           DEBUGASSERT(bt != NULL);
           regval       = stm32l4can_getreg(priv, STM32L4_CAN_BTR_OFFSET);
-          bt->bt_sjw   = ((regval & CAN_BTR_SJW_MASK) >> CAN_BTR_SJW_SHIFT) + 1;
-          bt->bt_tseg1 = ((regval & CAN_BTR_TS1_MASK) >> CAN_BTR_TS1_SHIFT) + 1;
-          bt->bt_tseg2 = ((regval & CAN_BTR_TS2_MASK) >> CAN_BTR_TS2_SHIFT) + 1;
-
-          brp          = ((regval & CAN_BTR_BRP_MASK) >> CAN_BTR_BRP_SHIFT) + 1;
+          bt->bt_sjw   = ((regval & CAN_BTR_SJW_MASK) >>
+                           CAN_BTR_SJW_SHIFT) + 1;
+          bt->bt_tseg1 = ((regval & CAN_BTR_TS1_MASK) >>
+                           CAN_BTR_TS1_SHIFT) + 1;
+          bt->bt_tseg2 = ((regval & CAN_BTR_TS2_MASK) >>
+                           CAN_BTR_TS2_SHIFT) + 1;
+          brp          = ((regval & CAN_BTR_BRP_MASK) >>
+                           CAN_BTR_BRP_SHIFT) + 1;
           bt->bt_baud  = STM32L4_PCLK1_FREQUENCY /
                          (brp * (bt->bt_tseg1 + bt->bt_tseg2 + 1));
           ret = OK;
@@ -839,8 +848,8 @@ static int stm32l4can_ioctl(FAR struct can_dev_s *dev, int cmd,
        * REVISIT: There is probably a limitation here:  If there are multiple
        * threads trying to send CAN packets, when one of these threads
        * reconfigures the bitrate, the MCAN hardware will be reset and the
-       * context of operation will be lost.  Hence, this IOCTL can only safely
-       * be executed in quiescent time periods.
+       * context of operation will be lost.  Hence, this IOCTL can only
+       * safely be executed in quiescent time periods.
        */
 
       case CANIOC_SET_BITTIMING:
@@ -860,8 +869,9 @@ static int stm32l4can_ioctl(FAR struct can_dev_s *dev, int cmd,
 
           regval = stm32l4can_getreg(priv, STM32L4_CAN_BTR_OFFSET);
 
-          /* Extract bit timing data */
-          /* tmp is in clocks per bit time */
+          /* Extract bit timing data.
+           * tmp is in clocks per bit time.
+           */
 
           tmp = STM32L4_PCLK1_FREQUENCY / bt->bt_baud;
 
@@ -884,7 +894,7 @@ static int stm32l4can_ioctl(FAR struct can_dev_s *dev, int cmd,
 
           else
             {
-              brp = (tmp + (can_bit_quanta/2)) / can_bit_quanta;
+              brp = (tmp + (can_bit_quanta / 2)) / can_bit_quanta;
               DEBUGASSERT(brp >= 1 && brp <= CAN_BTR_BRP_MAX);
             }
 
@@ -1013,7 +1023,7 @@ static int stm32l4can_ioctl(FAR struct can_dev_s *dev, int cmd,
         {
           DEBUGASSERT(arg != 0);
           ret = stm32l4can_addextfilter(priv,
-                                        (FAR struct canioc_extfilter_s *)arg);
+                                      (FAR struct canioc_extfilter_s *)arg);
         }
         break;
 
@@ -1050,7 +1060,7 @@ static int stm32l4can_ioctl(FAR struct can_dev_s *dev, int cmd,
         {
           DEBUGASSERT(arg != 0);
           ret = stm32l4can_addstdfilter(priv,
-                                        (FAR struct canioc_stdfilter_s *)arg);
+                                      (FAR struct canioc_stdfilter_s *)arg);
         }
         break;
 
@@ -1076,12 +1086,13 @@ static int stm32l4can_ioctl(FAR struct can_dev_s *dev, int cmd,
       case CANIOC_SET_NART:
         {
           uint32_t regval;
-          ret = stm32can_enterinitmode(priv);
+          ret = stm32l4can_enterinitmode(priv);
           if (ret != 0)
             {
               return ret;
             }
-          regval = stm32can_getreg(priv, STM32_CAN_MCR_OFFSET);
+
+          regval = stm32l4can_getreg(priv, STM32L4_CAN_MCR_OFFSET);
           if (arg == 1)
             {
               regval |= CAN_MCR_NART;
@@ -1090,20 +1101,22 @@ static int stm32l4can_ioctl(FAR struct can_dev_s *dev, int cmd,
             {
               regval &= ~CAN_MCR_NART;
             }
-          stm32can_putreg(priv, STM32_CAN_MCR_OFFSET, regval);
-          return stm32can_exitinitmode(priv);
+
+          stm32l4can_putreg(priv, STM32L4_CAN_MCR_OFFSET, regval);
+          return stm32l4can_exitinitmode(priv);
         }
         break;
 
       case CANIOC_SET_ABOM:
         {
           uint32_t regval;
-          ret = stm32can_enterinitmode(priv);
+          ret = stm32l4can_enterinitmode(priv);
           if (ret != 0)
             {
               return ret;
             }
-          regval = stm32can_getreg(priv, STM32_CAN_MCR_OFFSET);
+
+          regval = stm32l4can_getreg(priv, STM32L4_CAN_MCR_OFFSET);
           if (arg == 1)
             {
               regval |= CAN_MCR_ABOM;
@@ -1112,8 +1125,9 @@ static int stm32l4can_ioctl(FAR struct can_dev_s *dev, int cmd,
             {
               regval &= ~CAN_MCR_ABOM;
             }
-          stm32can_putreg(priv, STM32_CAN_MCR_OFFSET, regval);
-          return stm32can_exitinitmode(priv);
+
+          stm32l4can_putreg(priv, STM32L4_CAN_MCR_OFFSET, regval);
+          return stm32l4can_exitinitmode(priv);
         }
         break;
 
@@ -1226,7 +1240,8 @@ static int stm32l4can_send(FAR struct can_dev_s *dev,
       regval |= msg->cm_hdr.ch_id << CAN_TIR_STID_SHIFT;
     }
 #else
-   regval |= ( ( (uint32_t) msg->cm_hdr.ch_id << CAN_TIR_STID_SHIFT) & CAN_TIR_STID_MASK );
+  regval |= (((uint32_t) msg->cm_hdr.ch_id << CAN_TIR_STID_SHIFT) &
+             CAN_TIR_STID_MASK);
 
 #ifdef CONFIG_CAN_USE_RTR
   regval |= (msg->cm_hdr.ch_rtr ? CAN_TIR_RTR : 0);
@@ -1728,16 +1743,16 @@ static int stm32l4can_bittiming(FAR struct stm32l4_can_s *priv)
         }
     }
 
-  /* Otherwise, nquanta is CAN_BIT_QUANTA, ts1 is CONFIG_STM32L4_CAN_TSEG1, ts2 is
-   * CONFIG_STM32L4_CAN_TSEG2 and we calculate brp to achieve CAN_BIT_QUANTA quanta
-   * in the bit time
+  /* Otherwise, nquanta is CAN_BIT_QUANTA, ts1 is CONFIG_STM32L4_CAN_TSEG1,
+   * ts2 is CONFIG_STM32L4_CAN_TSEG2 and we calculate brp to achieve
+   * CAN_BIT_QUANTA quanta in the bit time
    */
 
   else
     {
       ts1 = CONFIG_STM32L4_CAN_TSEG1;
       ts2 = CONFIG_STM32L4_CAN_TSEG2;
-      brp = (tmp + (CAN_BIT_QUANTA/2)) / CAN_BIT_QUANTA;
+      brp = (tmp + (CAN_BIT_QUANTA / 2)) / CAN_BIT_QUANTA;
       DEBUGASSERT(brp >= 1 && brp <= CAN_BTR_BRP_MAX);
     }
 
@@ -1756,7 +1771,8 @@ static int stm32l4can_bittiming(FAR struct stm32l4_can_s *priv)
   tmp = ((brp - 1) << CAN_BTR_BRP_SHIFT) | ((ts1 - 1) << CAN_BTR_TS1_SHIFT) |
         ((ts2 - 1) << CAN_BTR_TS2_SHIFT) | ((1 - 1) << CAN_BTR_SJW_SHIFT);
 #ifdef CONFIG_CAN_LOOPBACK
-//tmp |= (CAN_BTR_LBKM | CAN_BTR_SILM);
+  /* tmp |= (CAN_BTR_LBKM | CAN_BTR_SILM); */
+
   tmp |= CAN_BTR_LBKM;
 #endif
 

arch/arm/src/stm32l4/stm32l4_serial.c

@@ -2013,8 +2013,6 @@ static int stm32l4serial_ioctl(FAR struct file *filep, int cmd,
             break;
           }
 
-        cfsetispeed(termiosp, priv->baud);
-
         /* Note that since we only support 8/9 bit modes and
          * there is no way to report 9-bit mode, we always claim 8.
          */
@@ -2031,6 +2029,8 @@ static int stm32l4serial_ioctl(FAR struct file *filep, int cmd,
 #endif
           CS8;
 
+        cfsetispeed(termiosp, priv->baud);
+
         /* TODO: CCTS_IFLOW, CCTS_OFLOW */
       }
       break;

arch/arm/src/tiva/common/tiva_hciuart.c

@@ -1040,7 +1040,7 @@ static int hciuart_configure(const struct hciuart_config_s *config)
   config->state->im = hciuart_getreg32(config, TIVA_UART_IM_OFFSET);
 
   hciuart_putreg32(config, TIVA_UART_IFLS_OFFSET,
-                   UART_IFLS_TXIFLSEL_18th | UART_IFLS_RXIFLSEL_78th);
+                   UART_IFLS_TXIFLSEL_18TH | UART_IFLS_RXIFLSEL_78TH);
 
   hciuart_putreg32(config, TIVA_UART_IM_OFFSET, UART_IM_RXIM | UART_IM_RTIM);
 
@@ -1585,7 +1585,9 @@ static ssize_t hciuart_write(const struct btuart_lowerhalf_s *lower,
         }
     }
 
-  /* If the Tx buffer is not empty, then exit with the Tx interrupts enabled. */
+  /* If the Tx buffer is not empty, then exit with the Tx interrupts
+   * enabled.
+   */
 
   if (state->txhead != state->txtail)
     {

arch/arm/src/tiva/common/tiva_serial.c

@@ -435,18 +435,18 @@ static struct up_dev_s g_uart1priv =
 
 static uart_dev_t g_uart1port =
 {
-  .recv     =
-  {
-    .size   = CONFIG_UART1_RXBUFSIZE,
-    .buffer = g_uart1rxbuffer,
-  },
-  .xmit     =
-  {
-    .size   = CONFIG_UART1_TXBUFSIZE,
-    .buffer = g_uart1txbuffer,
-   },
-  .ops      = &g_uart_ops,
-  .priv     = &g_uart1priv,
+  .recv       =
+    {
+      .size   = CONFIG_UART1_RXBUFSIZE,
+      .buffer = g_uart1rxbuffer,
+    },
+  .xmit       =
+    {
+      .size   = CONFIG_UART1_TXBUFSIZE,
+      .buffer = g_uart1txbuffer,
+    },
+  .ops        = &g_uart_ops,
+  .priv       = &g_uart1priv,
 };
 #endif
 
@@ -465,18 +465,18 @@ static struct up_dev_s g_uart2priv =
 
 static uart_dev_t g_uart2port =
 {
-  .recv     =
-  {
-    .size   = CONFIG_UART2_RXBUFSIZE,
-    .buffer = g_uart2rxbuffer,
-  },
-  .xmit     =
-  {
-    .size   = CONFIG_UART2_TXBUFSIZE,
-    .buffer = g_uart2txbuffer,
-   },
-  .ops      = &g_uart_ops,
-  .priv     = &g_uart2priv,
+  .recv       =
+    {
+      .size   = CONFIG_UART2_RXBUFSIZE,
+      .buffer = g_uart2rxbuffer,
+    },
+  .xmit       =
+    {
+      .size   = CONFIG_UART2_TXBUFSIZE,
+      .buffer = g_uart2txbuffer,
+    },
+  .ops        = &g_uart_ops,
+  .priv       = &g_uart2priv,
 };
 #endif
 
@@ -495,18 +495,18 @@ static struct up_dev_s g_uart3priv =
 
 static uart_dev_t g_uart3port =
 {
-  .recv     =
-  {
-    .size   = CONFIG_UART3_RXBUFSIZE,
-    .buffer = g_uart3rxbuffer,
-  },
-  .xmit     =
-  {
-    .size   = CONFIG_UART3_TXBUFSIZE,
-    .buffer = g_uart3txbuffer,
-  },
-  .ops      = &g_uart_ops,
-  .priv     = &g_uart3priv,
+  .recv       =
+    {
+      .size   = CONFIG_UART3_RXBUFSIZE,
+      .buffer = g_uart3rxbuffer,
+    },
+  .xmit       =
+    {
+      .size   = CONFIG_UART3_TXBUFSIZE,
+      .buffer = g_uart3txbuffer,
+    },
+  .ops        = &g_uart_ops,
+  .priv       = &g_uart3priv,
 };
 #endif
 
@@ -555,18 +555,18 @@ static struct up_dev_s g_uart5priv =
 
 static uart_dev_t g_uart5port =
 {
-  .recv     =
-  {
-    .size   = CONFIG_UART5_RXBUFSIZE,
-    .buffer = g_uart5rxbuffer,
-  },
-  .xmit     =
-  {
-    .size   = CONFIG_UART5_TXBUFSIZE,
-    .buffer = g_uart5txbuffer,
-  },
-  .ops      = &g_uart_ops,
-  .priv     = &g_uart5priv,
+  .recv       =
+    {
+      .size   = CONFIG_UART5_RXBUFSIZE,
+      .buffer = g_uart5rxbuffer,
+    },
+  .xmit       =
+    {
+      .size   = CONFIG_UART5_TXBUFSIZE,
+      .buffer = g_uart5txbuffer,
+    },
+  .ops        = &g_uart_ops,
+  .priv       = &g_uart5priv,
 };
 #endif
 
@@ -585,18 +585,18 @@ static struct up_dev_s g_uart6priv =
 
 static uart_dev_t g_uart6port =
 {
-  .recv     =
-  {
-    .size   = CONFIG_UART6_RXBUFSIZE,
-    .buffer = g_uart6rxbuffer,
-  },
-  .xmit     =
-  {
-    .size   = CONFIG_UART6_TXBUFSIZE,
-    .buffer = g_uart6txbuffer,
-  },
-  .ops      = &g_uart_ops,
-  .priv     = &g_uart6priv,
+  .recv       =
+    {
+      .size   = CONFIG_UART6_RXBUFSIZE,
+      .buffer = g_uart6rxbuffer,
+    },
+  .xmit       =
+    {
+      .size   = CONFIG_UART6_TXBUFSIZE,
+      .buffer = g_uart6txbuffer,
+    },
+  .ops        = &g_uart_ops,
+  .priv       = &g_uart6priv,
 };
 #endif
 
@@ -615,18 +615,18 @@ static struct up_dev_s g_uart7priv =
 
 static uart_dev_t g_uart7port =
 {
-  .recv     =
-  {
-    .size   = CONFIG_UART7_RXBUFSIZE,
-    .buffer = g_uart7rxbuffer,
-  },
-  .xmit     =
-  {
-    .size   = CONFIG_UART7_TXBUFSIZE,
-    .buffer = g_uart7txbuffer,
-  },
-  .ops      = &g_uart_ops,
-  .priv     = &g_uart7priv,
+  .recv       =
+    {
+      .size   = CONFIG_UART7_RXBUFSIZE,
+      .buffer = g_uart7rxbuffer,
+    },
+  .xmit       =
+    {
+      .size   = CONFIG_UART7_TXBUFSIZE,
+      .buffer = g_uart7txbuffer,
+    },
+  .ops        = &g_uart_ops,
+  .priv       = &g_uart7priv,
 };
 #endif
 
@@ -647,7 +647,8 @@ static inline uint32_t up_serialin(struct up_dev_s *priv, int offset)
  * Name: up_serialout
  ****************************************************************************/
 
-static inline void up_serialout(struct up_dev_s *priv, int offset, uint32_t value)
+static inline void up_serialout(struct up_dev_s *priv, int offset,
+                                uint32_t value)
 {
   putreg32(value, priv->uartbase + offset);
 }
@@ -749,36 +750,37 @@ static void up_set_format(struct uart_dev_s *dev)
    * "The baud-rate divisor is a 22-bit number consisting of a 16-bit integer
    *  and a 6-bit fractional part. The number formed by these two values is
    *  used by the baud-rate generator to determine the bit period. Having a
-   *  fractional baud-rate divider allows the UART to generate all the standard
-   *  baud rates.
+   *  fractional baud-rate divider allows the UART to generate all the
+   *  standard baud rates.
    *
    * "The 16-bit integer is loaded through the UART Integer Baud-Rate Divisor
-   *  (UARTIBRD) register ... and the 6-bit fractional part is loaded with the
-   *  UART Fractional Baud-Rate Divisor (UARTFBRD) register... The baud-rate
-   *  divisor (BRD) has the following relationship to the system clock (where
-   *  BRDI is the integer part of the BRD and BRDF is the fractional part,
-   *  separated by a decimal place.):
+   *  (UARTIBRD) register ... and the 6-bit fractional part is loaded with
+   *  the UART Fractional Baud-Rate Divisor (UARTFBRD) register... The
+   *  baud-rate divisor (BRD) has the following relationship to the system
+   *  clock (where BRDI is the integer part of the BRD and BRDF is the
+   *  fractional part, separated by a decimal place.):
    *
    *    "BRD = BRDI + BRDF = UARTSysClk / (16 * Baud Rate)
    *
    * "where UARTSysClk is the system clock connected to the UART. The 6-bit
-   *  fractional number (that is to be loaded into the DIVFRAC bit field in the
-   *  UARTFBRD register) can be calculated by taking the fractional part of the
-   *  baud-rate divisor, multiplying it by 64, and adding 0.5 to account for
-   *  rounding errors:
+   *  fractional number (that is to be loaded into the DIVFRAC bit field in
+   *  the UARTFBRD register) can be calculated by taking the fractional part
+   *  of the baud-rate divisor, multiplying it by 64, and adding 0.5 to
+   *  account for rounding errors:
    *
    *    "UARTFBRD[DIVFRAC] = integer(BRDF * 64 + 0.5)
    *
-   * "The UART generates an internal baud-rate reference clock at 16x the baud-
-   *  rate (referred to as Baud16). This reference clock is divided by 16 to
-   *  generate the transmit clock, and is used for error detection during receive
-   *  operations.
+   * "The UART generates an internal baud-rate reference clock at 16x the
+   *  baud-rate (referred to as Baud16). This reference clock is divided by
+   *  16 to generate the transmit clock, and is used for error detection
+   *  during receive operations.
    *
-   * "Along with the UART Line Control, High Byte (UARTLCRH) register ..., the
-   *  UARTIBRD and UARTFBRD registers form an internal 30-bit register. This
-   *  internal register is only updated when a write operation to UARTLCRH is
-   *  performed, so any changes to the baud-rate divisor must be followed by a
-   *  write to the UARTLCRH register for the changes to take effect. ..."
+   * "Along with the UART Line Control, High Byte (UARTLCRH) register ...,
+   *  the UARTIBRD and UARTFBRD registers form an internal 30-bit register.
+   *  This internal register is only updated when a write operation to
+   *  UARTLCRH is performed, so any changes to the baud-rate divisor must be
+   *  followed by a write to the UARTLCRH register for the changes to take
+   *  effect. ..."
    */
 
   den       = priv->baud << 4;
@@ -865,14 +867,15 @@ static int up_setup(struct uart_dev_s *dev)
    */
 
   up_serialout(priv, TIVA_UART_IFLS_OFFSET,
-               UART_IFLS_TXIFLSEL_18th | UART_IFLS_RXIFLSEL_18th);
+               UART_IFLS_TXIFLSEL_18TH | UART_IFLS_RXIFLSEL_18TH);
 
   /* Flush the Rx and Tx FIFOs -- How do you do that? */
 
-  /* Enable Rx interrupts from the UART except for Tx interrupts.  We don't want
-   * Tx interrupts until we have something to send.  We will check for serial
-   * errors as part of Rx interrupt processing (no interrupts will be received
-   * yet because the interrupt is still disabled at the interrupt controller.
+  /* Enable Rx interrupts from the UART except for Tx interrupts.  We don't
+   * want TX interrupts until we have something to send.  We will check for
+   * serial errors as part of Rx interrupt processing (no interrupts will be
+   * received yet because the interrupt is still disabled at the interrupt
+   * controller.
    */
 
   up_serialout(priv, TIVA_UART_IM_OFFSET, UART_IM_RXIM | UART_IM_RTIM);
@@ -919,9 +922,10 @@ static void up_shutdown(struct uart_dev_s *dev)
  *   the setup() method is called, however, the serial console may operate in
  *   a non-interrupt driven mode during the boot phase.
  *
- *   RX and TX interrupts are not enabled when by the attach method (unless the
- *   hardware supports multiple levels of interrupt enabling).  The RX and TX
- *   interrupts are not enabled until the txint() and rxint() methods are called.
+ *   RX and TX interrupts are not enabled when by the attach method (unless
+ *   the hardware supports multiple levels of interrupt enabling).  The RX
+ *   and TX interrupts are not enabled until the txint() and rxint() methods
+ *   are called.
  *
  ****************************************************************************/
 
@@ -950,8 +954,8 @@ static int up_attach(struct uart_dev_s *dev)
  *
  * Description:
  *   Detach UART interrupts.  This method is called when the serial port is
- *   closed normally just before the shutdown method is called.  The exception is
- *   the serial console which is never shutdown.
+ *   closed normally just before the shutdown method is called.  The
+ *   exception is the serial console which is never shutdown.
  *
  ****************************************************************************/
 
@@ -1073,8 +1077,6 @@ static int up_ioctl(struct file *filep, int cmd, unsigned long arg)
             break;
           }
 
-        cfsetispeed(termiosp, priv->baud);
-
         if (priv->bits >= 5 && priv->bits <= 8)
           {
             ccflag |= (CS5 + (priv->bits - 5));
@@ -1099,6 +1101,8 @@ static int up_ioctl(struct file *filep, int cmd, unsigned long arg)
          */
 
         termiosp->c_cflag = ccflag;
+
+        cfsetispeed(termiosp, priv->baud);
       }
       break;
 
@@ -1204,6 +1208,7 @@ static void up_rxint(struct uart_dev_s *dev, bool enable)
     {
       priv->im &= ~(UART_IM_RXIM | UART_IM_RTIM);
     }
+
   up_serialout(priv, TIVA_UART_IM_OFFSET, priv->im);
 }
 
@@ -1277,6 +1282,7 @@ static void up_txint(struct uart_dev_s *dev, bool enable)
       priv->im &= ~UART_IM_TXIM;
       up_serialout(priv, TIVA_UART_IM_OFFSET, priv->im);
     }
+
   leave_critical_section(flags);
 }
 

arch/arm/src/tiva/hardware/cc13x0/cc13x0_uart.h

@@ -67,7 +67,7 @@
 #define TIVA_UART_RIS_OFFSET       0x003c /* UART Raw Interrupt Status */
 #define TIVA_UART_MIS_OFFSET       0x0040 /* UART Masked Interrupt Status */
 #define TIVA_UART_ICR_OFFSET       0x0044 /* UART Interrupt Clear */
-#define TIVA_UART_DMACTL_OFFSET    0x0048  /* UART DMA Control */
+#define TIVA_UART_DMACTL_OFFSET    0x0048 /* UART DMA Control */
 
 #define TIVA_UART_PERIPHID4_OFFSET 0x0fd0 /* UART Peripheral Identification 4 */
 #define TIVA_UART_PERIPHID5_OFFSET 0x0fd4 /* UART Peripheral Identification 5 */
@@ -168,11 +168,13 @@
 #define UART_LCRH_STP2             (1 << 3)  /* Bit 3:  UART Two Stop Bits Select */
 #define UART_LCRH_FEN              (1 << 4)  /* Bit 4:  UART Enable FIFOs */
 #define UART_LCRH_WLEN_SHIFT       5         /* Bits 6-5: UART Word Length */
+
 #define UART_LCRH_WLEN_MASK        (3 << UART_LCRH_WLEN_SHIFT)
 #  define UART_LCRH_WLEN_5BITS     (0 << UART_LCRH_WLEN_SHIFT) /* 5-bits (reset) */
 #  define UART_LCRH_WLEN_6BITS     (1 << UART_LCRH_WLEN_SHIFT) /* 6-bits */
 #  define UART_LCRH_WLEN_7BITS     (2 << UART_LCRH_WLEN_SHIFT) /* 7-bits */
 #  define UART_LCRH_WLEN_8BITS     (3 << UART_LCRH_WLEN_SHIFT) /* 8-bits */
+
 #define UART_LCRH_SPS              (1 << 7)  /* Bit 7:  UART Stick Parity Select */
 
 /* UART Control (CTL) */
@@ -189,18 +191,19 @@
 
 #define UART_IFLS_TXIFLSEL_SHIFT   0         /* Bits 0-2: UART Transmit Interrupt FIFO Level Select */
 #define UART_IFLS_TXIFLSEL_MASK    (7 << UART_IFLS_TXIFLSEL_SHIFT)
-#  define UART_IFLS_TXIFLSEL_18th  (0 << UART_IFLS_TXIFLSEL_SHIFT) /* 1/8th full */
-#  define UART_IFLS_TXIFLSEL_14th  (1 << UART_IFLS_TXIFLSEL_SHIFT) /* 1/4th full */
-#  define UART_IFLS_TXIFLSEL_half  (2 << UART_IFLS_TXIFLSEL_SHIFT) /* half full */
-#  define UART_IFLS_TXIFLSEL_34th  (3 << UART_IFLS_TXIFLSEL_SHIFT) /* 3/4th full */
-#  define UART_IFLS_TXIFLSEL_78th  (4 << UART_IFLS_TXIFLSEL_SHIFT) /* 7/8th full */
+#  define UART_IFLS_TXIFLSEL_18TH  (0 << UART_IFLS_TXIFLSEL_SHIFT) /* 1/8th full */
+#  define UART_IFLS_TXIFLSEL_14TH  (1 << UART_IFLS_TXIFLSEL_SHIFT) /* 1/4th full */
+#  define UART_IFLS_TXIFLSEL_HALF  (2 << UART_IFLS_TXIFLSEL_SHIFT) /* half full */
+#  define UART_IFLS_TXIFLSEL_34TH  (3 << UART_IFLS_TXIFLSEL_SHIFT) /* 3/4th full */
+#  define UART_IFLS_TXIFLSEL_78TH  (4 << UART_IFLS_TXIFLSEL_SHIFT) /* 7/8th full */
+
 #define UART_IFLS_RXIFLSEL_SHIFT   3         /* Bits 3-5: UART Receive Interrupt FIFO Level Select */
 #define UART_IFLS_RXIFLSEL_MASK    (7 << UART_IFLS_RXIFLSEL_SHIFT)
-#  define UART_IFLS_RXIFLSEL_18th  (0 << UART_IFLS_RXIFLSEL_SHIFT) /* 1/8th full */
-#  define UART_IFLS_RXIFLSEL_14th  (1 << UART_IFLS_RXIFLSEL_SHIFT) /* 1/4th full */
-#  define UART_IFLS_RXIFLSEL_half  (2 << UART_IFLS_RXIFLSEL_SHIFT) /* half full */
-#  define UART_IFLS_RXIFLSEL_34th  (3 << UART_IFLS_RXIFLSEL_SHIFT) /* 3/4th full */
-#  define UART_IFLS_RXIFLSEL_78th  (4 << UART_IFLS_RXIFLSEL_SHIFT) /* 7/8th full */
+#  define UART_IFLS_RXIFLSEL_18TH  (0 << UART_IFLS_RXIFLSEL_SHIFT) /* 1/8th full */
+#  define UART_IFLS_RXIFLSEL_14TH  (1 << UART_IFLS_RXIFLSEL_SHIFT) /* 1/4th full */
+#  define UART_IFLS_RXIFLSEL_HALF  (2 << UART_IFLS_RXIFLSEL_SHIFT) /* half full */
+#  define UART_IFLS_RXIFLSEL_34TH  (3 << UART_IFLS_RXIFLSEL_SHIFT) /* 3/4th full */
+#  define UART_IFLS_RXIFLSEL_78TH  (4 << UART_IFLS_RXIFLSEL_SHIFT) /* 7/8th full */
 
 /* UART Interrupt Mask (IM) */
 
@@ -260,8 +263,4 @@
  * Public Data
  ************************************************************************************/
 
-/************************************************************************************
- * Public Functions
- ************************************************************************************/
-
 #endif /* __ARCH_ARM_SRC_TIVA_HARDWARE_CC13X0_CC13X0_UART_H */

arch/arm/src/tiva/hardware/cc13x2_cc26x2/cc13x2_cc26x2_uart.h

@@ -172,11 +172,13 @@
 #define UART_LCRH_STP2             (1 << 3)  /* Bit 3:  UART Two Stop Bits Select */
 #define UART_LCRH_FEN              (1 << 4)  /* Bit 4:  UART Enable FIFOs */
 #define UART_LCRH_WLEN_SHIFT       5         /* Bits 6-5: UART Word Length */
+
 #define UART_LCRH_WLEN_MASK        (3 << UART_LCRH_WLEN_SHIFT)
 #  define UART_LCRH_WLEN_5BITS     (0 << UART_LCRH_WLEN_SHIFT) /* 5-bits (reset) */
 #  define UART_LCRH_WLEN_6BITS     (1 << UART_LCRH_WLEN_SHIFT) /* 6-bits */
 #  define UART_LCRH_WLEN_7BITS     (2 << UART_LCRH_WLEN_SHIFT) /* 7-bits */
 #  define UART_LCRH_WLEN_8BITS     (3 << UART_LCRH_WLEN_SHIFT) /* 8-bits */
+
 #define UART_LCRH_SPS              (1 << 7)  /* Bit 7:  UART Stick Parity Select */
 
 /* UART Control (CTL) */
@@ -194,18 +196,19 @@
 
 #define UART_IFLS_TXIFLSEL_SHIFT   0         /* Bits 0-2: UART Transmit Interrupt FIFO Level Select */
 #define UART_IFLS_TXIFLSEL_MASK    (7 << UART_IFLS_TXIFLSEL_SHIFT)
-#  define UART_IFLS_TXIFLSEL_18th  (0 << UART_IFLS_TXIFLSEL_SHIFT) /* 1/8th full */
-#  define UART_IFLS_TXIFLSEL_14th  (1 << UART_IFLS_TXIFLSEL_SHIFT) /* 1/4th full */
-#  define UART_IFLS_TXIFLSEL_half  (2 << UART_IFLS_TXIFLSEL_SHIFT) /* half full */
-#  define UART_IFLS_TXIFLSEL_34th  (3 << UART_IFLS_TXIFLSEL_SHIFT) /* 3/4th full */
-#  define UART_IFLS_TXIFLSEL_78th  (4 << UART_IFLS_TXIFLSEL_SHIFT) /* 7/8th full */
+#  define UART_IFLS_TXIFLSEL_18TH  (0 << UART_IFLS_TXIFLSEL_SHIFT) /* 1/8th full */
+#  define UART_IFLS_TXIFLSEL_14TH  (1 << UART_IFLS_TXIFLSEL_SHIFT) /* 1/4th full */
+#  define UART_IFLS_TXIFLSEL_HALF  (2 << UART_IFLS_TXIFLSEL_SHIFT) /* half full */
+#  define UART_IFLS_TXIFLSEL_34TH  (3 << UART_IFLS_TXIFLSEL_SHIFT) /* 3/4th full */
+#  define UART_IFLS_TXIFLSEL_78TH  (4 << UART_IFLS_TXIFLSEL_SHIFT) /* 7/8th full */
+
 #define UART_IFLS_RXIFLSEL_SHIFT   3         /* Bits 3-5: UART Receive Interrupt FIFO Level Select */
 #define UART_IFLS_RXIFLSEL_MASK    (7 << UART_IFLS_RXIFLSEL_SHIFT)
-#  define UART_IFLS_RXIFLSEL_18th  (0 << UART_IFLS_RXIFLSEL_SHIFT) /* 1/8th full */
-#  define UART_IFLS_RXIFLSEL_14th  (1 << UART_IFLS_RXIFLSEL_SHIFT) /* 1/4th full */
-#  define UART_IFLS_RXIFLSEL_half  (2 << UART_IFLS_RXIFLSEL_SHIFT) /* half full */
-#  define UART_IFLS_RXIFLSEL_34th  (3 << UART_IFLS_RXIFLSEL_SHIFT) /* 3/4th full */
-#  define UART_IFLS_RXIFLSEL_78th  (4 << UART_IFLS_RXIFLSEL_SHIFT) /* 7/8th full */
+#  define UART_IFLS_RXIFLSEL_18TH  (0 << UART_IFLS_RXIFLSEL_SHIFT) /* 1/8th full */
+#  define UART_IFLS_RXIFLSEL_14TH  (1 << UART_IFLS_RXIFLSEL_SHIFT) /* 1/4th full */
+#  define UART_IFLS_RXIFLSEL_HALF  (2 << UART_IFLS_RXIFLSEL_SHIFT) /* half full */
+#  define UART_IFLS_RXIFLSEL_34TH  (3 << UART_IFLS_RXIFLSEL_SHIFT) /* 3/4th full */
+#  define UART_IFLS_RXIFLSEL_78TH  (4 << UART_IFLS_RXIFLSEL_SHIFT) /* 7/8th full */
 
 /* UART Interrupt Mask (IM) */
 
@@ -269,8 +272,4 @@
  * Public Data
  ************************************************************************************/
 
-/************************************************************************************
- * Public Functions
- ************************************************************************************/
-
 #endif /* __ARCH_ARM_SRC_TIVA_HARDWARE_CC13X20_CC26X2_CC13X20_CC26X2_UART_H */

arch/arm/src/tiva/hardware/lm/lm_uart.h

@@ -402,11 +402,13 @@
 #define UART_LCRH_STP2             (1 << 3)  /* Bit 3:  UART Two Stop Bits Select */
 #define UART_LCRH_FEN              (1 << 4)  /* Bit 4:  UART Enable FIFOs */
 #define UART_LCRH_WLEN_SHIFT       5         /* Bits 6-5: UART Word Length */
+
 #define UART_LCRH_WLEN_MASK        (3 << UART_LCRH_WLEN_SHIFT)
 #  define UART_LCRH_WLEN_5BITS     (0 << UART_LCRH_WLEN_SHIFT) /* 5-bits (reset) */
 #  define UART_LCRH_WLEN_6BITS     (1 << UART_LCRH_WLEN_SHIFT) /* 6-bits */
 #  define UART_LCRH_WLEN_7BITS     (2 << UART_LCRH_WLEN_SHIFT) /* 7-bits */
 #  define UART_LCRH_WLEN_8BITS     (3 << UART_LCRH_WLEN_SHIFT) /* 8-bits */
+
 #define UART_LCRH_SPS              (1 << 7)  /* Bit 7:  UART Stick Parity Select */
 
 /* UART Control (CTL) */
@@ -422,18 +424,19 @@
 
 #define UART_IFLS_TXIFLSEL_SHIFT   0         /* Bits 2-0: UART Transmit Interrupt FIFO Level Select */
 #define UART_IFLS_TXIFLSEL_MASK    (7 << UART_IFLS_TXIFLSEL_SHIFT)
-#  define UART_IFLS_TXIFLSEL_18th  (0 << UART_IFLS_TXIFLSEL_SHIFT) /* 1/8th full */
-#  define UART_IFLS_TXIFLSEL_14th  (1 << UART_IFLS_TXIFLSEL_SHIFT) /* 1/4th full */
-#  define UART_IFLS_TXIFLSEL_half  (2 << UART_IFLS_TXIFLSEL_SHIFT) /* half full */
-#  define UART_IFLS_TXIFLSEL_34th  (3 << UART_IFLS_TXIFLSEL_SHIFT) /* 3/4th full */
-#  define UART_IFLS_TXIFLSEL_78th  (4 << UART_IFLS_TXIFLSEL_SHIFT) /* 7/8th full */
+#  define UART_IFLS_TXIFLSEL_18TH  (0 << UART_IFLS_TXIFLSEL_SHIFT) /* 1/8th full */
+#  define UART_IFLS_TXIFLSEL_14TH  (1 << UART_IFLS_TXIFLSEL_SHIFT) /* 1/4th full */
+#  define UART_IFLS_TXIFLSEL_HALF  (2 << UART_IFLS_TXIFLSEL_SHIFT) /* half full */
+#  define UART_IFLS_TXIFLSEL_34TH  (3 << UART_IFLS_TXIFLSEL_SHIFT) /* 3/4th full */
+#  define UART_IFLS_TXIFLSEL_78TH  (4 << UART_IFLS_TXIFLSEL_SHIFT) /* 7/8th full */
+
 #define UART_IFLS_RXIFLSEL_SHIFT   3         /* Bits 5-3: UART Receive Interrupt FIFO Level Select */
 #define UART_IFLS_RXIFLSEL_MASK    (7 << UART_IFLS_RXIFLSEL_SHIFT)
-#  define UART_IFLS_RXIFLSEL_18th  (0 << UART_IFLS_RXIFLSEL_SHIFT) /* 1/8th full */
-#  define UART_IFLS_RXIFLSEL_14th  (1 << UART_IFLS_RXIFLSEL_SHIFT) /* 1/4th full */
-#  define UART_IFLS_RXIFLSEL_half  (2 << UART_IFLS_RXIFLSEL_SHIFT) /* half full */
-#  define UART_IFLS_RXIFLSEL_34th  (3 << UART_IFLS_RXIFLSEL_SHIFT) /* 3/4th full */
-#  define UART_IFLS_RXIFLSEL_78th  (4 << UART_IFLS_RXIFLSEL_SHIFT) /* 7/8th full */
+#  define UART_IFLS_RXIFLSEL_18TH  (0 << UART_IFLS_RXIFLSEL_SHIFT) /* 1/8th full */
+#  define UART_IFLS_RXIFLSEL_14TH  (1 << UART_IFLS_RXIFLSEL_SHIFT) /* 1/4th full */
+#  define UART_IFLS_RXIFLSEL_HALF  (2 << UART_IFLS_RXIFLSEL_SHIFT) /* half full */
+#  define UART_IFLS_RXIFLSEL_34TH  (3 << UART_IFLS_RXIFLSEL_SHIFT) /* 3/4th full */
+#  define UART_IFLS_RXIFLSEL_78TH  (4 << UART_IFLS_RXIFLSEL_SHIFT) /* 7/8th full */
 
 /* UART Interrupt Mask (IM) */
 
@@ -531,8 +534,4 @@
  * Public Data
  ************************************************************************************/
 
-/************************************************************************************
- * Public Functions
- ************************************************************************************/
-
 #endif /* __ARCH_ARM_SRC_TIVA_HARDWARE_LM_LM_UART_H */

arch/arm/src/tiva/hardware/tm4c/tm4c_uart.h

@@ -492,11 +492,13 @@
 #define UART_LCRH_STP2             (1 << 3)  /* Bit 3:  UART Two Stop Bits Select */
 #define UART_LCRH_FEN              (1 << 4)  /* Bit 4:  UART Enable FIFOs */
 #define UART_LCRH_WLEN_SHIFT       5         /* Bits 6-5: UART Word Length */
+
 #define UART_LCRH_WLEN_MASK        (3 << UART_LCRH_WLEN_SHIFT)
 #  define UART_LCRH_WLEN_5BITS     (0 << UART_LCRH_WLEN_SHIFT) /* 5-bits (reset) */
 #  define UART_LCRH_WLEN_6BITS     (1 << UART_LCRH_WLEN_SHIFT) /* 6-bits */
 #  define UART_LCRH_WLEN_7BITS     (2 << UART_LCRH_WLEN_SHIFT) /* 7-bits */
 #  define UART_LCRH_WLEN_8BITS     (3 << UART_LCRH_WLEN_SHIFT) /* 8-bits */
+
 #define UART_LCRH_SPS              (1 << 7)  /* Bit 7:  UART Stick Parity Select */
 
 /* UART Control (CTL) */
@@ -526,18 +528,19 @@
 
 #define UART_IFLS_TXIFLSEL_SHIFT   0         /* Bits 2-0: UART Transmit Interrupt FIFO Level Select */
 #define UART_IFLS_TXIFLSEL_MASK    (7 << UART_IFLS_TXIFLSEL_SHIFT)
-#  define UART_IFLS_TXIFLSEL_18th  (0 << UART_IFLS_TXIFLSEL_SHIFT) /* 1/8th full */
-#  define UART_IFLS_TXIFLSEL_14th  (1 << UART_IFLS_TXIFLSEL_SHIFT) /* 1/4th full */
-#  define UART_IFLS_TXIFLSEL_half  (2 << UART_IFLS_TXIFLSEL_SHIFT) /* half full */
-#  define UART_IFLS_TXIFLSEL_34th  (3 << UART_IFLS_TXIFLSEL_SHIFT) /* 3/4th full */
-#  define UART_IFLS_TXIFLSEL_78th  (4 << UART_IFLS_TXIFLSEL_SHIFT) /* 7/8th full */
+#  define UART_IFLS_TXIFLSEL_18TH  (0 << UART_IFLS_TXIFLSEL_SHIFT) /* 1/8th full */
+#  define UART_IFLS_TXIFLSEL_14TH  (1 << UART_IFLS_TXIFLSEL_SHIFT) /* 1/4th full */
+#  define UART_IFLS_TXIFLSEL_HALF  (2 << UART_IFLS_TXIFLSEL_SHIFT) /* half full */
+#  define UART_IFLS_TXIFLSEL_34TH  (3 << UART_IFLS_TXIFLSEL_SHIFT) /* 3/4th full */
+#  define UART_IFLS_TXIFLSEL_78TH  (4 << UART_IFLS_TXIFLSEL_SHIFT) /* 7/8th full */
+
 #define UART_IFLS_RXIFLSEL_SHIFT   3         /* Bits 5-3: UART Receive Interrupt FIFO Level Select */
 #define UART_IFLS_RXIFLSEL_MASK    (7 << UART_IFLS_RXIFLSEL_SHIFT)
-#  define UART_IFLS_RXIFLSEL_18th  (0 << UART_IFLS_RXIFLSEL_SHIFT) /* 1/8th full */
-#  define UART_IFLS_RXIFLSEL_14th  (1 << UART_IFLS_RXIFLSEL_SHIFT) /* 1/4th full */
-#  define UART_IFLS_RXIFLSEL_half  (2 << UART_IFLS_RXIFLSEL_SHIFT) /* half full */
-#  define UART_IFLS_RXIFLSEL_34th  (3 << UART_IFLS_RXIFLSEL_SHIFT) /* 3/4th full */
-#  define UART_IFLS_RXIFLSEL_78th  (4 << UART_IFLS_RXIFLSEL_SHIFT) /* 7/8th full */
+#  define UART_IFLS_RXIFLSEL_18TH  (0 << UART_IFLS_RXIFLSEL_SHIFT) /* 1/8th full */
+#  define UART_IFLS_RXIFLSEL_14TH  (1 << UART_IFLS_RXIFLSEL_SHIFT) /* 1/4th full */
+#  define UART_IFLS_RXIFLSEL_HALF  (2 << UART_IFLS_RXIFLSEL_SHIFT) /* half full */
+#  define UART_IFLS_RXIFLSEL_34TH  (3 << UART_IFLS_RXIFLSEL_SHIFT) /* 3/4th full */
+#  define UART_IFLS_RXIFLSEL_78TH  (4 << UART_IFLS_RXIFLSEL_SHIFT) /* 7/8th full */
 
 /* UART Interrupt Mask (IM) */
 
@@ -731,8 +734,4 @@
  * Public Data
  ************************************************************************************/
 
-/************************************************************************************
- * Public Functions
- ************************************************************************************/
-
 #endif /* __ARCH_ARM_SRC_TIVA_HARDWARE_TM4C_TM4C_UART_H */

arch/arm/src/tms570/tms570_serial.c

@@ -282,7 +282,9 @@ static inline void tms570_serialout(struct tms570_dev_s *priv, int offset,
 static inline void tms570_restoresciint(struct tms570_dev_s *priv,
                                         uint32_t ints)
 {
-  /* Restore the previous interrupt state (assuming all interrupts disabled) */
+  /* Restore the previous interrupt state (assuming all interrupts
+   * disabled)
+   */
 
   tms570_serialout(priv, TMS570_SCI_SETINT_OFFSET, ints);
 }
@@ -364,9 +366,10 @@ static void tms570_shutdown(struct uart_dev_s *dev)
  *   the setup() method is called, however, the serial console may operate in
  *   a non-interrupt driven mode during the boot phase.
  *
- *   RX and TX interrupts are not enabled when by the attach method (unless the
- *   hardware supports multiple levels of interrupt enabling).  The RX and TX
- *   interrupts are not enabled until the txint() and rxint() methods are called.
+ *   RX and TX interrupts are not enabled when by the attach method (unless
+ *   the hardware supports multiple levels of interrupt enabling).  The RX
+ *   and TX interrupts are not enabled until the txint() and rxint() methods
+ *   are called.
  *
  ****************************************************************************/
 
@@ -395,8 +398,8 @@ static int tms570_attach(struct uart_dev_s *dev)
  *
  * Description:
  *   Detach SCI interrupts.  This method is called when the serial port is
- *   closed normally just before the shutdown method is called.  The exception
- *   is the serial console which is never shutdown.
+ *   closed normally just before the shutdown method is called.  The
+ *   exception is the serial console which is never shutdown.
  *
  ****************************************************************************/
 
@@ -435,7 +438,8 @@ static int tms570_interrupt(int irq, void *context, FAR void *arg)
        * INVECT0 register clears the corresponding INTFLAG.
        */
 
-      intvec = tms570_serialin(priv, TMS570_SCI_INTVECT0_OFFSET) & SCI_INTVECT_MASK;
+      intvec = tms570_serialin(priv, TMS570_SCI_INTVECT0_OFFSET) & \
+               SCI_INTVECT_MASK;
 
       /* Handle the pending interrupt */
 
@@ -445,6 +449,7 @@ static int tms570_interrupt(int irq, void *context, FAR void *arg)
             return OK;
 
           case SCI_INTVECT_WAKEUP:  /* Wake-up interrupt */
+
             /* SCI sets the WAKEUP flag if bus activity on the RX line
              * either prevents power-down mode from being entered, or RX
              * line activity causes an exit from power-down mode. If
@@ -480,7 +485,9 @@ static int tms570_interrupt(int irq, void *context, FAR void *arg)
 
           case SCI_INTVECT_TX:      /* Tranmit interrupt */
             {
-              /* Transmit data register available ... process outgoing bytes */
+              /* Transmit data register available ...
+               * process outgoing bytes
+               */
 
               uart_xmitchars(dev);
             }
@@ -551,10 +558,6 @@ static int tms570_ioctl(struct file *filep, int cmd, unsigned long arg)
             break;
           }
 
-        /* Return baud */
-
-        cfsetispeed(termiosp, priv->config.baud);
-
         /* Return parity */
 
         termiosp->c_cflag = ((priv->config.parity != 0) ? PARENB : 0) |
@@ -564,6 +567,10 @@ static int tms570_ioctl(struct file *filep, int cmd, unsigned long arg)
 
         termiosp->c_cflag |= (priv->config.stopbits2) ? CSTOPB : 0;
 
+        /* Return baud */
+
+        cfsetispeed(termiosp, priv->config.baud);
+
         /* Return number of bits */
 
         switch (priv->config.bits)
@@ -728,8 +735,8 @@ static void tms570_rxint(struct uart_dev_s *dev, bool enable)
 
   if (enable)
     {
-      /* Receive an interrupt when their is anything in the Rx data register (or an Rx
-       * timeout occurs).
+      /* Receive an interrupt when their is anything in the Rx data register
+       * (or an RX timeout occurs).
        */
 
 #ifndef CONFIG_SUPPRESS_SERIAL_INTS
@@ -753,7 +760,8 @@ static void tms570_rxint(struct uart_dev_s *dev, bool enable)
 static bool tms570_rxavailable(struct uart_dev_s *dev)
 {
   struct tms570_dev_s *priv = (struct tms570_dev_s *)dev->priv;
-  return ((tms570_serialin(priv, TMS570_SCI_FLR_OFFSET) & SCI_FLR_RXRDY) != 0);
+  return ((tms570_serialin(priv, TMS570_SCI_FLR_OFFSET) & \
+          SCI_FLR_RXRDY) != 0);
 }
 
 /****************************************************************************
@@ -821,7 +829,8 @@ static void tms570_txint(struct uart_dev_s *dev, bool enable)
 static bool tms570_txready(struct uart_dev_s *dev)
 {
   struct tms570_dev_s *priv = (struct tms570_dev_s *)dev->priv;
-  return ((tms570_serialin(priv, TMS570_SCI_FLR_OFFSET) & SCI_FLR_TXRDY) != 0);
+  return ((tms570_serialin(priv, TMS570_SCI_FLR_OFFSET) & \
+          SCI_FLR_TXRDY) != 0);
 }
 
 /****************************************************************************
@@ -835,7 +844,8 @@ static bool tms570_txready(struct uart_dev_s *dev)
 static bool tms570_txempty(struct uart_dev_s *dev)
 {
   struct tms570_dev_s *priv = (struct tms570_dev_s *)dev->priv;
-  return ((tms570_serialin(priv, TMS570_SCI_FLR_OFFSET) & SCI_FLR_TXEMPTY) != 0);
+  return ((tms570_serialin(priv, TMS570_SCI_FLR_OFFSET) & \
+          SCI_FLR_TXEMPTY) != 0);
 }
 
 /****************************************************************************

arch/mips/src/mips32/Kconfig

@@ -58,7 +58,7 @@ config MIPS32_TOOLCHAIN_MICROCHIPOPENL
 
 config MIPS32_TOOLCHAIN_PINGUINOW
 	bool "Pinguino mips-elf toolchain under Windows"
-	depends on TOOLCHAIN_WINDOWS || WINDOWS_UBUNTU
+	depends on TOOLCHAIN_WINDOWS
 	select CYGWIN_WINTOOL if WINDOWS_CYGWIN
 	select ARCH_TOOLCHAIN_GNU
 

arch/renesas/src/Makefile

@@ -96,16 +96,16 @@ endif
 # Add the builtin library
 
 EXTRA_LIBS += -lgcc
-EXTRA_LIBPATHS += -L "${dir ${shell $(CC) $(ARCHCPUFLAGS) --print-libgcc-file-name}}"
+EXTRA_LIBPATHS += -L"${shell dirname "`$(CC) $(ARCHCPUFLAGS) --print-libgcc-file-name`"}"
 
 ifneq ($(CONFIG_LIBM),y)
   EXTRA_LIBS += -lm
-  EXTRA_LIBPATHS += -L "${dir ${shell $(CC) $(ARCHCPUFLAGS) --print-file-name=libm.a}}"
+  EXTRA_LIBPATHS += -L"${shell dirname "`$(CC) $(ARCHCPUFLAGS) --print-file-name=libm.a`"}"
 endif
 
 ifeq ($(CONFIG_CXX_LIBSUPCXX),y)
   EXTRA_LIBS += -lsupc++
-  EXTRA_LIBPATHS += -L "${dir ${shell $(CC) $(ARCHCPUFLAGS) --print-file-name=libsupc++.a}}"
+  EXTRA_LIBPATHS += -L"${shell dirname "`$(CC) $(ARCHCPUFLAGS) --print-file-name=libsupc++.a`"}"
 endif
 
 VPATH = chip:common

arch/sim/Kconfig

@@ -99,7 +99,7 @@ endchoice
 
 config SIM_WALLTIME
 	bool "Run the simulation at a fixed cadence in near real-time"
-	default n
+	default y
 
 if SIM_WALLTIME
 choice
@@ -134,10 +134,9 @@ endif
 config SIM_NETDEV
 	bool "Simulated Network Device"
 	default y
-	depends on NET_ETHERNET
 	select ARCH_HAVE_NETDEV_STATISTICS
 	select SCHED_LPWORK
-	select SIM_WALLTIME
+	depends on (NET_ETHERNET && SIM_WALLTIME)
 	---help---
 		Build in support for a simulated network device.
 
@@ -226,7 +225,7 @@ config SIM_X11FB
 	bool "Use X11 window"
 	default n
 	select SCHED_LPWORK
-	select SIM_WALLTIME
+	depends on SIM_WALLTIME
 	---help---
 		Use an X11 graphics window to simulate the graphics device"
 
@@ -498,7 +497,7 @@ config SIM_QSPIFLASH_PAGESIZE
 config SIM_HCISOCKET
 	bool "Attach Host Bluetooth"
 	default false
-	depends on (WIRELESS_BLUETOOTH && HOST_LINUX)
+	depends on (WIRELESS_BLUETOOTH && HOST_LINUX && SIM_WALLTIME)
 	---help---
 		Attached the local bluetooth device to the simulation
 		target via HCI_CHANNEL_USER. This gives NuttX full

arch/sim/include/arch.h

@@ -40,6 +40,14 @@
 #ifndef __ARCH_SIM_INCLUDE_ARCH_H
 #define __ARCH_SIM_INCLUDE_ARCH_H
 
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
 /****************************************************************************
  * Inline functions
  ****************************************************************************/
@@ -53,4 +61,29 @@ static inline uintptr_t sim_getsp(void)
   return (uintptr_t)__builtin_frame_address(0);
 }
 
+/****************************************************************************
+ * Public Types
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Function Prototypes
+ ****************************************************************************/
+
+#ifdef __cplusplus
+#define EXTERN extern "C"
+extern "C"
+{
+#else
+#define EXTERN extern
+#endif
+
+#undef EXTERN
+#ifdef __cplusplus
+}
+#endif
+
 #endif /* __ARCH_SIM_INCLUDE_ARCH_H */

arch/sim/src/Makefile

@@ -287,9 +287,11 @@ board/libboard$(LIBEXT):
 # Step 3 cheat the host there is no object to construct
 # Note: the destructor can be fixed in the same way.
 
-nuttx$(EXEEXT): libarch$(LIBEXT) board/libboard$(LIBEXT) $(LINKOBJS) $(HOSTOBJS)
-	$(Q) echo "LD:  nuttx$(EXEEXT)"
+nuttx-names.dat: nuttx-names.in
 	$(call PREPROCESS, nuttx-names.in, nuttx-names.dat)
+
+nuttx$(EXEEXT): libarch$(LIBEXT) board/libboard$(LIBEXT) $(LINKOBJS) $(HOSTOBJS) nuttx-names.dat
+	$(Q) echo "LD:  nuttx$(EXEEXT)"
 	$(Q) $(LD) -r $(LDLINKFLAGS) $(RELPATHS) $(EXTRA_LIBPATHS) -o nuttx.rel $(REQUIREDOBJS) $(LDSTARTGROUP) $(RELLIBS) $(EXTRA_LIBS) $(LDENDGROUP)
 	$(Q) $(OBJCOPY) --redefine-syms=nuttx-names.dat nuttx.rel
 	$(Q) $(CC) $(CCLINKFLAGS) -Wl,-verbose 2>&1 | \
@@ -305,7 +307,7 @@ nuttx$(EXEEXT): libarch$(LIBEXT) board/libboard$(LIBEXT) $(LINKOBJS) $(HOSTOBJS)
 
 # This is part of the top-level export target
 
-export_startup: board/libboard$(LIBEXT) up_head.o $(HOSTOBJS)
+export_startup: board/libboard$(LIBEXT) up_head.o $(HOSTOBJS) nuttx-names.dat
 	cp up_head.o $(HOSTOBJS) ${EXPORT_DIR}/startup
 	cp nuttx-names.dat ${EXPORT_DIR}/libs
 	echo main NXmain >> ${EXPORT_DIR}/libs/nuttx-names.dat

arch/sim/src/sim/up_internal.h

@@ -242,7 +242,6 @@ void sim_cpu0_start(void);
 void up_cpu_started(void);
 int up_cpu_paused(int cpu);
 struct tcb_s *up_this_task(void);
-int up_cpu_set_pause_handler(int irq);
 #endif
 
 /* up_oneshot.c *************************************************************/

arch/sim/src/sim/up_simsmp.c

@@ -123,6 +123,7 @@ static void *sim_idle_trampoline(void *arg)
 #ifdef CONFIG_SIM_WALLTIME
   uint64_t now = 0;
 #endif
+  sigset_t set;
   int ret;
 
   /* Set the CPU number for the CPU thread */
@@ -136,7 +137,14 @@ static void *sim_idle_trampoline(void *arg)
 
   /* Make sure the SIGUSR1 is not masked */
 
-  up_cpu_set_pause_handler(SIGUSR1);
+  sigemptyset(&set);
+  sigaddset(&set, SIGUSR1);
+
+  ret = pthread_sigmask(SIG_UNBLOCK, &set, NULL);
+  if (ret < 0)
+    {
+      return NULL;
+    }
 
   /* Let up_cpu_start() continue */
 
@@ -172,6 +180,28 @@ static void *sim_idle_trampoline(void *arg)
   return NULL;
 }
 
+/****************************************************************************
+ * Name: sim_handle_signal
+ *
+ * Description:
+ *   This is the SIGUSR signal handler.  It implements the core logic of
+ *   up_cpu_pause() on the thread of execution the simulated CPU.
+ *
+ * Input Parameters:
+ *   arg - Standard sigaction arguments
+ *
+ * Returned Value:
+ *   None
+ *
+ ****************************************************************************/
+
+static void sim_handle_signal(int signo, siginfo_t *info, void *context)
+{
+  int cpu = (int)((uintptr_t)pthread_getspecific(g_cpu_key));
+
+  up_cpu_paused(cpu);
+}
+
 /****************************************************************************
  * Public Functions
  ****************************************************************************/
@@ -193,6 +223,8 @@ static void *sim_idle_trampoline(void *arg)
 
 void sim_cpu0_start(void)
 {
+  struct sigaction act;
+  sigset_t set;
   int ret;
 
   g_cpu_thread[0] = pthread_self();
@@ -215,7 +247,26 @@ void sim_cpu0_start(void)
 
   /* Register the common signal handler for all threads */
 
-  up_cpu_set_pause_handler(SIGUSR1);
+  act.sa_sigaction = sim_handle_signal;
+  act.sa_flags     = SA_SIGINFO;
+  sigemptyset(&act.sa_mask);
+
+  ret = sigaction(SIGUSR1, &act, NULL);
+  if (ret < 0)
+    {
+      return;
+    }
+
+  /* Make sure the SIGUSR1 is not masked */
+
+  sigemptyset(&set);
+  sigaddset(&set, SIGUSR1);
+
+  ret = pthread_sigmask(SIG_UNBLOCK, &set, NULL);
+  if (ret < 0)
+    {
+      return;
+    }
 }
 
 /****************************************************************************

arch/sim/src/sim/up_smpsignal.c

@@ -46,32 +46,6 @@
 #include "sched/sched.h"
 #include "up_internal.h"
 
-/****************************************************************************
- * Private Functions
- ****************************************************************************/
-
-/****************************************************************************
- * Name: sim_cpupause_handler
- *
- * Description:
- *   This is the SIGUSR signal handler.  It implements the core logic of
- *   up_cpu_pause() on the thread of execution the simulated CPU.
- *
- * Input Parameters:
- *   irq - the interrupt number
- *   context  - not used
- *   arg      - not used
- *
- * Returned Value:
- *   In case of success OK (0) is returned otherwise a negative value.
- *
- ****************************************************************************/
-
-static int sim_cpupause_handler(int irq, FAR void *context, FAR void *arg)
-{
-  return up_cpu_paused(this_cpu());
-}
-
 /****************************************************************************
  * Public Functions
  ****************************************************************************/
@@ -230,22 +204,3 @@ struct tcb_s *up_this_task(void)
 {
   return this_task();
 }
-
-/****************************************************************************
- * Name: up_cpu_set_pause_handler
- *
- * Description:
- *   Attach the CPU pause request interrupt to the NuttX logic.
- *
- * Input Parameters:
- *   irq - the SIGUSR1 interrupt number
- *
- * Returned Value:
- *   On success returns OK (0), otherwise a negative value.
- ****************************************************************************/
-
-int up_cpu_set_pause_handler(int irq)
-{
-  up_enable_irq(irq);
-  return irq_attach(irq, sim_cpupause_handler, NULL);
-}

arch/x86/src/Makefile

@@ -74,7 +74,7 @@ OBJS = $(AOBJS) $(COBJS)
 
 LDSTARTGROUP ?= --start-group
 LDENDGROUP ?= --end-group
-LDFLAGS += $(ARCHSCRIPT)
+LDFLAGS += $(ARCHSCRIPT) -static
 
 BOARDMAKE = $(if $(wildcard board$(DELIM)Makefile),y,)
 

arch/xtensa/src/esp32/esp32_intdecode.c

@@ -60,7 +60,6 @@ static inline void xtensa_intclear(uint32_t mask)
 {
   __asm__ __volatile__
   (
-    "movi a2, 0\n"
     "wsr %0, INTCLEAR\n"
     : "=r"(mask) : :
   );

arch/xtensa/src/esp32/esp32_serial.c

@@ -845,10 +845,6 @@ static int esp32_ioctl(struct file *filep, int cmd, unsigned long arg)
             break;
           }
 
-        /* Return baud */
-
-        cfsetispeed(termiosp, priv->baud);
-
         /* Return parity */
 
         termiosp->c_cflag = ((priv->parity != 0) ? PARENB : 0) |
@@ -863,6 +859,10 @@ static int esp32_ioctl(struct file *filep, int cmd, unsigned long arg)
 #if defined(CONFIG_SERIAL_IFLOWCONTROL) || defined(CONFIG_SERIAL_OFLOWCONTROL)
         termiosp->c_cflag |= (priv->flowc) ? (CCTS_OFLOW | CRTS_IFLOW): 0;
 #endif
+        /* Return baud */
+
+        cfsetispeed(termiosp, priv->baud);
+
         /* Return number of bits */
 
         switch (priv->bits)

boards/arm/cxd56xx/common/src/cxd56_gs2200m.c

@@ -112,35 +112,18 @@ static int gs2200m_irq_attach(xcpt_t handler, FAR void *arg)
 
 static void gs2200m_irq_enable(void)
 {
-  irqstate_t flags = spin_lock_irqsave();
+  irqstate_t flags = enter_critical_section();
 
   wlinfo("== ec:%d called=%d \n", _enable_count, _n_called++);
 
   if (0 == _enable_count)
     {
-#ifdef CONFIG_SMP
-      bool unlock = false;
-
-      if (0 != up_cpu_index())
-        {
-          unlock = true;
-          spin_unlock_irqrestore(flags);
-        }
-#endif
-
       cxd56_gpioint_enable(PIN_UART2_CTS);
-
-#ifdef CONFIG_SMP
-      if (unlock)
-        {
-          flags = spin_lock_irqsave();
-        }
-#endif
     }
 
   _enable_count++;
 
-  spin_unlock_irqrestore(flags);
+  leave_critical_section(flags);
 }
 
 /****************************************************************************
@@ -149,7 +132,7 @@ static void gs2200m_irq_enable(void)
 
 static void gs2200m_irq_disable(void)
 {
-  irqstate_t flags = spin_lock_irqsave();
+  irqstate_t flags = enter_critical_section();
 
   wlinfo("== ec:%d called=%d \n", _enable_count, _n_called++);
 
@@ -157,27 +140,10 @@ static void gs2200m_irq_disable(void)
 
   if (0 == _enable_count)
     {
-#ifdef CONFIG_SMP
-      bool unlock = false;
-
-      if (0 != up_cpu_index())
-        {
-          unlock = true;
-          spin_unlock_irqrestore(flags);
-        }
-#endif
-
       cxd56_gpioint_disable(PIN_UART2_CTS);
-
-#ifdef CONFIG_SMP
-      if (unlock)
-        {
-          flags = spin_lock_irqsave();
-        }
-#endif
     }
 
-  spin_unlock_irqrestore(flags);
+  leave_critical_section(flags);
 }
 
 /****************************************************************************
@@ -186,7 +152,7 @@ static void gs2200m_irq_disable(void)
 
 static uint32_t gs2200m_dready(int *ec)
 {
-  irqstate_t flags = spin_lock_irqsave();
+  irqstate_t flags = enter_critical_section();
 
   uint32_t r = cxd56_gpio_read(PIN_UART2_CTS);
 
@@ -197,7 +163,7 @@ static uint32_t gs2200m_dready(int *ec)
       *ec = _enable_count;
     }
 
-  spin_unlock_irqrestore(flags);
+  leave_critical_section(flags);
   return r;
 }
 

boards/arm/cxd56xx/spresense/scripts/Make.defs

@@ -35,7 +35,7 @@
 
 include $(TOPDIR)/.config
 include $(TOPDIR)/tools/Config.mk
-include $(TOPDIR)/boards/arm/cxd56xx/spresense/scripts/Config.mk
+include $(TOPDIR)/tools/cxd56/Config.mk
 include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs
 
 # Setup for the kind of memory that we are executing from

boards/arm/imx6/sabre-6quad/README.txt

@@ -592,24 +592,7 @@ Debugging with QEMU
 
 The nuttx ELF image can be debugged with QEMU.
 
-1. Before debugging, following change (enabling wfi instruction in up_idle)
-   is recommended to reduce CPU usage on host PC.
-
-diff --git a/arch/arm/src/common/up_idle.c b/arch/arm/src/common/up_idle.c
-index 45fab0b7c6..c54c1178a1 100644
---- a/arch/arm/src/common/up_idle.c
-+++ b/arch/arm/src/common/up_idle.c
-@@ -71,7 +71,7 @@ void up_idle(void)
-
-   /* Sleep until an interrupt occurs to save power */
-
--#if 0
-+#if 1
-   asm("WFI");  /* For example */
- #endif
- #endif
-
-2. Also, to debug the nuttx (ELF) with symbols, following change must
+1. To debug the nuttx (ELF) with symbols, following change must
    be applied to defconfig.
 
 diff --git a/boards/arm/imx6/sabre-6quad/configs/nsh/defconfig b/boards/arm/imx6/sabre-6quad/configs/nsh/defconfig
@@ -624,6 +607,33 @@ index b15becbb51..3ad4d13ad7 100644
 +CONFIG_DEBUG_SYMBOLS=y
  CONFIG_DEV_ZERO=y
 
+2. Please note that QEMU does not report PL310 (L2CC) related
+   registers correctly, so if you enable CONFIG_DEBUG_ASSERTION
+   the nuttx will stop with DEBUGASSERT(). To avoid this,
+   comment out the following lines.
+
+--- a/arch/arm/src/armv7-a/arm_l2cc_pl310.c
++++ b/arch/arm/src/armv7-a/arm_l2cc_pl310.c
+@@ -333,7 +333,7 @@ void arm_l2ccinitialize(void)
+ #if defined(CONFIG_ARMV7A_ASSOCIATIVITY_8WAY)
+   DEBUGASSERT((getreg32(L2CC_ACR) & L2CC_ACR_ASS) == 0);
+ #elif defined(CONFIG_ARMV7A_ASSOCIATIVITY_16WAY)
+- DEBUGASSERT((getreg32(L2CC_ACR) & L2CC_ACR_ASS) == L2CC_ACR_ASS);
++ //DEBUGASSERT((getreg32(L2CC_ACR) & L2CC_ACR_ASS) == L2CC_ACR_ASS);
+ #else
+ # error No associativity selected
+ #endif
+@@ -345,8 +345,8 @@ void arm_l2ccinitialize(void)
+   DEBUGASSERT((getreg32(L2CC_ACR) & L2CC_ACR_WAYSIZE_MASK) ==
+               L2CC_ACR_WAYSIZE_32KB);
+ #elif defined(CONFIG_ARMV7A_WAYSIZE_64KB)
+- DEBUGASSERT((getreg32(L2CC_ACR) & L2CC_ACR_WAYSIZE_MASK) ==
+- L2CC_ACR_WAYSIZE_64KB);
++ // DEBUGASSERT((getreg32(L2CC_ACR) & L2CC_ACR_WAYSIZE_MASK) ==
++ // L2CC_ACR_WAYSIZE_64KB);
+ #elif defined(CONFIG_ARMV7A_WAYSIZE_128KB)
+   DEBUGASSERT((getreg32(L2CC_ACR) & L2CC_ACR_WAYSIZE_MASK) ==
+               L2CC_ACR_WAYSIZE_128KB);
 
 3. Run QEMU
 
@@ -691,58 +701,7 @@ Open Issues:
    This will cause the interrupt handlers on other CPUs to spin until
    leave_critical_section() is called.  More verification is needed.
 
-2. Cache Concurrency.  Cache coherency in SMP configurations is managed by the
-   MPCore snoop control unit (SCU).  But I don't think I have the set up
-   correctly yet.
-
-   Currently cache inconsistencies appear to be the root cause of all current SMP
-   issues.  SMP works as expected if the caches are disabled, but otherwise there
-   are problems (usually hangs):
-
-   This will disable the caches:
-
-diff --git a/arch/arm/src/armv7-a/arm_head.S b/arch/arm/src/armv7-a/arm_head.S
-index 27c2a5b..2a6274c 100644
---- a/arch/arm/src/armv7-a/arm_head.S
-+++ b/arch/arm/src/armv7-a/arm_head.S
-@@ -454,6 +454,7 @@ __start:
-         * after SMP cache coherency has been setup.
-         */
-
-+#if 0 // REMOVE ME
- #if !defined(CPU_DCACHE_DISABLE) && !defined(CONFIG_SMP)
-        /* Dcache enable
-         *
-@@ -471,6 +472,7 @@ __start:
-
-        orr             r0, r0, #(SCTLR_I)
- #endif
-+#endif // REMOVE ME
-
- #ifdef CPU_ALIGNMENT_TRAP
-        /* Alignment abort enable
-diff --git a/arch/arm/src/armv7-a/arm_scu.c b/arch/arm/src/armv7-a/arm_scu.c
-index eedf179..1db2092 100644
---- a/arch/arm/src/armv7-a/arm_scu.c
-+++ b/arch/arm/src/armv7-a/arm_scu.c
-@@ -156,6 +156,7 @@ static inline void arm_set_actlr(uint32_t actlr)
-
- void arm_enable_smp(int cpu)
- {
-+#if 0 // REMOVE ME
-   uint32_t regval;
-
-   /* Handle actions unique to CPU0 which comes up first */
-@@ -222,6 +223,7 @@ void arm_enable_smp(int cpu)
-   regval  = arm_get_sctlr();
-   regval |= SCTLR_C;
-   arm_set_sctlr(regval);
-+#endif // REMOVE ME
- }
-
- #endif
-
-3. Recent redesigns to SMP of another ARMv7-M platform have made changes to the OS
+2. Recent redesigns to SMP of another ARMv7-M platform have made changes to the OS
    SMP support.  There are no known problem but the changes have not been verified
    fully (see STATUS above for 2019-02-06).
 

boards/arm/imx6/sabre-6quad/configs/nsh/defconfig

@@ -17,14 +17,21 @@ CONFIG_ARCH_INTERRUPTSTACK=2048
 CONFIG_ARCH_IRQBUTTONS=y
 CONFIG_ARCH_LOWVECTORS=y
 CONFIG_ARCH_STACKDUMP=y
+CONFIG_ARMV7A_ASSOCIATIVITY_16WAY=y
+CONFIG_ARMV7A_L2CC_PL310=y
+CONFIG_ARMV7A_WAYSIZE_64KB=y
 CONFIG_BOARD_LOOPSPERMSEC=99369
 CONFIG_BOOT_RUNFROMSDRAM=y
 CONFIG_BUILTIN=y
+CONFIG_CLOCK_MONOTONIC=y
+CONFIG_DEBUG_FULLOPT=y
+CONFIG_DEBUG_SYMBOLS=y
 CONFIG_DEV_ZERO=y
+CONFIG_EXAMPLES_HELLO=y
+CONFIG_EXPERIMENTAL=y
 CONFIG_FS_PROCFS=y
 CONFIG_HAVE_CXX=y
 CONFIG_HAVE_CXXINITIALIZE=y
-CONFIG_HOST_WINDOWS=y
 CONFIG_IMX6_UART1=y
 CONFIG_IMX_DDR_SIZE=1073741824
 CONFIG_INTELHEX_BINARY=y
@@ -34,6 +41,8 @@ CONFIG_NSH_ARCHINIT=y
 CONFIG_NSH_BUILTIN_APPS=y
 CONFIG_NSH_FILEIOSIZE=512
 CONFIG_NSH_READLINE=y
+CONFIG_PL310_LOCKDOWN_BY_LINE=y
+CONFIG_PL310_LOCKDOWN_BY_MASTER=y
 CONFIG_PREALLOC_TIMERS=4
 CONFIG_RAMLOG=y
 CONFIG_RAMLOG_BUFSIZE=16384
@@ -42,13 +51,17 @@ CONFIG_RAM_SIZE=1073741824
 CONFIG_RAM_START=0x10000000
 CONFIG_RAM_VSTART=0x10000000
 CONFIG_RAW_BINARY=y
+CONFIG_READLINE_CMD_HISTORY=y
 CONFIG_RR_INTERVAL=200
 CONFIG_SCHED_HPWORK=y
 CONFIG_SCHED_HPWORKPRIORITY=192
 CONFIG_SCHED_WAITPID=y
+CONFIG_STACK_COLORATION=y
 CONFIG_START_MONTH=3
 CONFIG_START_YEAR=2016
 CONFIG_SYMTAB_ORDEREDBYNAME=y
 CONFIG_SYSTEM_NSH=y
+CONFIG_TESTING_GETPRIME=y
+CONFIG_TESTING_OSTEST=y
 CONFIG_UART1_SERIAL_CONSOLE=y
 CONFIG_USER_ENTRYPOINT="nsh_main"

boards/arm/imx6/sabre-6quad/configs/smp/defconfig

@@ -17,18 +17,22 @@ CONFIG_ARCH_INTERRUPTSTACK=2048
 CONFIG_ARCH_IRQBUTTONS=y
 CONFIG_ARCH_LOWVECTORS=y
 CONFIG_ARCH_STACKDUMP=y
+CONFIG_ARMV7A_ASSOCIATIVITY_16WAY=y
+CONFIG_ARMV7A_L2CC_PL310=y
+CONFIG_ARMV7A_WAYSIZE_64KB=y
 CONFIG_BOARD_LOOPSPERMSEC=99369
 CONFIG_BOOT_RUNFROMSDRAM=y
 CONFIG_BUILTIN=y
+CONFIG_CLOCK_MONOTONIC=y
 CONFIG_DEBUG_FULLOPT=y
 CONFIG_DEBUG_SYMBOLS=y
 CONFIG_DEV_ZERO=y
 CONFIG_DRIVER_NOTE=y
 CONFIG_EXAMPLES_HELLO=y
+CONFIG_EXPERIMENTAL=y
 CONFIG_FS_PROCFS=y
 CONFIG_HAVE_CXX=y
 CONFIG_HAVE_CXXINITIALIZE=y
-CONFIG_HOST_WINDOWS=y
 CONFIG_IMX6_UART1=y
 CONFIG_IMX_DDR_SIZE=1073741824
 CONFIG_INTELHEX_BINARY=y
@@ -37,6 +41,8 @@ CONFIG_NSH_ARCHINIT=y
 CONFIG_NSH_BUILTIN_APPS=y
 CONFIG_NSH_FILEIOSIZE=512
 CONFIG_NSH_READLINE=y
+CONFIG_PL310_LOCKDOWN_BY_LINE=y
+CONFIG_PL310_LOCKDOWN_BY_MASTER=y
 CONFIG_PREALLOC_TIMERS=4
 CONFIG_RAMLOG=y
 CONFIG_RAMLOG_BUFSIZE=16384
@@ -45,18 +51,21 @@ CONFIG_RAM_SIZE=1073741824
 CONFIG_RAM_START=0x10000000
 CONFIG_RAM_VSTART=0x10000000
 CONFIG_RAW_BINARY=y
+CONFIG_READLINE_CMD_HISTORY=y
 CONFIG_RR_INTERVAL=200
 CONFIG_SCHED_HPWORK=y
 CONFIG_SCHED_HPWORKPRIORITY=192
 CONFIG_SCHED_INSTRUMENTATION=y
 CONFIG_SMP=y
 CONFIG_SPINLOCK_IRQ=y
+CONFIG_STACK_COLORATION=y
 CONFIG_START_MONTH=3
 CONFIG_START_YEAR=2016
 CONFIG_SYMTAB_ORDEREDBYNAME=y
 CONFIG_SYSTEM_NSH=y
 CONFIG_SYSTEM_SYSTEM=y
 CONFIG_SYSTEM_TASKSET=y
+CONFIG_TESTING_GETPRIME=y
 CONFIG_TESTING_OSTEST=y
 CONFIG_TESTING_OSTEST_FPUTESTDISABLE=y
 CONFIG_TESTING_SMP=y

boards/arm/lc823450/lc823450-xgevk/configs/rndis/defconfig

@@ -16,6 +16,7 @@ CONFIG_ARCH_BOARD_LC823450_XGEVK=y
 CONFIG_ARCH_CHIP="lc823450"
 CONFIG_ARCH_CHIP_LC823450=y
 CONFIG_ARCH_INTERRUPTSTACK=2048
+CONFIG_ARCH_STACKDUMP=y
 CONFIG_ARCH_STDARG_H=y
 CONFIG_AUDIO=y
 CONFIG_AUDIO_BUFFER_NUMBYTES=1024
@@ -116,8 +117,6 @@ CONFIG_NSH_DISABLE_DIRNAME=y
 CONFIG_NSH_DISABLE_EXEC=y
 CONFIG_NSH_DISABLE_GET=y
 CONFIG_NSH_DISABLE_LOSETUP=y
-CONFIG_NSH_DISABLE_MB=y
-CONFIG_NSH_DISABLE_MH=y
 CONFIG_NSH_DISABLE_MKFIFO=y
 CONFIG_NSH_DISABLE_MKRD=y
 CONFIG_NSH_DISABLE_PUT=y
@@ -167,6 +166,7 @@ CONFIG_SMP=y
 CONFIG_SMP_NCPUS=2
 CONFIG_SPI=y
 CONFIG_SPINLOCK_IRQ=y
+CONFIG_STACK_COLORATION=y
 CONFIG_START_DAY=3
 CONFIG_START_MONTH=10
 CONFIG_START_YEAR=2013

boards/arm/stm32/stm32f4discovery/configs/wifi/defconfig

@@ -5,7 +5,6 @@
 # You can then do "make savedefconfig" to generate a new defconfig file that includes your
 # modifications.
 #
-# CONFIG_ARCH_FPU is not set
 # CONFIG_MMCSD_HAVE_CARDDETECT is not set
 # CONFIG_MMCSD_HAVE_WRITEPROTECT is not set
 # CONFIG_NSH_ARGCAT is not set
@@ -19,7 +18,9 @@ CONFIG_ARCH_BUTTONS=y
 CONFIG_ARCH_CHIP="stm32"
 CONFIG_ARCH_CHIP_STM32=y
 CONFIG_ARCH_CHIP_STM32F407VG=y
+CONFIG_ARCH_INTERRUPTSTACK=2048
 CONFIG_ARCH_STACKDUMP=y
+CONFIG_ARMV7M_LAZYFPU=y
 CONFIG_BOARDCTL_RESET=y
 CONFIG_BOARD_LOOPSPERMSEC=16717
 CONFIG_BUILTIN=y
@@ -101,6 +102,7 @@ CONFIG_SYSTEM_NSH_SYMTAB_ARRAYNAME="g_symtab"
 CONFIG_SYSTEM_NSH_SYMTAB_COUNTNAME="g_nsymbols"
 CONFIG_SYSTEM_NTPC=y
 CONFIG_TESTING_OSTEST=y
+CONFIG_TESTING_OSTEST_FPUSIZE=132
 CONFIG_USART2_RXBUFSIZE=128
 CONFIG_USART2_SERIAL_CONSOLE=y
 CONFIG_USART2_TXBUFSIZE=128

boards/arm/stm32l4/b-l475e-iot01a/README.txt

@@ -190,14 +190,14 @@ Configurations
   Each  B-L475E-IOT01A configuration is maintained in a sub-directory and
   can be selected as follow:
 
-    tools/configure.sh [-l|c|u|n] /b-l475e-iot01a:<subdir>
+    tools/configure.sh [-l|c|n] /b-l475e-iot01a:<subdir>
 
   Where:
    -l selects the Linux (l) host environment.  The [-c|u|n] options
        select one of the Windows environments.  Default:  Use host setup
        in the defconfig file
-   [-c|u|n] selects the Windows host and a Windows environment:  Cygwin (c),
-       Ubuntu under Windows 10 (u), or Windows native (n).  Default Cygwin
+   [-c|n] selects the Windows host and a Windows environment:
+      Cygwin (c), or Windows native (n). Default Cygwin
 
   Before building, make sure that:
 

boards/renesas/rx65n/rx65n-grrose/configs/ipv6/defconfig

@@ -1,74 +1,62 @@
-CONFIG_ARCH_BOARD_RX65N_GRROSE=y
+#
+# This file is autogenerated: PLEASE DO NOT EDIT IT.
+#
+# You can use "make menuconfig" to make any modifications to the installed .config file.
+# You can then do "make savedefconfig" to generate a new defconfig file that includes your
+# modifications.
+#
+# CONFIG_NET_IPv4 is not set
+CONFIG_ARCH="renesas"
 CONFIG_ARCH_BOARD="rx65n-grrose"
+CONFIG_ARCH_BOARD_RX65N_GRROSE=y
+CONFIG_ARCH_CHIP="rx65n"
 CONFIG_ARCH_CHIP_R5F565NEHDFP=y
+CONFIG_ARCH_INTERRUPTSTACK=1024
 CONFIG_ARCH_RENESAS=y
 CONFIG_ARCH_STACKDUMP=y
-CONFIG_ARCH="renesas"
-CONFIG_ARCH_CHIP="rx65n"
 CONFIG_BOARD_LOOPSPERMSEC=15001
-CONFIG_MOTOROLA_SREC=y
-CONFIG_ENDIAN_LITTLE=y
-CONFIG_SYSTEM_NSH=y
-CONFIG_MAX_TASKS=8
-CONFIG_DEBUG_FEATURES=y
-CONFIG_ARCH_INTERRUPTSTACK=1024
 CONFIG_BUILTIN=y
-CONFIG_ETH0_PHY_LAN8720A=y
+CONFIG_DEBUG_FEATURES=y
+CONFIG_DEBUG_NET=y
+CONFIG_EXAMPLES_SERIALBLASTER=y
+CONFIG_EXAMPLES_SERIALRX=y
+CONFIG_EXAMPLES_SERIALRX_PRINTSTR=y
+CONFIG_EXAMPLES_SERIALRX_PRIORITY=75
+CONFIG_FS_PROCFS=y
+CONFIG_FS_PROCFS_REGISTER=y
+CONFIG_MAX_TASKS=8
+CONFIG_MOTOROLA_SREC=y
 CONFIG_NET=y
-#CONFIG_NETDB_DNSCLIENT=y
-#CONFIG_NETDB_DNSSERVER_NOADDR=y
 CONFIG_NETDEV_PHY_IOCTL=y
 CONFIG_NETDEV_STATISTICS=y
-#CONFIG_NETUTILS_TFTPC=y
-#CONFIG_NETUTILS_WEBCLIENT=y
-#CONFIG_NET_ARP_SEND=y
+CONFIG_NETINIT_IPv6NETMASK_8=0xff80
+CONFIG_NETINIT_THREAD=y
 CONFIG_NET_BROADCAST=y
-#CONFIG_NET_ICMP=y
-#CONFIG_NET_ICMP_SOCKET=y
+CONFIG_NET_ICMPv6=y
+CONFIG_NET_ICMPv6_NEIGHBOR=y
+CONFIG_NET_ICMPv6_SOCKET=y
+CONFIG_NET_IPv6=y
+CONFIG_NET_MLD=y
 CONFIG_NET_SOCKOPTS=y
+CONFIG_NET_SOLINGER=y
 CONFIG_NET_STATISTICS=y
 CONFIG_NET_TCP=y
 CONFIG_NET_TCPBACKLOG=y
 CONFIG_NET_TCP_WRITE_BUFFERS=y
 CONFIG_NET_UDP=y
-CONFIG_NSH_BUILTIN_APPS=y
 CONFIG_NFILE_DESCRIPTORS=8
+CONFIG_NSH_BUILTIN_APPS=y
 CONFIG_NSH_FILEIOSIZE=512
 CONFIG_NSH_LINELEN=64
 CONFIG_NSH_READLINE=y
-CONFIG_NETINIT_MONITOR=y
-CONFIG_NETINIT_THREAD=y
-
-CONFIG_NETINIT_RETRYMSEC=2000
-CONFIG_NETINIT_SIGNO=18
-
 CONFIG_NUNGET_CHARS=0
 CONFIG_PREALLOC_TIMERS=0
 CONFIG_PTHREAD_STACK_DEFAULT=1024
 CONFIG_RAM_SIZE=655360
 CONFIG_RAM_START=0x00000000
 CONFIG_RAW_BINARY=y
-CONFIG_RX65N_SCI0=y
-CONFIG_RX65N_SCI1=y
-CONFIG_RX65N_SCI2=y
-CONFIG_RX65N_SCI5=y
-CONFIG_RX65N_SCI6=y
-CONFIG_RX65N_SCI8=y
-CONFIG_SCI0_SERIALDRIVER=y
-CONFIG_SCI0_BAUD=115200
-CONFIG_SCI1_SERIAL_CONSOLE=y
-CONFIG_SCI1_SERIALDRIVER=y
-CONFIG_SCI1_BAUD=115200
-CONFIG_SCI2_SERIALDRIVER=y
-CONFIG_SCI2_BAUD=115200
-CONFIG_SCI5_SERIALDRIVER=y
-CONFIG_SCI5_BAUD=921600
-CONFIG_SCI6_SERIALDRIVER=y
-CONFIG_SCI6_BAUD=115200
-CONFIG_SCI8_SERIALDRIVER=y
-CONFIG_SCI8_BAUD=115200
-CONFIG_RX65N_EMAC=y
 CONFIG_RX65N_EMAC0=y
+CONFIG_RX65N_EMAC0_PHYADDR=0
 CONFIG_RX65N_EMAC0_PHYSR=30
 CONFIG_RX65N_EMAC0_PHYSR_100FD=0x18
 CONFIG_RX65N_EMAC0_PHYSR_100HD=0x08
@@ -77,49 +65,16 @@ CONFIG_RX65N_EMAC0_PHYSR_10HD=0x04
 CONFIG_RX65N_EMAC0_PHYSR_ALTCONFIG=y
 CONFIG_RX65N_EMAC0_PHYSR_ALTMODE=0x1c
 CONFIG_RX65N_EMAC0_RMII=y
-CONFIG_RX65N_EMAC0_PHYADDR=0
-CONFIG_SCHED_WORKQUEUE=y
+CONFIG_RX65N_SCI0=y
 CONFIG_SCHED_HPWORK=y
 CONFIG_SCHED_LPWORK=y
+CONFIG_SCI1_SERIAL_CONSOLE=y
+CONFIG_SCI5_BAUD=921600
 CONFIG_SDCLONE_DISABLE=y
-#CONFIG_SYSTEM_PING=y
-CONFIG_ICU=y
 CONFIG_STDIO_DISABLE_BUFFERING=y
-CONFIG_TASK_NAME_SIZE=0
-CONFIG_USER_ENTRYPOINT="nsh_main"
-CONFIG_USERMAIN_STACKSIZE=1024
-CONFIG_IDLETHREAD_STACKSIZE=1024
-CONFIG_FS_PROCFS=y
-CONFIG_FS_PROCFS_REGISTER=y
-CONFIG_NET_ETH_PKTSIZE = 590
-CONFIG_RX65N_CMTW0=y
-CONFIG_RX65N_PERIB=y
-CONFIG_NETUTILS_DHCPC=y
-CONFIG_NETUTILS_DHCPD=y
-CONFIG_NSH_DHCPC=y
-CONFIG_NETINIT_DHCPC=y
-CONFIG_SYSTEM_DHCPC_RENEW=y
+CONFIG_SYSTEM_NSH=y
 CONFIG_SYSTEM_NSH_PRIORITY=50
-CONFIG_EXAMPLES_SERIALBLASTER=y
-CONFIG_EXAMPLES_SERIALBLASTER_STACKSIZE=2048
-CONFIG_EXAMPLES_SERIALBLASTER_PRIORITY=50
-CONFIG_EXAMPLES_SERIALBLASTER_DEVPATH="/dev/ttyS2"
-CONFIG_EXAMPLES_SERIALRX=y
-CONFIG_EXAMPLES_SERIALRX_STACKSIZE=2048
-CONFIG_EXAMPLES_SERIALRX_PRIORITY=75
-CONFIG_EXAMPLES_SERIALRX_BUFSIZE=11520
-CONFIG_EXAMPLES_SERIALRX_DEVPATH="/dev/ttyS0"
-CONFIG_EXAMPLES_SERIALRX_PRINTSTR=y
-CONFIG_DEBUG_NET=y
-
-# CONFIG_NET_IPv4 is not set
-CONFIG_NETINIT_IPv6NETMASK_8=0xff80
-CONFIG_NET_ICMPv6=y
-CONFIG_NET_ICMPv6_NEIGHBOR=y
-CONFIG_NET_ICMPv6_SOCKET=y
-CONFIG_NET_IPv6=y
 CONFIG_SYSTEM_PING6=y
-CONFIG_NET_MLD=y
-#CONFIG_NET_MCASTGROUP=y
-CONFIG_NET_SOLINGER=y
-
+CONFIG_TASK_NAME_SIZE=0
+CONFIG_USERMAIN_STACKSIZE=1024
+CONFIG_USER_ENTRYPOINT="nsh_main"

boards/renesas/rx65n/rx65n-rsk2mb/configs/ipv6/defconfig

@@ -1,60 +1,62 @@
+#
+# This file is autogenerated: PLEASE DO NOT EDIT IT.
+#
+# You can use "make menuconfig" to make any modifications to the installed .config file.
+# You can then do "make savedefconfig" to generate a new defconfig file that includes your
+# modifications.
+#
+# CONFIG_NET_IPv4 is not set
+CONFIG_ARCH="renesas"
+CONFIG_ARCH_BOARD="rx65n-rsk2mb"
 CONFIG_ARCH_BOARD_RX65N_RSK2MB=y
-CONFIG_ARCH_BOARD="rx65n"
+CONFIG_ARCH_CHIP="rx65n"
 CONFIG_ARCH_CHIP_R5F565NEHDFC=y
+CONFIG_ARCH_INTERRUPTSTACK=1024
 CONFIG_ARCH_RENESAS=y
 CONFIG_ARCH_STACKDUMP=y
-CONFIG_ARCH="renesas"
-CONFIG_ARCH_CHIP="rx65n"
 CONFIG_BOARD_LOOPSPERMSEC=15001
-CONFIG_MOTOROLA_SREC=y
-CONFIG_ENDIAN_LITTLE=y
-CONFIG_SYSTEM_NSH=y
-CONFIG_MAX_TASKS=8
-CONFIG_DEBUG_FEATURES=y
-CONFIG_ARCH_INTERRUPTSTACK=1024
 CONFIG_BUILTIN=y
-CONFIG_ETH0_PHY_DP83620=y
+CONFIG_DEBUG_FEATURES=y
+CONFIG_DEBUG_NET=y
+CONFIG_EXAMPLES_SERIALBLASTER=y
+CONFIG_EXAMPLES_SERIALRX=y
+CONFIG_EXAMPLES_SERIALRX_PRINTSTR=y
+CONFIG_EXAMPLES_SERIALRX_PRIORITY=75
+CONFIG_FS_PROCFS=y
+CONFIG_FS_PROCFS_REGISTER=y
+CONFIG_MAX_TASKS=8
+CONFIG_MOTOROLA_SREC=y
 CONFIG_NET=y
-#CONFIG_NETDB_DNSCLIENT=y
-#CONFIG_NETDB_DNSSERVER_NOADDR=y
 CONFIG_NETDEV_PHY_IOCTL=y
 CONFIG_NETDEV_STATISTICS=y
-#CONFIG_NETUTILS_TFTPC=y
-#CONFIG_NETUTILS_WEBCLIENT=y
-#CONFIG_NET_ARP_SEND=y
+CONFIG_NETINIT_IPv6NETMASK_8=0xff80
+CONFIG_NETINIT_THREAD=y
 CONFIG_NET_BROADCAST=y
-#CONFIG_NET_ICMP=y
-#CONFIG_NET_ICMP_SOCKET=y
+CONFIG_NET_ICMPv6=y
+CONFIG_NET_ICMPv6_NEIGHBOR=y
+CONFIG_NET_ICMPv6_SOCKET=y
+CONFIG_NET_IPv6=y
+CONFIG_NET_MLD=y
 CONFIG_NET_SOCKOPTS=y
+CONFIG_NET_SOLINGER=y
 CONFIG_NET_STATISTICS=y
 CONFIG_NET_TCP=y
 CONFIG_NET_TCPBACKLOG=y
 CONFIG_NET_TCP_WRITE_BUFFERS=y
 CONFIG_NET_UDP=y
-CONFIG_NSH_BUILTIN_APPS=y
 CONFIG_NFILE_DESCRIPTORS=8
+CONFIG_NSH_BUILTIN_APPS=y
 CONFIG_NSH_FILEIOSIZE=512
 CONFIG_NSH_LINELEN=64
 CONFIG_NSH_READLINE=y
-CONFIG_NETINIT_MONITOR=y
-CONFIG_NETINIT_THREAD=y
-
-CONFIG_NETINIT_RETRYMSEC=2000
-CONFIG_NETINIT_SIGNO=18
-
 CONFIG_NUNGET_CHARS=0
 CONFIG_PREALLOC_TIMERS=0
 CONFIG_PTHREAD_STACK_DEFAULT=1024
 CONFIG_RAM_SIZE=262144
 CONFIG_RAM_START=0x00000000
 CONFIG_RAW_BINARY=y
-CONFIG_SCI2_SERIALDRIVER=y
-CONFIG_RX65N_SCI2=y
-CONFIG_SCI8_SERIALDRIVER=y
-CONFIG_SCI8_SERIAL_CONSOLE=y
-CONFIG_RX65N_SCI8=y
-CONFIG_RX65N_EMAC=y
 CONFIG_RX65N_EMAC0=y
+CONFIG_RX65N_EMAC0_PHYADDR=30
 CONFIG_RX65N_EMAC0_PHYSR=30
 CONFIG_RX65N_EMAC0_PHYSR_100FD=0x4
 CONFIG_RX65N_EMAC0_PHYSR_100HD=0x0
@@ -62,48 +64,16 @@ CONFIG_RX65N_EMAC0_PHYSR_10FD=0x6
 CONFIG_RX65N_EMAC0_PHYSR_10HD=0x2
 CONFIG_RX65N_EMAC0_PHYSR_ALTCONFIG=y
 CONFIG_RX65N_EMAC0_PHYSR_ALTMODE=0x6
-CONFIG_RX65N_EMAC0_MII=y
-CONFIG_RX65N_EMAC0_PHYADDR=30
-CONFIG_SCHED_WORKQUEUE=y
+CONFIG_RX65N_SCI2=y
+CONFIG_RX65N_SCI8=y
 CONFIG_SCHED_HPWORK=y
 CONFIG_SCHED_LPWORK=y
+CONFIG_SCI8_SERIAL_CONSOLE=y
 CONFIG_SDCLONE_DISABLE=y
-#CONFIG_SYSTEM_PING=y
-CONFIG_ICU=y
 CONFIG_STDIO_DISABLE_BUFFERING=y
-CONFIG_TASK_NAME_SIZE=0
-CONFIG_USER_ENTRYPOINT="nsh_main"
-CONFIG_USERMAIN_STACKSIZE=1024
-CONFIG_FS_PROCFS=y
-CONFIG_FS_PROCFS_REGISTER=y
-CONFIG_NET_ETH_PKTSIZE = 590
-CONFIG_RX65N_CMTW0=y
-CONFIG_RX65N_PERIB=y
-CONFIG_NETUTILS_DHCPC=y
-CONFIG_NETUTILS_DHCPD=y
-CONFIG_NSH_DHCPC=y
-CONFIG_NETINIT_DHCPC=y
+CONFIG_SYSTEM_NSH=y
 CONFIG_SYSTEM_NSH_PRIORITY=50
-CONFIG_EXAMPLES_SERIALBLASTER=y
-CONFIG_EXAMPLES_SERIALBLASTER_STACKSIZE=2048
-CONFIG_EXAMPLES_SERIALBLASTER_PRIORITY=50
-CONFIG_EXAMPLES_SERIALBLASTER_DEVPATH="/dev/ttyS2"
-CONFIG_EXAMPLES_SERIALRX=y
-CONFIG_EXAMPLES_SERIALRX_STACKSIZE=2048
-CONFIG_EXAMPLES_SERIALRX_PRIORITY=75
-CONFIG_EXAMPLES_SERIALRX_BUFSIZE=11520
-CONFIG_EXAMPLES_SERIALRX_DEVPATH="/dev/ttyS0"
-CONFIG_EXAMPLES_SERIALRX_PRINTSTR=y
-CONFIG_DEBUG_NET=y
-
-# CONFIG_NET_IPv4 is not set
-CONFIG_NETINIT_IPv6NETMASK_8=0xff80
-CONFIG_NET_ICMPv6=y
-CONFIG_NET_ICMPv6_NEIGHBOR=y
-CONFIG_NET_ICMPv6_SOCKET=y
-CONFIG_NET_IPv6=y
 CONFIG_SYSTEM_PING6=y
-CONFIG_NET_MLD=y
-#CONFIG_NET_MCASTGROUP=y
-CONFIG_NET_SOLINGER=y
-
+CONFIG_TASK_NAME_SIZE=0
+CONFIG_USERMAIN_STACKSIZE=1024
+CONFIG_USER_ENTRYPOINT="nsh_main"