Added support for using timers with ADCs. Updated Kconfig to support TRGO2, although driver support for TRGO and TRGO2 not developed yet. Updated hardware/stm32_tim.h with missing CCER bits needed for compilation.
Changed the LLVM architecture type from thumbv7 to thumbv7a in
Toolchain.defs to better match the ARMv7-A architecture specification.
This change ensures proper code generation and optimization for
Cortex-A series processors when using the Thumb instruction set.
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
Added LLVM-specific configuration variables to ARM architecture CMake files:
- LLVM_ARCHTYPE for architecture variant (thumbv6m, thumbv7a, etc)
- LLVM_CPUTYPE for CPU target (cortex-m0, cortex-a5, etc)
- LLVM_ABITYPE for ABI (eabi/eabihf)
These changes enable LLVM/Clang toolchain support while maintaining
compatibility with existing GCC configurations. The LLVM variables
are set based on the same architecture/CPU/FPU configurations used
for GCC flags.
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
Reformatted the FPU options table to use a clearer markdown-style table format
with proper alignment and column headers. Added visual separators (~~~) to make
the table stand out from surrounding code. Improved consistency in column widths
and fixed line wrapping for better readability.
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
Used the STM32H7 as a reference.
Removed APB enabling from stm32h5xx_rcc.c. This is done in timer initialization, like STM32H7.
Also removed LPTIM. Will add later.
tim_lowerhalf: Timers 9, 10, and 11 removed. Timers 15,16, and 17 added.
Removed low-power timers from Kconfig. Not implemented yet.
Style Updates
Added stm32_tim_enable and stm32_tim_disable to Timer operations.
This commit cleans up redundant header file includes throughout the codebase.
The changes include:
- Removing duplicate #include directives that were present in the same file
- Consolidating includes that were split across multiple lines unnecessarily
- Removing unused includes that were no longer needed
- Fixing some formatting issues with includes
The changes improve code organization and maintainability by:
- Reducing unnecessary dependencies
- Making include dependencies more explicit
- Following consistent include patterns
- Removing dead code
No functional changes are made - this is purely a code cleanup commit.
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
Raise compilation error when I2C configuration is invalid.
It's better to catch invalid clock configuration during compilation instead of
producing binary that doesn't work as expected anyway.
Signed-off-by: raiden00pl <raiden00@railab.me>
In the file stm32g474xxxx_rcc.c, the enable PLL
code, according to the intent of the comment,
wants to keep the reserved bit, but the code
clears the reserved bit.
Signed-off-by: jerryslhao <jerryslhao@gmail.com>
Adding source files to the fdcan branch based on identical register set. These files should mostly just work.
Removed references to FDCAN3. H5 only has 2 FDCAN interfaces.
Add basic FDCAN Kconfig
FDCAN Kconfig options
Added various options for FDCAN mode, FDCAN bitrate, clock selection and division, and timing.
Added bit timing config options (nominal and data). Added stm32h56xxx pin mappings.
Fixed Data Bit Timing. Pulled in STM32H5_FDCAN_PDIV_VALUE. Added stm32_fdcan.c to Make.defs. Added DBITRATE to Kconfig
Clock source changes to FDCAN
Moved the setting of the clock source to the stm32h5xx_rcc.c file. Added notes to stm32_fdcan.c that STM32_FDCAN_FREQUENCY and STM32_FDCAN_PDIV should be set in board.h
Change STM32H5_FDCAN_PDIV to STM32_FDCAN_PDIV
Updated Kconfig to match G4 implementation. Removed stm32_fdcan_sock for now.
Removed FDCAN3 from stm32_fdcan.h
incomplete changes for bit timning
Set NBRP and DBRP registers based on STM32H7 FDCAN socket algorithm.
Added board file for initializing 1 can device. Will update later to initialize second device.
Fixed ifdefs. Changed STM32 to STM32H5.
Add some can testing changes.
Added option to configure bit timing, with automatic bit timing set as default.
Style fixes
Fixed FDCAN2 and memory access issues
FDCAN2 msgram offset was wrong by 1 word (4 bytes). I removed the + 4 at the end of the definition. This fixed the issues with fdcan2. Also changed ifdefs when setting ESI, FDF, and BRS bits. When CAN FD was used, this resulted in the first command after the endif (the setting of dest at line 2325) being skipped because it was included in the else block when it shouldn't have. This resulted in exceptions. Adjust ifdefs fixes this problem. Other minor fixes.
Restoring board files to upstream versions. These files will be pulled in later in a separate pull request. stm32h5_fdcan_test branch created for this.
Fixed Queue Mode Transmit
The can driver checks the TFFL bits in the TXFQS register. In Queue mode, this always returns 0. As a result, fdcan_txempty was always returning false, which resulted in no transmissions. This code fixes that.
Add stm32h5 fdcan chardriver to Make.defs
Inline & inline_function both used make confuze, let's modify all inline
in irq.h to inline_function, also clear the always_inline_funcion
declaration.
Signed-off-by: buxiasen <buxiasen@xiaomi.com>
Register addresses are defined. Bit defintions are still needed.
Bitmaps for OCTOSPI peripheral register
Incremental updates to qspi files
Redefined QSPI/OCTOSPI registers for STM32H5
Fixed register definitions for the STM32H5. However, more work still needs to be done. Some bits that shared registers on the STM32H7 have different register locations on the H5. This still needs to be accounted for.
Fixed more differences vs STM32H7 qspi
Added ifdef for including stm32_dma.h in stm32_qspi.c. Added stm32_qspi.c to Make.defs.
Register fixes. SPI activity but not able to format device yet.
Fixed DCYC mask
Set HCLK frequency to correct value. Undid ccrconfig debug.
Tested Interrupt Mode (single SPI). Added alternate bytes to meminfo and cmdinfo structures. Updated Kconfig variables for STM32H5.
Fixed base register in hardware/stm32_qspi.h. Updated qspi_dumpregs.
The base register was previously set to STM32_QUADSPI_BASE, changed to the correctly named STM32_OCTOSPI1_BASE. However, these defines for the OCTOSPI registers are not even used. Instead qspi_putreg and qspi_getreg utilize the priv->base value to access OCTOSPI registers.
Removed altbytes code, left as before. Moved QSPI clock selection to stm32h5xx_rcc.c
Changed STM32H5_QUADSPI to STM32H5_QSPI1
Added hook to define QSPI_CLK_FREQUENCY as STM32_QSPI_FREQUENCY from board.h
Removed changes to nuttx qspi.h
style fixes
chip/efm32_leserial.c: In function 'efm32_restoreuartint':
Error: chip/efm32_leserial.c:329:37: error: 'len' undeclared (first use in this function); did you mean 'ien'?
329 | efm32_restoreuartint_nolock(priv, len);
| ^~~
| ien
Signed-off-by: hujun5 <hujun5@xiaomi.com>
There were two simple errors when running ci tests on pull #15351. These errors were unrelated to that pull. After investigating I found two simple errors. 1. The len variable was likely a typo that should have been the function argument, ien. 2. The spinlock_t lock was defined in a section dependent on CONFIG_SERIAL_TERMIOS. However, the spinlock_t lock was used in code that did not require the SERIAL_TERMIOS config. Therefore errors resulted.
imxrt_edma_s missing lock variable
CI build tests noted that the variable g_edma was referencing a lock variable that did not exist in the structure. This change adds that missing lock as a spinlock_t type.
Remove unused flags variable from imxrt_dmach_stop
Removed extra =
Fixed comments and indent
Add commit log to OCTOSPI HW PR
Summary
hardware/stm32_qspi.h - Defines for the STM32H5 QSPI driver. The peripheral on the STM32H5 is actually an OCTOSPI peripheral, however it was decided to use it as a QSPI peripheral for the following reasons:
There is currently support for QSPI within Nuttx.
The STM32H7 QSPI register set is very similar to the STM32H5 OCTOSPI register set and the STM32H7 series has an existing QSPI driver.
OCTOSPI devices are rare as of now and are not part of our use case.
hardware/stm32h56xxx_pinmap.h - Added pin mappings for OCTOSPI GPIOs.
Impact
This change will not impact any architectures outside of the STM32H5 series. Even for the STM32H5 series, these changes will only have an impact if they are utilized.
Testing
No testing yet for these files other than ensuring that we can still build Nuttx. Further testing will be documented in a future pull request when the STM32H5 QSPI driver is added.
