Commit 313d6df7 caused the following build error:
CC: fixedmath/lib_b16atan2.c chip/sam_qspi.c: In function 'qspi_memory':
chip/sam_qspi.c:1552:7: warning: implicit declaration of function 'IS_ALIGNED' [-Wimplicit-function-declaration]
1552 | IS_ALIGNED((uintptr_t)meminfo->buffer, 4) &&
| ^~~~~~~~~~
In file included from chip/sam_qspi.c:41:
chip/sam_qspi.c: In function 'qspi_alloc':
chip/sam_qspi.c:1591:21: warning: implicit declaration of function 'ALIGN_UP' [-Wimplicit-function-declaration]
1591 | return kmm_malloc(ALIGN_UP(buflen, 4));
This was caused by missing include of nuttx.h header defining ALIGN_UP
and IS_ALIGNED.
Signed-off-by: Michal Lenc <michallenc@seznam.cz>
Add --no-warn-rwx-segments in case of RAM boot mode to linker to
suppress the below warning:
"nuttx has a LOAD segment with RWX permissions"
Signed-off-by: Jinliang Li <lijinliang1@lixiang.com>
Summary
add memory map for DDR region
fix arm-v7a/knsh boot dataabort on arm_addrenv_utils.c first time memset
after arm_pgvaddr.
Signed-off-by: qinwei1 <qinwei1@xiaomi.com>
that pr requires chip turn on CONFIG_DRIVERS_BLUETOOTH to use bluetooth,
but not all defconig enable this option, so let's map bt_driver_register
to bt_netdev_register in header file in this case, and revert the unnessary
change in the related chip and board folders.
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
When sig dispatch do up_schedule_sigaction, need to make a new frame to
run arm_sigdeliver. But the exception_direct cannot handle xcp.regs as
we are using c-function exception handler.
Need to use exception_common to handle SMP call.
Signed-off-by: buxiasen <buxiasen@xiaomi.com>
Implement PIC loading in armv8-m qemu,
for example: load address-independent AP ELF in the bootloader,
and the text segment in AP ELF is XIP,
no need to apply for memory and modify it.
Two config:
bootloader abbreviation bl:
use romfs to load ap elf, use the boot command to parse and jump to ap
application abbreviation ap:
run os test
We need to compile ap first, then compile bl.
compile step:
./tools/configure.sh mps3-an547:ap
make -j20
mkdir -p pic
cp boot pic/.
genromfs -a 128 -f ../romfs.img -d pic
make distclean -j20
./tools/configure.sh mps3-an547:bl
make -j20
run qemu:
qemu-system-arm -M mps3-an547 -m 2G -nographic -kernel nuttx.bin \
-gdb tcp::1127 -device loader,file=../romfs.img,addr=0x60000000
nsh> boot /etc/boot
ap> ostest
Signed-off-by: anjiahao <anjiahao@xiaomi.com>
Need to start up a new to setup special registers use
`arm_pic_setupxcp`.
Note that CONFIG_BUILD_PIC compiles the entire NuttX image
as position-independent(PIC), enable CONFIG_PIC to load PIC
application code.
Signed-off-by: anjiahao <anjiahao@xiaomi.com>
Added a flash driver for the STM32G4 series. The primary change here is
the addition of stm32g4xxx_flash.c. This file uses the STM32L4 flash
driver as a template. The primary difference is the accounting for dual
banks with different page sizes.
Fixed error while building b-g474e-dpow1/buckboost. It was possible (technically) to have page be used uninitialzied. Changing the if statement to default to using a flash_page_size == 2048 fixes this issue.
In armv8m the FPSCR[18:16] LTPSIZE field must be set to 0b100 for
"Tail predication not applied" as it's reset value.
Signed-off-by: zhangyuan29 <zhangyuan29@xiaomi.com>
Summary:
1. Support armv7-a armv7-r armv8-r
2. The NSACR is read-only in Non-secure PL1 and PL2 modes.
3. The NSACR is read/write in Secure PL1 modes.
4. When the NSACR.{CP11,CP10} bit is set to 1,
Non-secure access to coprocessor 11,10 enable
Signed-off-by: wangming9 <wangming9@xiaomi.com>
Signed-off-by: lipengfei28 <lipengfei28@xiaomi.com>
Summary:
Add the default CPU frequency configuration.
Signed-off-by: wangming9 <wangming9@xiaomi.com>
Signed-off-by: lipengfei28 <lipengfei28@xiaomi.com>
toolchain file variable is global scope
dont need set parent scope
clear warning:
CMake Warning (dev) at /github/workspace/sources/nuttx/arch/arm/src/cmake/gcc.cmake:69 (set):
Cannot set "GCCVER": current scope has no parent.
Call Stack (most recent call first):
/github/workspace/sources/nuttx/arch/arm/src/cmake/Toolchain.cmake:56 (include)
/github/workspace/sources/nuttx/build/CMakeFiles/3.26.0/CMakeSystem.cmake:6 (include)
/github/workspace/sources/nuttx/build/CMakeFiles/CMakeScratch/TryCompile-ZJVOZO/CMakeLists.txt:5 (project)
This warning is for project developers. Use -Wno-dev to suppress it.
Signed-off-by: xuxin19 <xuxin19@xiaomi.com>
1. The -c parameter should not be added during the link phase, otherwise the link will fail.
2. If it is the clang compiler, its toolchain library should use --print-file-name to find it, otherwise an error will occur
Signed-off-by: wangmingrong1 <wangmingrong1@xiaomi.com>
When neon is enabled, compiler may optimize 64bits access to vstr, that
will cause data aborts.
Split 64bits access to double 32bits access for GIC_IROUTER/GICR_TYPER,
just like linux.
Signed-off-by: Jinliang Li <lijinliang1@lixiang.com>
Signed-off-by: chao an <anchao@lixiang.com>
Need to save the regs firstly in case syslog triggers another crash.
Otherwise we may loose the register contents for the first exception.
Signed-off-by: xuxingliang <xuxingliang@xiaomi.com>
1. Add config CONFIG_ARMV7A_GICv2_DUMP to control gic dump,
because irqinfo introduce too much other log;
2. Change the log api from irqinfo() to syslog(), syslog not
append the function name in the log, so the gic dump format
will not be destoried.
Signed-off-by: Bowen Wang <wangbowen6@xiaomi.com>
1. add IS_ALIGNED() definitions for NuttX;
2. replace all the ALIGN_UP() and ALIGN_DOWN() to use common
align implementation;
Signed-off-by: Bowen Wang <wangbowen6@xiaomi.com>
When using alarm_arch implementation, 64-bit time can be returned. Using unsign long will cause precision loss.
Signed-off-by: yinshengkai <yinshengkai@xiaomi.com>
gprof can analyze code hot spots based on scheduled sampling.
After adding the "-pg" parameter when compiling, you can view the code call graph.
Signed-off-by: yinshengkai <yinshengkai@xiaomi.com>
Some app with same code runs on different cores in AMP mode,
need the physical core on which the function is called.
Signed-off-by: hujun5 <hujun5@xiaomi.com>
Signed-off-by: fangxinyong <fangxinyong@xiaomi.com>
This PR support Nested interrupt in armv6/7/8m:
There are two types of nested interrupt model:
Zero latency nested interrupt
Interrupt Priority Note
Data abort Highest
SVC 0x50
High irq1 0x60 ISR can't access system API
irq_save() 0x70
High irq2 0x80 ISR can't access system API
normal irq3 0xB0
We have already support this mode before this PR
Nested interrupt which interrupt level lower than up_irq_save()
Interrupt Priority Note
Data abort Highest
SVC 0x70
irq_save() 0x80
High irq1 0x90 ISR can access system API
High irq2 0xA0 ISR can access system API
normal irq3 0xB0
Now, this PR can support this mode
Signed-off-by: ligd <liguiding1@xiaomi.com>
reason:
To remove the "sync pause" and decouple the critical section from the dependency on enabling interrupts,
after that we need to further implement "schedlock + spinlock".
changelist
1 Modify the implementation of critical sections to no longer involve enabling interrupts or handling synchronous pause events.
2 GIC_SMP_CPUCALL attach to pause handler to remove arch interface up_cpu_paused_restore up_cpu_paused_save
3 Completely remove up_cpu_pause, up_cpu_resume, up_cpu_paused, and up_cpu_pausereq
4 change up_cpu_pause_async to up_send_cpu_sgi
Signed-off-by: hujun5 <hujun5@xiaomi.com>
1. Kconfig - Removed USART1 config option from STM32_STM32G47XX. Not necessary to adding LPUART functionality. 2. stm32_lowput.c - Added extra check from STM32G4 board because that is the only with LPUART functionality. 2. stm32_serial.c - Removed unneeded function (stm32_serial_get_lpuart). Fixed up_putc return bug. Added configuration for DMAMAP_LPUART RX and TX for STM32G4XXX only. The G4 is the only in this family with LPUART and uses a DMAMUX unlike the others.
1. Removed 1WIRE LPUART refereences in Kconfig and stm32_uart.h. There is no support for LPUART currently in stm32_1wire.c. 2. Removed references to LPUART under DMA_V2 ifdefs. STM32G4 uses DMA_V1, and I saw that none of the chips DMA_V2 (F20, F4) have LPUARTs. AFAIK the only chip in the stm32 folder that has LPUART peripherals is the STM32G4.
Removed unnecessary brackets and empty lines
Added lpuartnsh (LPUART NuttShell) config to the nucleo-g474re board configurations. nsh uses USART3 by default. lpuartnsh uses nsh as a template, changes the serial console to LPUART1, and adds the DMA configs to enable DMA for the LPUART.
Added support for using the lpuart prescaler register. Without prescaling the apbclock, 9600 baud is not supported on the G474RE. By utilizing the prescaler, when necessary, we can support nearly any baud rate (300 baud to 30M Mbaud). lowputc defaults to a prescaler of 16 for the lpuart so standard baud rates (9600 to 115200) are supported early in the boot process. Later in stm32_serial.c the ideal prescaler and BRR values are determined.
Added ifdef statements for LPUART code sections not compatible with other chips.
Changed LPUART BRR calcuation to use 64-bit integers.
Feedback from nuttx pull request. Added brackets around single line if/else statements. Reordered lpuartnsh defconfig file.
Fix lpuart brr calculation after attempting to break the calculation into 2 lines.
Removed TAB
reason:
In the kernel, we are planning to remove all occurrences of up_cpu_pause as one of the steps to
simplify the implementation of critical sections. The goal is to enable spin_lock_irqsave to encapsulate critical sections,
thereby facilitating the replacement of critical sections(big lock) with smaller spin_lock_irqsave(small lock)
Signed-off-by: hujun5 <hujun5@xiaomi.com>
read content of undefinedinsn address, and compare it with what it is in elf to check if there is a ram bit flip
Signed-off-by: liaoao <liaoao@xiaomi.com>
add_compile_options(--param asan-globals=1) is recognized as
--param-lasan-globals=1, which causes compilation exception:
Signed-off-by: W-M-R <Mike_0528@163.com>
1. refactor the ghs/gcc/clang/armclang toolchain management in CMake
2. unify the cmake toolchain naming style
3. support greenhills build procedure with CMake
4. add protect build for greenhills and gnu toolchain with CMake
Signed-off-by: guoshichao <guoshichao@xiaomi.com>
Summary:
Due to the modification of 4244610, the heap_size may be used on SRAM1, which can lead to misconfiguration problems for some mps qemu configurations (e.g.MPS3) that use extern DDR as the heap, refer to the previous issue VELAPLATFO-34555.
Signed-off-by: chenrun1 <chenrun1@xiaomi.com>
Signed-off-by: ligd <liguiding1@xiaomi.com>
Summary
MPS-521 support Dual Cortex-M33 and maybe suitable for AMP-like
case which is for AUTO OS, the change
1. add support for single core at msp-521 with nsh bringup
2. testing with ostest
TODO:
Dual core support for flat-build
Dual CORE support for Protected Build
Signed-off-by: qinwei1 <qinwei1@xiaomi.com>
Signed-off-by: ligd <liguiding1@xiaomi.com>
Summary
1. add Protected build Support for ARM MPS AN500
2. refine mps Memory layout configure and enable MPU support
Note
1. ostest for an547:nsh
2. ostest for an500:nsh and an500:knsh
Signed-off-by: qinwei1 <qinwei1@xiaomi.com>
Signed-off-by: ligd <liguiding1@xiaomi.com>
reason:
Currently, if we need to schedule a task to another CPU, we have to completely halt the other CPU,
manipulate the scheduling linked list, and then resume the operation of that CPU. This process is both time-consuming and unnecessary.
During this process, both the current CPU and the target CPU are inevitably subjected to busyloop.
The improved strategy is to simply send a cross-core interrupt to the target CPU.
The current CPU continues to run while the target CPU responds to the interrupt, eliminating the certainty of a busyloop occurring.
Signed-off-by: hujun5 <hujun5@xiaomi.com>
compile error:
Register: ostest
Register: nsh
Register: sh
Register: hello
Register: getprime
In file included from /home/hujun5/downloads1/vela_sim/nuttx/include/arch/irq.h:35,
from /home/hujun5/downloads1/vela_sim/nuttx/include/nuttx/irq.h:37,
from /home/hujun5/downloads1/vela_sim/nuttx/include/nuttx/sched.h:40,
from /home/hujun5/downloads1/vela_sim/nuttx/include/nuttx/arch.h:87,
from common/arm_signal_dispatch.c:26:
common/arm_signal_dispatch.c: In function 'up_signal_dispatch':
common/arm_signal_dispatch.c:72:3: error: 'asm' operand has impossible constraints
72 | sys_call4(SYS_signal_handler, (uintptr_t)sighand, (uintptr_t)signo,
| ^~~~~~~~~
make[1]: *** [Makefile:168：arm_signal_dispatch.o] error 1
Signed-off-by: hujun5 <hujun5@xiaomi.com>
reason:
when a context switch occurs, up_switch_context is executed.
In order to reduce the time taken for context switching,
we inline the up_switch_context function.
Signed-off-by: hujun5 <hujun5@xiaomi.com>
/vela/nuttx/drivers/pci/pci_ecam.c:432:(.text.pci_ecam_get_irq+0x16): undefined reference to `up_get_legacy_irq'
Signed-off-by: Yongrong Wang <wangyongrong@xiaomi.com>
reason:
Only one timer will be effective at a time.In the current
implementation of NuttX's timer handling, only a single global timer is necessary.
Having an excessive number of timers can lead to additional performance
overhead and logical errors, especially when operating in SMP
(Symmetric Multi-Processing) tickless mode.
Signed-off-by: hujun5 <hujun5@xiaomi.com>
for the citimon stats:
thread 0: thread 1:
enter_critical (t0)
up_switch_context
note suspend thread0 (t1)
thread running
IRQ happen, in ISR:
post thread0
up_switch_context
note resume thread0 (t2)
ISR continue f1
ISR continue f2
...
ISR continue fn
leave_critical (t3)
You will see, the thread 0, critical_section time is:
(t1 - t0) + (t3 - t2)
BUT, this result contains f1 f2 .. fn time spent, it is wrong
to tell user thead0 hold the critical lots of time but actually
not belong to it.
Resolve:
change the nxsched_suspend/resume_scheduler to real hanppends
Signed-off-by: ligd <liguiding1@xiaomi.com>
with other functionalities removed.
reason:
by doing this we can reduce context switch time,
When we exit from an interrupt handler, we directly use tcb->xcp.regs
before
size nuttx
text data bss dec hex filename
225920 409 30925 257254 3ece6 nuttx
after
text data bss dec hex filename
225604 409 30925 256938 3ebaa nuttx
szie change -316
Signed-off-by: hujun5 <hujun5@xiaomi.com>
Change syslog API naming more reasonable:
1. rename syslog_channel() to syslog_channel_register()
2. rename syslog_channel_remove() to syslog_channel_unregister()
Signed-off-by: chao an <anchao@lixiang.com>
When the toolchain does not support atomic, it will use the version implemented by NuttX (low performance version). This scenario is consistent with the original design, so we can ignore it.
see bug here:
https://bugs.llvm.org/show_bug.cgi?id=43603
Error: inode/fs_inodeaddref.c:50:7: error: large atomic operation may incur significant performance penalty; the access size (4 bytes) exceeds the max lock-free size (0 bytes) [-Werror,-Watomic-alignment]
50 | atomic_fetch_add(&inode->i_crefs, 1);
| ^
/tools/clang-arm-none-eabi/lib/clang/17/include/stdatomic.h:152:43: note: expanded from macro 'atomic_fetch_add'
152 | #define atomic_fetch_add(object, operand) __c11_atomic_fetch_add(object, operand, __ATOMIC_SEQ_CST)
| ^
1 error generated.
make[1]: *** [Makefile:83: fs_inodeaddref.o] Error 1
Error: inode/fs_inodefind.c:74:7: error: large atomic operation may incur significant performance penalty; the access size (4 bytes) exceeds the max lock-free size (0 bytes) [-Werror,-Watomic-alignment]
74 | atomic_fetch_add(&node->i_crefs, 1);
Signed-off-by: chenrun1 <chenrun1@xiaomi.com>
Summary:
1.Modified the i_crefs from int16_t to atomic_int
2.Modified the i_crefs add, delete, read, and initialize interfaces to atomic operations
The purpose of this change is to avoid deadlock in cross-core scenarios, where A Core blocks B Core’s request for a write operation to A Core when A Core requests a read operation to B Core.
Signed-off-by: chenrun1 <chenrun1@xiaomi.com>
1. Similar to asan, supports single byte out of bounds detection
2. Fix the script to address the issue of not supporting the big end
Signed-off-by: wangmingrong1 <wangmingrong1@xiaomi.com>
resson:
using percpu storage for g_current_regs or leveraging interrupt status
registers to determine if code is running within an interrupt context can enhance performance.
Signed-off-by: hujun5 <hujun5@xiaomi.com>
detail: Add g_ prefix to can_dlc_to_len and len_to_can_dlc to
follow NuttX coding style conventions for global symbols,
improving code readability and maintainability.
Signed-off-by: zhaohaiyang1 <zhaohaiyang1@xiaomi.com>
Fix an issue of driver open failure caused by the following commit
that changes the initial value of inode reference.
43d0d95f81 fs/inode: using inode reference to indicate unlink and simply code
after enable both CONFIG_BUILD_KERNEL and CONFIG_ARCH_VMA_MAPPING
arch.h:141:18: error: 'ARCH_SHM_MAXPAGES' undeclared here
Signed-off-by: wanggang26 <wanggang26@xiaomi.com>
In SMP mode, qemu/goldfish platform, cpu0 use up_cpu_start()
to start others cpus.
But in previous patch(mathion ahead), arm_gic_initialize() will
wait others cpus start, so deadlocked!
Resolve:
Move the wait logic when use using sgi
Signed-off-by: ligd <liguiding1@xiaomi.com>
After move the SGI irq to group1, other cpu can't response the
sgi request from cpu0 when its gic not initialized.
So let cpu0 wait until all other cpus gic initialize done.
Signed-off-by: Bowen Wang <wangbowen6@xiaomi.com>
Revert "Parallelize depend file generation"
This reverts commit d5b6ec450f.
parallel depend ddc does not significantly speed up compilation,
intermediately generated .ddc files can cause problems if compilation is interrupted unexpectedly
Signed-off-by: xuxin19 <xuxin19@xiaomi.com>
change the extra library from a file to an import target;
this will avoid differences in the handling of static libraries
between different versions of cmake and different platforms.
after unifying as a target, extra libraries can be
handled as the same as other compiled libraries
Signed-off-by: xuxin19 <xuxin19@xiaomi.com>
prepare 16550 UART driver to support PCI:
- [breaking change] change argument of uart_ioctl() from `struct file *filep` to `FAR struct u16550_s *priv`
Also fix moxart_16550.c build related to this change
- [breaking change] change argument of uart_getreg() and uart_putreg from `uart_addrwidth_t base` to `FAR struct u16550_s *priv`
Also fix arch/x86/src/qemu/qemu_serial.c and arch/x86_64/src/intel64/intel64_serial.c related to this change
- [breaking change] change argument of uart_dmachan() from `uart_addrwidth_t base` to `FAR struct u16550_s *priv`
- move `struct u16550_s` to public header
- generalize UART_XXX_OFFSET so we can use it with any register increment
- make u16550_bind(), u16550_interrupt(), u16550_interrupt() public
- remove arch/or1k/src/common/or1k_uart.c and use common 16550 MIMO interfacve
- change irq type in `struct u16550_s` from uint8_t to int to match MSI API
Signed-off-by: p-szafonimateusz <p-szafonimateusz@xiaomi.com>
reason:
1 On different architectures, we can utilize more optimized strategies
to implement up_current_regs/up_set_current_regs.
eg. use interrupt registersor percpu registers.
code size
before
text data bss dec hex filename
262848 49985 63893 376726 5bf96 nuttx
after
text data bss dec hex filename
262844 49985 63893 376722 5bf92 nuttx
size change -4
Configuring NuttX and compile:
$ ./tools/configure.sh -l qemu-armv8a:nsh_smp
$ make
Running with qemu
$ qemu-system-aarch64 -cpu cortex-a53 -smp 4 -nographic \
-machine virt,virtualization=on,gic-version=3 \
-net none -chardev stdio,id=con,mux=on -serial chardev:con \
-mon chardev=con,mode=readline -kernel ./nuttx
Signed-off-by: hujun5 <hujun5@xiaomi.com>
reason:
In SMP, when a context switch occurs, restore_critical_section is executed.
To reduce the time taken for context switching, we directly pass the required
parameters to restore_critical_section instead of acquiring them repeatedly.
Signed-off-by: hujun5 <hujun5@xiaomi.com>
We can see them in ifconfig:
ap> ifconfig
wlan0 Link encap:Ethernet HWaddr 42:64:7f:b3:12:03 at UP mtu 1500
inet addr:10.0.1.2 DRaddr:10.0.1.1 Mask:255.255.255.0
inet6 DRaddr: ::
RX: Received Fragment Errors Bytes
00000b9b 00000000 00000000 21daf5
IPv4 IPv6 ARP Dropped
00000a33 00000137 00000031 00000000
TX: Queued Sent Errors Timeouts Bytes
00000ac4 00000ac4 00000000 00000000 1a2103
Total Errors: 00000000
Signed-off-by: meijian <meijian@xiaomi.com>
Since the introduction of the rp2350, the pico-sdk project has been
re-arranged and elf2uf2 has been merged in to a new 'picotool' binary
which is supplied and installed separately.
Make umm & kmm heap alloc more clear, and possible support FLAT build to
enable kernel heap.
Signed-off-by: yinshengkai <yinshengkai@xiaomi.com>
Signed-off-by: buxiasen <buxiasen@xiaomi.com>
1. correct the armv8-r fpu flag from vfpv3-d16 to fpv5-sp-d16
2. add neon support
This commit updates the build script to specify the FPU type of
`fpv5-sp-d16` when the processor is configured with a single-precision
FPU, and `neon-fp-armv8` when the processor is configured with a
double-precision + Advanced SIMD-capable FPU.
Note that the `fp-armv8` FPU type is an alias for double-precision FPv5
with 32 double-precision registers (refer to the GCC
`gcc/config/arm/arm-cpus.in` for more details); NEON is always
specified in case of a double-precision configuration because the
Cortex-R52 can only be configured as such.
Reference:
https://developer.arm.com/Processors/Cortex-R52
Instruction set:
Arm and Thumb-2. Supports DSP instructions and a configurable Floating-Point
Unit either with single-precision or double precision and Neon.
Signed-off-by: chao an <anchao@lixiang.com>
Make this_cpu is arch independent and up_cpu_index do that.
In AMP mode, up_cpu_index() may return the index of the physical core.
Signed-off-by: fangxinyong <fangxinyong@xiaomi.com>
In corner case, the pending ISR will be triggered immediately
after enable the IRQ, this PR will setting CPU affinity first
to avoid routing the unexpected IRQ to other CPUs.
Signed-off-by: chao an <anchao@lixiang.com>
Some USB controllers can receive or send multiple data packets then
generate one interrupt. This mechanism can reduce the number of data
copies. Extend req buf to accommodate this.
Signed-off-by: yangsong8 <yangsong8@xiaomi.com>
