Commit graph

1859 commits

Author SHA1 Message Date
Tiago Medicci Serrano
c72c66fff8 espressif: Fix deadlock in RT timer caused by critical section
This commit fixes a deadlock in `esp32s3-devkit:sta_softap`
defconfig: `spin_lock_irqsave` was being used to enter a critical
section that calls `nxsem_post`. In this case, it's recommended
to use `[enter|leave]_critical_section` to avoid deadlocks when a
context switch may happen, for instance.
2024-08-30 17:00:51 -03:00
Tiago Medicci Serrano
a916de0e14 espressif: Update HAL library reference to include debug assert
During the board bringup, the new HAL reference includes an assert
to check if the critical section flags is being stored as expected.
2024-08-30 21:41:47 +08:00
yangsong8
5a39e83c05 usbdev: extend the usb req len to size_t
Some USB controllers can receive or send multiple data packets then
generate one interrupt. This mechanism can reduce the number of data
copies. Extend req buf to accommodate this.

Signed-off-by: yangsong8 <yangsong8@xiaomi.com>
2024-08-30 01:32:02 +08:00
4c35bde3ba risc-v/bl808: Configure MMU to cache User Text, Data and Heap
This PR configures the BL808 MMU to cache the the User Text, Data and Heap. We enable the T-Head MMU Flags for Shareable, Bufferable and Cacheable, as explained in the previous PR: https://github.com/apache/nuttx/pull/13199

This PR fixes the Slow Memory Access for NuttX Apps on Ox64 BL808 SBC: https://github.com/apache/nuttx/issues/12696. With this fix, Ox64 NuttX CoreMark jumps from 19 to 1,104. (Close to Buildroot Linux CoreMark)

Modified Files:

`arch/risc-v/Kconfig`: Enabled `ARCH_MMU_EXT_THEAD` for BL808 SoC.
2024-08-28 13:47:41 +08:00
b14dc8f8ae risc-v/mmu: Configure T-Head MMU to cache User Text, Data and Heap
This PR configures the T-Head MMU to cache the the User Text, Data and Heap. We enable the MMU Flags for Shareable, Bufferable and Cacheable, as explained in this article: https://lupyuen.github.io/articles/plic3#appendix-mmu-caching-for-t-head-c906

This PR fixes the Slow Memory Access for NuttX Apps on BL808 and SG2000 SoCs: https://github.com/apache/nuttx/issues/12696. With this fix, SG2000 NuttX CoreMark jumps from 21 to 2,423. (Close to SG2000 Debian CoreMark)

We introduce a Kconfig Option: `ARCH_MMU_EXT_THEAD` ("System Type > Enable T-Head MMU extension support"). Enabling this Kconfig Option will configure the T-Head MMU to cache the User Text, Data and Heap.

This PR enables the MMU cache for only SG2000 SoC (Milk-V Duo S SBC). The next PR will apply the same settings to BL808 SoC (Pine64 Ox64 SBC).

Modified Files:

`arch/risc-v/Kconfig`: Added Kconfig Option `ARCH_MMU_EXT_THEAD` that will configure the T-Head MMU. Enabled `ARCH_MMU_EXT_THEAD` for SG2000 SoC.

`arch/risc-v/src/common/riscv_mmu.h`: Set the T-Head MMU Flags (Shareable, Bufferable and Cacheable) for User Text, Data and Heap, if `ARCH_MMU_EXT_THEAD` is enabled

`arch/risc-v/src/common/riscv_addrenv.c`: Extended the MMU Flags from 32 bits to 64 bits, to accommodate the T-Head MMU Flags

`arch/risc-v/src/common/riscv_exception.c`: Extended the MMU Flags from 32 bits to 64 bit, to accommodate the T-Head MMU Flags. This code is enabled only for MMU Paging (`CONFIG_PAGING`).
2024-08-27 19:54:58 -04:00
hujun5
1d6a099180 irq: remove restore_critical_section in irq
Only in the non-critical region, nuttx can the respond to the irq and not hold the lock
When returning from the irq, there is no need to check whether the lock needs to be released
we also need keep restore_critical_section in svc call

test:
Configuring NuttX and compile:
$ ./tools/configure.sh -l qemu-armv8a:nsh_smp
$ make
Running with qemu
$ qemu-system-aarch64 -cpu cortex-a53 -smp 4 -nographic \
   -machine virt,virtualization=on,gic-version=3 \
   -net none -chardev stdio,id=con,mux=on -serial chardev:con \
   -mon chardev=con,mode=readline -kernel ./nuttx

Signed-off-by: hujun5 <hujun5@xiaomi.com>
2024-08-25 21:14:19 +08:00
Petro Karashchenko
d499ac9d58 nuttx: fix multiple 'FAR', 'CODE' and style issues
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
2024-08-25 19:22:15 +08:00
Petro Karashchenko
7b18f9d19f nuttx: add missing 'FAR' and fix style issues
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
2024-08-25 19:22:15 +08:00
Petro Karashchenko
f40b09cbc9 style: remove redundant spaces
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
2024-08-25 19:22:15 +08:00
Yanfeng Liu
634ee5b1f6 board/maix-bit: add cmake support
This adds initial CMake support for `maix-bit` device.

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
2024-08-24 11:08:25 +08:00
Matheus Catarino
93b520f7b0 swift6 embedded support 2024-08-23 09:02:20 +08:00
chenrun1
8e1a042eef nuttx/atomic.h:Fix missing type declarations at compile time
Summary:
  1.Modify the conditions for entering different include header files
  2.Added pre-definition for _Atomic _Bool when it is missing
  3.Added nuttx for stdatomic implementation. When toolchain does not support atomic, use lib/stdatomic to implement it

Signed-off-by: chenrun1 <chenrun1@xiaomi.com>
2024-08-22 01:44:29 +08:00
Tiago Medicci Serrano
568917bfd2 espressif: Fix MCUboot build on RISC-V and unify linker script
This commit fixes building MCUboot on Espressif's RISC-V SoCs and
unify the associated linker scripts to make improve readability.
2024-08-21 23:28:45 +08:00
Tiago Medicci Serrano
5680e9d5a4 espressif: Update internal libraries reference
Update internal reference to get the most updated Espressif's
libraries. Those libraries are based on branch `release/v5.1` of
the ESP-IDF and include `v5.1.4` version of it.
2024-08-21 23:28:45 +08:00
hujun5
4cb419866f arch: inline up_testset in arm arm64 riscv xtensa
test:
Configuring NuttX and compile:
$ ./tools/configure.sh -l qemu-armv8a:nsh_smp
$ make
Running with qemu
$ qemu-system-aarch64 -cpu cortex-a53 -smp 4 -nographic \
   -machine virt,virtualization=on,gic-version=3 \
   -net none -chardev stdio,id=con,mux=on -serial chardev:con \
   -mon chardev=con,mode=readline -kernel ./nuttx

Signed-off-by: hujun5 <hujun5@xiaomi.com>
2024-08-21 01:45:10 +08:00
Filipe Cavalcanti
4d4d8a6ca5 arch/risc-v/esp32c3: fix AP password memcpy typo 2024-08-20 00:50:26 +02:00
Yanfeng Liu
3166c6d9c6 riscv/qemu-rv: add RPTUN cmake
This adds cmake support for RPTUN.
2024-08-19 19:53:03 +08:00
xuxin19
9fdd299d32 cmake:split the archive process to avoid parameter problems
refer to:https://cmake.org/cmake/help/latest/variable/CMAKE_LANG_ARCHIVE_APPEND.html

this will solve the problem of too long parameters
when executing ar in cygwin environment such as msys.

Signed-off-by: xuxin19 <xuxin19@xiaomi.com>
2024-08-18 23:26:01 +08:00
Yanfeng Liu
b9fde453ce riscv/qemu-rv: add RPTUN support
This adds initial RPTUN support for qemu-rv and rv-virt device.

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
2024-08-18 19:55:27 +08:00
Yanfeng Liu
2af5ad174f riscv/qemu-rv: add RPTUN Kconfig
This add RPTUN related Kconfigs for qemu-rv chip.

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
2024-08-18 19:55:27 +08:00
Eren Terzioglu
e11a53bec9 esp32[c3|c6|h2]: Add adjustable SPI clock speed 2024-08-17 13:43:58 +08:00
Tiago Medicci
69a8e2697f espressif: Fix default pins for SPI bus 2 on ESP32-[C3|C6|H2]
Fix the correct pin number for the SPI 2 bus on ESP32-C3, ESP32-C6
and ESP32-H2.
2024-08-17 13:43:58 +08:00
Eren Terzioglu
61dff51a33 esp32[c3|c6|h2]: Fix SPI clock issue 2024-08-17 13:43:58 +08:00
chenxiaoyi
7ce5241f0e types.h: fix windows build error
Windows Kits\10\Include\10.0.22621.0\ucrt\corecrt.h(605,39): error C2371: 'wint_t': redefinition; different basic types
Windows Kits\10\Include\10.0.22621.0\ucrt\corecrt.h(606,39): error C2371: 'wctype_t': redefinition; different basic types

Co-authored-by: chenxiaoyi <chenxiaoyi@xiaomi.com>
Co-authored-by: xuxin19 <xuxin19@xiaomi.com>
2024-08-14 22:36:57 +08:00
Yanfeng Liu
41dba46c1d arch/riscv: fix IRQ_SOFT for non-SMP
This fixes software interrupt number for non-SMP cases

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
2024-08-14 20:59:52 +08:00
Yanfeng Liu
f5b2fc371e riscv/qemu-rv: use cluster PLIC/CLINT configs
This uses cluster speficic PLIC, CLINT and ACLINT devices in NuttX.

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
2024-08-12 20:43:05 +08:00
Yanfeng Liu
6db85498a2 riscv/qemu-rv: add cluster PLIC/CLINT configs
This adds cluster specific configs for PLIC, CLINT and ACLINT
devices.

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
2024-08-12 20:43:05 +08:00
yanghuatao
fecc5091af toolchain/ghs: Fix SP_DSB warnings
"/mnt/yang/qixinwei_vela_warnings/nuttx/include/nuttx/spinlock.h", line 252: warning #76-D:
          argument to macro is empty
        SP_DSB();
               ^

"/mnt/yang/qixinwei_vela_warnings/nuttx/include/nuttx/spinlock.h", line 261: warning #76-D:
          argument to macro is empty
    SP_DMB();
           ^

"/mnt/yang/qixinwei_vela_warnings/nuttx/include/nuttx/spinlock.h", line 252: warning #76-D:
          argument to macro is empty
        SP_DSB();
               ^

"/mnt/yang/qixinwei_vela_warnings/nuttx/include/nuttx/spinlock.h", line 261: warning #76-D:
          argument to macro is empty
    SP_DMB();
           ^

"/mnt/yang/qixinwei_vela_warnings/nuttx/include/nuttx/spinlock.h", line 296: warning #76-D:
          argument to macro is empty
        SP_DSB();
               ^

Signed-off-by: yanghuatao <yanghuatao@xiaomi.com>
2024-08-11 14:28:12 -03:00
Yanfeng Liu
47b0414eab arch/riscv: add cluster local hartid
Some multicore RV chips (mpfs, jh7110 etc) have hart clusters
and globally numbered mhartids. Clusters with single hart or
SMP support can be managed by one NuttX instance. Currently
NuttX expects to use cluster-local ids.

This allows us to get local ids by offsetting mhartids with a
base value.

Note that there are chips (e.g. k230) that use cluster-local
ids directly, so this is not needed for them.

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
2024-08-12 00:10:13 +08:00
Yanfeng Liu
46f4a24d59 riscv/qemu: add CMake for PROTECTED
This adds CMake support for PROTECTED build mode on rv-virt target.

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
2024-08-09 23:43:31 +08:00
Yanfeng Liu
01c37f7012 riscv/rv32m1: fix build issue
This exports `return_from_exception` symbol to fix build issue with
unified in-kernel syscall.

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
2024-08-08 21:25:59 +08:00
Yanfeng Liu
6986cd4105 arch/riscv: unify in-kernel syscall
This generalizes the in-kernel syscall approach from KERNEL mode to
all build modes so that to unify in-kernel syscall invocations.  As
a result, machine mode ECALL and the supervisor folder are no longer
needed.

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
2024-08-08 21:25:59 +08:00
Yanfeng Liu
77cfbf8914 riscv/fork: fix gp register handling
This fixes the handling of gp register in fork.

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
2024-08-08 09:42:29 +08:00
Yanfeng Liu
3f021d5429 riscv/fork: fix fp/s0 field position
The fp/s0 field position shall be in line with the macro
FORK_FP_OFFSET/FORK_S0_OFFSET.

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
2024-08-08 09:42:29 +08:00
Ville Juven
622e5b26b3 riscv/syscall: Fix fork() system call
When executing fork() via a system call, the parent's stack gets corrupted
by the child, as during exception return the child loads the parent's
stack pointer from the context save area.

This happens because the full parent stack (including what has been pushed
during the system call) is copied to the child. What should be copied, is
only the user stack of the parent (the kernel stack is not interesting).

Fix this by only copying the parent's user stack to the child; and make
the child return directly to userspace (not via dispatch_syscall).
2024-08-07 02:41:14 +08:00
Ville Juven
2cf8ac2f63 risc-v/riscv_swint.c: Simplify implementation of dispatch_syscall
Simplifies the implementation of dispatch_syscall, making it easier to
understand and maintain. Let the C-compiler do most of the work, instead
of doing everything as inline assembly.
2024-08-07 02:41:14 +08:00
Ville Juven
fa71bc3d74 riscv/syscall: Add dependency to RISCV_PERCPU_SCRATCH when LIB_SYSCALL=y
The per CPU scratch register is needed by system calls -> enable it by
default.
2024-08-07 02:41:14 +08:00
Filipe Cavalcanti
65e989e063 arch/risc-v: add support for motor control on ESP32|C6|H2 2024-08-05 15:35:19 -03:00
Yanfeng Liu
a36c168e54 riscv/nsbi: fix up_udelay for rv32
This fixes riscv_sbi_get_time for rv32 and NuttSBI is used.

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
2024-08-05 16:21:49 +08:00
Yanfeng Liu
5848a8e77c riscv/qemu-rv: revise PROTECTED mode
This revises PROTECTED build for qemu-rv mainly to avoid hard-coded
addresses in linker scripts. It also added rv32 support, cleaned up
config `pnsh64` and added config `pnsh`.

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
2024-08-04 11:09:26 +08:00
Ville Juven
1f928b2338 qemu-rv: Add test target pnsh64 for BUILD_PROTECTED
This adds BUILD_PROTECTED target for rv-virt (rv-virt:pnsh64).
2024-08-02 20:29:11 +08:00
Yanfeng Liu
918ad10859 riscv/qemu: add NuttSBI support
This adds NuttSBI support for rv-virt device so that to enable CI
checks for NuttSBI later. It allows using `-bios nuttx` option to
run NuttX with QEMU v6.2 w/o OpenSBI.

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
2024-08-01 23:32:01 +08:00
Yanfeng Liu
ab7bc90ebb riscv/nsbi: halt upon sbi_mexception
This avoids endless restart if NuttSBI fails to enter S-mode.

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
2024-08-01 23:32:01 +08:00
Yanfeng Liu
5e551632dd riscv/nsbi: prefer PMP settings in device hook
This adjusts sbi_start behavior so that if SBI late initialization hook
is defined, PMP setting is assumed to be fully done in the hook, because
the default PMP operation may fail for various reasons such as lacking
free entries or the default setting doesn't work on devices like QEMU
v6.2.

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
2024-08-01 23:32:01 +08:00
Huang Qi
f9cc33468f riscv/espressif: Mark private data as static in esp_spi.c
These symbols only used in esp_spi.c and too simple
to conflict with others, so mark them as static:
- cfg
- ctx
- dev_cfg
- timing_param

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2024-08-01 23:28:53 +08:00
Ville Juven
cbb07a595e k230_start.c: Fix condition for k230_copy_init_data()
Fixes regression from https://github.com/apache/nuttx/pull/12220

Error: chip/k230_start.c:80:13: error: 'k230_copy_init_data' defined but not used [-Werror=unused-function]
   80 | static void k230_copy_init_data(void)
      |             ^~~~~~~~~~~~~~~~~~~
2024-08-01 23:27:30 +08:00
Tiago Medicci
24954800a7 espressif: Update HAL version for all Espressif SoCs
Provides the most update libraries to support the drivers for the
Espressif SoCs.
2024-08-01 16:04:53 +08:00
Huang Qi
6ea3bc1217 riscv/debug: Add support for steppoint
Steppoint can be implemented by icount(instruction count)
from RISC-V debug extension, but it may not implemented in all RISC-V cores.

Unfortunately, the currently supported RISC-V cores do not implement it.

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2024-08-01 13:57:51 +08:00
Eren Terzioglu
00ff9ef15c esp32[c3|c6|h2]: Add SPI slave DMA support 2024-08-01 01:26:29 +08:00
Eren Terzioglu
f5b63cea18 esp32[c3|c6|h2]: Add SPI master DMA support 2024-08-01 01:26:29 +08:00
Inochi Amaoto
b35f7aed48 arch/risc-v: qemu: add AIA support
Implement AIA support for qemu rv-virt.

Signed-off-by: Inochi Amaoto <inochiama@outlook.com>
2024-07-31 12:43:04 -03:00
Inochi Amaoto
5f70307111 arch/risc-v: introduce AIA support
Advanced Interrupt Architecture (AIA) introduces flexiable interrupt
controll for RISC-V. It includes three parts: AIA CSRs, Incoming Message
Signaled Interrupt Controller (IMSIC) and  Advanced Platform-Level
Interrupt Controller (APLIC).

Signed-off-by: Inochi Amaoto <inochiama@outlook.com>
2024-07-31 12:43:04 -03:00
Yanfeng Liu
a6c7e68b5d riscv/qemu-rv: skip reloading mhartid
As a0 already has mhartid passed by SBI  or ZSBL, no need to load it
again here.

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
2024-07-30 18:20:22 +08:00
Eren Terzioglu
e467a16abe esp32[c3|c6|h2]: Add temperature sensor support 2024-07-27 14:12:44 -03:00
Henry Rovner
23bc78a5b7 bl808_wdt: Expand function headers 2024-07-27 22:59:23 +08:00
Henry Rovner
42eafcdfa5 risc-v/bl808: Add watchdog driver
This change implements a driver for the two watchdog timers on the BL808, and enables it as part of the timer config. The driver is based on the GP timer driver.
2024-07-27 22:59:23 +08:00
buxiasen
f5021021ae up_backtrace: fix maybe backtrace the exiting thread
when the thread to backtrace is exiting, get_tcb and up_backtrace in
different critical section may cause try to dump invalid pointer, have
to ensure the nxsched_get_tcb and up_backtrace inside same critical
section procedure.

Signed-off-by: buxiasen <buxiasen@xiaomi.com>
2024-07-26 12:03:43 +08:00
Yanfeng Liu
9e59b0b43b riscv/qemu: guard u16550 uses
This guards the uses for u16550 serial initialization, just in case
that no u16550 is configured.

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
2024-07-26 12:01:29 +08:00
Henry Rovner
049a6da098 risc-v/bl808: Add timer driver
This change implements a driver for the hardware timer blocks on the BL808, as well as a config with the timer example enabled.
2024-07-24 10:06:54 +08:00
Yanfeng Liu
3b9a346fe7 riscv/nsbi: unblock up_udelay
This fixes the always zero time in NuttSBI case as the `error` field
contains the correct timestamp. This in turn also fixes the block of
`up_udelay()` which further leads to boot failure of `canmv230:master`
config.

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
2024-07-22 23:46:43 +08:00
Inochi Amaoto
0ddcbe62ec arch/risc-v: does not clear IPI address in S mode
According to the riscv-aclint doc, writing 0 to SSWI address
has no effect. Remove this unnecessary write for S mode.

Link: https://github.com/riscv/riscv-aclint/blob/main/riscv-aclint.adoc

Signed-off-by: Inochi Amaoto <inochiama@outlook.com>
2024-07-18 22:59:29 +08:00
Inochi Amaoto
000b0ec4a1 arch/risc-v: make common up_allocate_heap weak symbol
The common `up_allocate_heap` is a strong symbol, which leads to
error when building with CONFIG_DEBUG_LINK_WHOLE_ARCHIVE. Make
`up_allocate_heap` weak function to mitigate this problem.

Signed-off-by: Inochi Amaoto <inochiama@outlook.com>
2024-07-18 13:40:37 +08:00
bdf60d7966 risc-v/bl808, sg2000: Configure MMU to cache Kernel Text, Data and Heap (T-Head C906)
This PR configures the BL808 and SG2000 MMU (inside T-Head C906) to cache the the Kernel Text, Data and Heap.  We set the MMU Flags (Shareable, Bufferable and Cacheable) as explained in this article: https://lupyuen.github.io/articles/plic3#appendix-mmu-caching-for-t-head-c906

This PR fixes the Slow Memory Access for NuttX Kernel in BL808 and SG2000: https://github.com/apache/nuttx/issues/12696

In the next PR, we will fix the Slow Memory Access for NuttX Apps, by caching the User Text and Data.

arch/risc-v/src/bl808/bl808_mm_init.c: Added MMU Flags (Shareable, Bufferable and Cacheable) for BL808 Kernel Text, Data and Heap

arch/risc-v/src/sg2000/sg2000_mm_init.c: Added MMU Flags (Shareable, Bufferable and Cacheable) for SG2000 Kernel Text, Data and Heap
2024-07-17 12:08:04 -03:00
Yanfeng Liu
d6c67c555f riscv/trap: fix sp restore logic
This fixes stack pointer restore logic to avoid parent stack corruption
by forked child in PROTECTED build.

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
2024-07-17 17:20:00 +08:00
Yanfeng Liu
08c4686f47 riscv/fork: fix tp for PROTECTED
This fixes `tp` value of forked child in PROTECTED build to support
vfork. Why? the optimized `dispatch_syscall` requires `tp` to hold
the task TCB since commit e6973c764c.

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
2024-07-17 17:20:00 +08:00
Eren Terzioglu
0df037855a esp32[c3]: Add mcuboot build script for esp32c3-legacy 2024-07-16 10:30:56 +08:00
Eren Terzioglu
553b1f5f5e esp32[c3|c6|h2]: Add nuttx toolchain support on mcuboot 2024-07-16 10:30:56 +08:00
Yanfeng Liu
8bdc975abb riscv/cmake: fix Toolchain.cmake issue
This fixes the following issue when configuring canmv230:master
with Ubuntu stock toolchain and cmake 3.22:

```
CMake Error at .../arch/risc-v/src/cmake/Toolchain.cmake:218 (if):
  if given arguments:
    "STREQUAL" "GNU_RVG"
  Unknown arguments specified
```

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
2024-07-15 19:41:03 +08:00
hujun5
a4fece3450 spin_lock: inline spin_lock
test:
We can use qemu for testing.
compiling
make distclean -j20; ./tools/configure.sh -l qemu-armv8a:nsh_smp ;make -j20
running
qemu-system-aarch64 -cpu cortex-a53 -smp 4 -nographic -machine virt,virtualization=on,gic-version=3 -net none -chardev stdio,id=con,mux=on -serial chardev:con -mon chardev=con,mode=readline -kernel ./nuttx
2024-07-15 02:29:30 +08:00
Huang Qi
e047ab9c70 riscv: Initial support for debug trigger module
Implement up_debugpoint_add/up_debugpoint_remove for riscv.

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2024-07-14 20:32:19 +08:00
Eren Terzioglu
c15c0d1a78 esp32[h2]: Add MCUBoot support 2024-07-14 11:38:29 +08:00
Eren Terzioglu
0f0c258fa2 esp32[c6]: Add MCUBoot support 2024-07-14 11:38:29 +08:00
Yanfeng Liu
211e2cd8b9 riscv/k230: revise canmv230:pnsh
This revises canm230:pnsh in a few ways:

- adjusting linker scripts structure,
- asserting PMP setting results,
- adjusting configs for both k230d and k230 devices.

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
2024-07-13 07:21:22 -03:00
simbit18
f12c4e05cc Fix Kconfig style
Remove spaces from Kconfig files
Add TABs
Replace help => ---help---
Remove extra TABs
2024-07-12 06:37:59 +08:00
Henry Rovner
091372069c risc-v/bl808: Add SPI driver
This commit implements a driver for SPI0 and SPI1 on the BL808 and introduces an accompanying example configuration.
2024-07-11 11:32:24 +08:00
Huang Qi
d0210c1174 riscv_tcbinfo: Fix register ordering for PC
X0 is always 0 but still should be transfered to the client, but it don't existed in thread context, use any other register for it, and its value will be omitted by gdb client.

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2024-07-08 21:13:25 +08:00
Henry Rovner
a83e7ced77 ox64: Add adc example config 2024-07-05 13:17:02 +08:00
Henry Rovner
8493273c2c risc-v/bl808: Add GPADC character driver
This commit implements a character driver for the general purpose ADC of the BL808, based on the hardware scanning functionality. The driver supports setting different conversion resolutions and the order of channels to be scanned via menuconfig.
2024-07-05 13:17:02 +08:00
Filipe Cavalcanti
0c63840b18 arch/risc-v: add support for capture driver on ESP32C6 and ESP32H2. 2024-07-04 18:24:50 -03:00
Masayuki Ishikawa
04c19bb1c9 Revert "irq: remove restore_critical_section in irq"
This reverts commit f6a9e91057.
2024-07-02 15:46:20 +08:00
hujun5
f6a9e91057 irq: remove restore_critical_section in irq
Only in the non-critical region, nuttx can the respond to the irq and not hold the lock
When returning from the irq, there is no need to check whether the lock needs to be restored

test:
We can use qemu for testing.
compiling
make distclean -j20; ./tools/configure.sh -l qemu-armv8a:nsh_smp ;make -j20
running
qemu-system-aarch64 -cpu cortex-a53 -smp 4 -nographic -machine virt,virtualization=on,gic-version=3 -net none -chardev stdio,id=con,mux=on -serial chardev:con -mon chardev=con,mode=readline -kernel ./nuttx

Signed-off-by: hujun5 <hujun5@xiaomi.com>
2024-07-02 03:00:57 +08:00
xuxingliang
c6d712df0e sched: move nxsched_dumponexit() to task_exithook
So the tcb->group still exists to dump files.

Signed-off-by: xuxingliang <xuxingliang@xiaomi.com>
2024-06-30 17:30:42 +08:00
Huang Qi
c66b0866e8 riscv_exception.c: Add missing comma in exception reasons array 2024-06-28 17:00:11 -03:00
Yanfeng Liu
28eaa08cbc arch/riscv: fix PMP in sbi_start()
This fixes PMP setting for open everything before going S-mode, which
has been broken since pull/12398.

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
2024-06-28 21:30:53 +08:00
Yanfeng Liu
cd57bc16c7 riscv/pmp: add all region in NAPOT
This allows using 0 base and size to depict the whole region.

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
2024-06-28 17:54:46 +08:00
Eren Terzioglu
dcea703bae esp32[c3|c6|h2]: Add GDMA support 2024-06-28 17:52:56 +08:00
Eren Terzioglu
dda55419f9 esp32[c3|c6|h2]: Add I2C master support 2024-06-28 17:27:46 +08:00
Henry Rovner
63375bf9cd BL808: Replace courier with M0 interrupt controller
It turns out that the D0 core of the BL808 has an IRQ that represents all interrupt sources for the M0 core. This change uses this IRQ to access these sources, eliminating the need for IPC between M0 and D0.
2024-06-28 17:23:02 +08:00
Henry Rovner
7d2dbc00f6 Revert "Add courier system driver"
This reverts commit 50dd04c0f6.
2024-06-28 17:23:02 +08:00
yanghuatao
7e342b3422 arch: Add --whole-archive linker option for some of architectures
Add Kconfig option that enable --whole-archive linker option for some of architectures

Signed-off-by: yanghuatao <yanghuatao@xiaomi.com>
2024-06-28 02:31:40 +08:00
rushabhvg
05842e726f risc-v/bl808: Add GPIO Driver
- This PR adds the GPIO Driver for BL808 SoC. This will be used by the upcoming LED Driver for Ox64 Board.
- The BL808 GPIO Driver was derived from the NuttX Driver for BL602 GPIO

Co-Authored-By: Lup Yuen Lee <luppy@appkaki.com>
2024-06-27 11:49:25 -03:00
Huang Qi
c3b05bde44 riscv: Improve exception and irq mapping
Allow chip to define the custom exception on demand.

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2024-06-26 09:07:52 +08:00
Henry Rovner
023bd08faa BL808: Add support for UARTs 0-2 and serial configuration
This commit modifies the existing serial driver to add support for the remaining UARTs on the BL808. It also introduces support for setting baud rate, character length, stop bits, parity, flow control and which serial port acts as the console.
2024-06-26 09:06:38 +08:00
Tiago Medicci Serrano
126c83a7dc espressif: Fix error while evaluating Wi-Fi task ID
Use `nxsched_gettid` instead of `nxsched_getpid`. Previously each
kernel thread was modelled as a task, so the pid is the same of the
kthread id. Now, with shared kthread group (introduced by #12320),
the pid of all kthreads will be 0 by design in shared group.
2024-06-25 18:40:27 -03:00
Yanfeng Liu
9790248f9a riscv/nuttsbi: add MTVAL argument
The MTVAL and the other two provides a complete exception story.

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
2024-06-23 22:25:10 +08:00
Henry Rovner
5a7cf6ccad Style and comment fixes, more definitions in terms of constants for better clarity 2024-06-23 11:21:55 +08:00
Henry Rovner
210ea76b04 Add courier system driver
This change implements a system for allowing the D0 core (which runs NuttX) to receive forwarded interrupts from the M0 core. This makes it possible for drivers that rely on interrupts to work with peripherals attached to the M0 core.
2024-06-23 11:21:55 +08:00
hujun5
ed78646798 signal: fix deadlock when sigdeliver call enter_critical_section
cpu0                                 cpu1:

user_main
signest_test
sched_unlock
nxsched_merge_pending
nxsched_add_readytorun
up_cpu_pause
			             arm_sigdeliver
				     enter_critical_section

Reason:
In the SMP, cpu0 is already in the critical section and waiting for cpu1 to enter the suspended state.
However, when cpu1 executes arm_sigdeliver, it is in the irq-disabled state but not in the critical section.
At this point, cpu1 is unable to respond to interrupts and
is continuously attempting to enter the critical section, resulting in a deadlock.

Resolve:
adjust the logic, do not entering the critical section when interrupt-disabled.

test:
We can use qemu for testing.

compiling
make distclean -j20; ./tools/configure.sh -l qemu-armv8a:nsh_smp ;make -j20
running
qemu-system-aarch64 -cpu cortex-a53 -smp 4 -nographic -machine virt,virtualization=on,gic-version=3 -net none -chardev stdio,id=con,mux=on -serial chardev:con -mon chardev=con,mode=readline -kernel ./nuttx

Signed-off-by: hujun5 <hujun5@xiaomi.com>
2024-06-22 19:35:28 -03:00
Yanfeng Liu
3fb56c9218 arch/risc-v: move PRIxREG to inttypes.h
This moves PRIxREG to inttypes.h to make it available for both kernel
and user spaces.

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
2024-06-22 22:00:06 +08:00
Yanfeng Liu
3a4c2cea55 risc-v/64ilp32: revise up_fpucmp
This revises `up_fpucmp()` to add rv64ilp32 support.

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
2024-06-21 22:42:37 +08:00
Huang Qi
040e1379cd riscv_vector.S: Align trap vector to 64 byte
Bump align to 64 byte to support all interrupt mode, it is essential for CLIC.

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2024-06-21 03:02:59 +08:00
Huang Qi
384610b253 riscv: Add indirect CSRs for CLIC
Add indirect CSR registers for RISC-V Core-Local Interrupt Controller (CLIC) Privileged Architecture Extensions.

Refer to: https://github.com/riscv/riscv-fast-interrupt

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2024-06-21 03:02:59 +08:00
Huang Qi
e5ee04a902 riscv: Add CSRs for CLIC
Add CSR registers for RISC-V Core-Local Interrupt Controller (CLIC) Privileged Architecture Extensions.

Refer to: https://github.com/riscv/riscv-fast-interrupt

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2024-06-21 03:02:59 +08:00
Huang Qi
8ee461fa0e riscv: Add CSRs for Smcsrind/Sscsrind
Add CSR registers for RISC-V Indirect CSR Access (Smcsrind/Sscsrind) Extension.

Refer to: https://github.com/riscvarchive/riscv-indirect-csr-access/tree/main

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2024-06-21 03:02:59 +08:00
Inochi Amaoto
caeb1757f6 arch/risc-v: Improve the SBI function handle
To simplify processing, the existed SBI function code is just
invoking the ecall and return the error value. This omits
potential return value in "a1", which is defined in SBI doc.
Add the "sbiret" struct so it can handle all the return value.

In addition, there are some minor improvement:
1. move the SBI related interface to a separate file to make it clean.
2. add all necessary SBI ecall interface macro until version 2.0.
3. add an utilty function to convert sbi error numner to standard
error number.

Signed-off-by: Inochi Amaoto <inochiama@outlook.com>
2024-06-19 20:55:10 +08:00
Yanfeng Liu
8720594f4d risc-v/k230: initial rv64ilp32 support
This enables NuttX FLAT build with rv64ilp32 on CanMV230 device.

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
2024-06-19 15:32:19 +08:00
Yanfeng Liu
07463e2de1 arch/risc-v: revise mtime address for rv64ilp32
This revises the `mtime` and `mtimecmp` register addresses to
support rv64ilp32.

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
2024-06-19 01:53:21 +08:00
Yanfeng Liu
28ae3b3849 arch/risc-v: revise MMIO for rv64ilp32
This revises `getregXX` and `setregXX` for rv64ilp32 to overcome
the limitation of compiler generated addresses and reach devices
in a larger range.

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
2024-06-18 10:50:49 +08:00
Stuart Ianna
66df96e384 arch/risc-v/include/elf.f: Support coredump for rv32 and rv64 targets.
Adds the missing elf_gregset_t type definition so pr_regs field can be
resolved. Coredumps can be produced for both 32 and 64 bit targets.
2024-06-18 10:41:56 +08:00
008803865f boards/risc-v: Add support for Milk-V Duo S SBC (SOPHGO SG2000 SoC)
This PR adds support for Milk-V Duo S 64-bit RISC-V SBC, based on SOPHGO SG2000 SoC (T-Head C906 Core). Most of the code is derived from NuttX for Ox64 BL808. The source files are explained in the articles here: https://github.com/lupyuen/nuttx-sg2000

Modified Files:

`boards/Kconfig`: Added Milk-V Duo S board

`arch/risc-v/src/sg2000/sg2000_timerisr.c`: Fixed MTIMER_FREQ for sleep() to work correctly

New Files in boards/risc-v/sg2000/milkv_duos:

`src/sg2000_appinit.c`: Startup Code

`include/board.h`: Milk-V Duo S Definitions

`include/board_memorymap.h`: Memory Map

`src/etc/init.d/rc.sysinit`, `rcS`: Startup Script

`src/.gitignore`: Ignore the tmp filesystem

`scripts/ld.script`: Linker Script

`scripts/Make.defs`: Milk-V Duo S Makefile

`src/Makefile`: Milk-V Duo S Makefile

`Kconfig`: Milk-V Duo S Config

`configs/nsh/defconfig`: Build Config for `milkv_duos:nsh`

Updated Documentation:

`platforms/risc-v/sg2000/index.rst`: New page for SOPHGO SG2000 SoC

`platforms/risc-v/sg2000/boards/milkv_duos/index.rst`: Building and booting NuttX for Milk-V Duo S
2024-06-18 00:13:35 +08:00
8e30c13441 arch/risc-v: Add support for SOPHGO SG2000 SoC (T-Head C906)
This PR adds support for the SOPHGO SG2000 SoC, based on T-Head C906 64-bit RISC-V Core. This will be used by the upcoming port of NuttX for Milk-V Duo S SBC.

Most of the code was derived from NuttX for Ox64 BL808. The source files are explained in the articles here: https://github.com/lupyuen/nuttx-sg2000

Modified Files in arch/risc-v:

`Kconfig`: Added ARCH_CHIP_SG2000 for SG2000 SoC

New Files in arch/risc-v:

`include/sg2000/chip.h`: SG2000 Definitions

`include/sg2000/irq.h`: External Interrupts

`src/sg2000/chip.h`: Interrupt Stack Macro

`src/sg2000/sg2000_allocateheap.c`: Kernel Heap

`src/sg2000/sg2000_head.S`: Linux Header and Boot Code

`src/sg2000/sg2000_irq.c`: Configure Interrupts

`src/sg2000/sg2000_irq_dispatch.c`: Dispatch Interrupts

`src/sg2000/sg2000_memorymap.h`: Memory Map

`src/sg2000/sg2000_mm_init.c`, `sg2000_mm_init.h`: Memory Mgmt

`src/sg2000/sg2000_pgalloc.c`: Page Allocator

`src/sg2000/sg2000_start.c`: Startup Code

`src/sg2000/sg2000_timerisr.c`: Timer Interrupt

`src/sg2000/hardware/sg2000_memorymap.h`: PLIC and UART Base Address

`src/sg2000/hardware/sg2000_plic.h`: PLIC Register Addresses

`src/sg2000/Kconfig`: SG2000 Config

`src/sg2000/Make.defs`: Makefile
2024-06-17 09:41:29 +08:00
Inochi Amaoto
e37348aeba arch/risc-v: Add support for S-mode flat build
There is no need to use kernel build for S-mode all the time. As cpu
scratch is supported for non kernel mode build, it is possible to use
flat build for S-mode.

Add flat build support for risc-v S mode.

Signed-off-by: Inochi Amaoto <inochiama@outlook.com>
2024-06-14 19:52:00 +08:00
Yanfeng Liu
8ebc3aa9e8 arch/risc-v: initial qemu-rv64ilp32 support
This applies uintreg_t in risc-v commons and fixes araised ci issues
for multiple devices. The FLAT build runs on qemu-rv64ilp32 target.

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
2024-06-14 19:50:00 +08:00
Yanfeng Liu
33afbaadb9 arch/risc-v: add rv64ilp32 toolchain
This adds support of rv64ilp32 toolchain available from Github repo
`ruyisdk/riscv-gnu-toolchain-rv64ilp32`. With this 32-bit nuttx can
be generated for RV64 devices.

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
2024-06-14 19:50:00 +08:00
Neale Ferguson
73b15a87dc Fix SHMODULEFLAGS so that we link dynamically correctly
* arch/risc-v/src/common/Toolchain.defs
  arch/xtensa/src/lx6/Toolchain.defs
  arch/xtensa/src/lx7/Toolchain.defs
  - Define SHMODULEFLAGS etc. for sotest/dynload
  - Add --entry=__start to SHMODULEFLAGS

* boards/arm64/qemu/qemu-armv8a/scripts/Make.defs
  boards/sim/sim/sim/scripts/Make.defs
  - Define SHMODULEFLAGS etc. for sotest/dynload
2024-06-12 23:21:16 -03:00
Neale Ferguson
5033966d8c Add flags for building shared objects for architectures supporting dynamic loading
* arch/arm/src/common/Toolchain.defs
  arch/risc-v/src/common/Toolchain.defs
  boards/sim/sim/sim/scripts/Make.defs
  - Add SHCCFLAGS and SSHLDFLAGS
2024-06-12 23:21:16 -03:00
Eren Terzioglu
0cf7676aca esp32[c3|c6|h2]: Add SPI Slave support 2024-06-12 22:53:19 -03:00
Eren Terzioglu
62af2993a4 esp32h2: Change delimiter constant with variable 2024-06-12 23:35:24 +08:00
Eren Terzioglu
99ea8b7832 esp32[c3|c6|h2]: Add gspi master support 2024-06-12 23:35:24 +08:00
Tiago Medicci Serrano
6c3eeb7d5c espressif: Remove outdated config about IDF bootloader
For newer devices, IDF bootloader is not supported because the
devices are able to boot directly into NuttX or use MCUBoot to
enable OTA and security features.
2024-06-12 16:11:56 +08:00
Tiago Medicci Serrano
480ad6b631 esp: Make the legacy bootloader (IDF bootloader) option visible
This commit enables users to select the legacy bootloader (IDF
bootloader) in `menuconfig` directly. Please note, that this is a
legacy option intended to support devices already deployed and it
isn't recommended for new designs.
2024-06-12 16:11:56 +08:00
Matheus Catarino
c6eea4ad8b add LDC2 (dlang) support
*Note:* ldmd2 is ldc2-wrapper, allow using dmd frontend flags.
      This support may be extended to gdc (gnu) if nuttx developers demand it
  or are interested in it.
2024-06-06 09:32:56 +08:00
Jani Paalijarvi
b32a1dfd3d risc-v/mpfs: Add error handling for PMP conf
Check return value of mpfs_board_pmp_setup() and
jump to mpfs_board_pmp_error() in case of error.

Signed-off-by: Jani Paalijarvi <jani.paalijarvi@unikie.com>
2024-06-05 12:07:02 -03:00
Eren Terzioglu
24af23e49c esp32[c3]: Add XTWDT support 2024-06-04 17:42:07 -03:00
Stuart Ianna
e3056c781e arch/risc-v/riscv_mtimer: Update the mtimecmp value once per interrupt event.
Cache the next timeout value in the drivers instance and update the mtimecmp value once. This is advantageous as the opensbi ecall to set the timer is expensive in systems which don't have the supervisor mode timer extension.
2024-06-02 09:28:19 -03:00
Ville Juven
e6973c764c riscv/syscall: Optimize user service call performance
This patch changes how user service calls are executed:
Instead of using the common interrupt logic, execute the user service
call directly.

Why? When a user makes a service call request, all of the service call
parameters are already loaded into the correct registers, thus it makes
no sense to first clobber them and then reload them, which is what the
old logic does. It is much more effective to run the system call directly.

During a user system call the interrupts must be re-enabled, which the
new logic does as soon as we know the exception is a user service call
request.

This patch does NOT change the behavior of reserved system calls (like
switch_context), only the user service call request is affected.
2024-06-01 10:40:53 -03:00
Ville Juven
a5574d9485 risc-v_percpu: Add TCB to the per CPU structure
Also, convert the type to union; we don't need the list element once
the item has been popped from the free list (the linkage is never needed
when the item is in use).
2024-06-01 10:40:53 -03:00
Ville Juven
6bad48e4c7 riscv_syscall.S: Remove duplicated code
Return from exception is common code for both system calls and
exceptions
2024-06-01 10:40:53 -03:00
Stuart Ianna
1f02c05c6d arch/litex/litex_arch_alarm: Support tickless schedular with arch alarm.
This provides an alternate tickless scheduling method, which uses the riscv
mtimer as a timebase, allowing the time and timeh registers to used
throughout an application.

The exiting tickless method, using Litex's timer0 has been left in place, as
it is a more performant option, but currently has the potential issue
identified in #11189.
2024-05-31 10:21:44 +08:00
Ville Juven
c1f3245167 riscv-v/fork.S: Fix clobbering of s0 in fork()
Value of s0 (callee-saved) must be preserved through the call, use
a0 (caller-saved) to calculate the original SP instead.
2024-05-31 02:29:48 +08:00
xuxin19
275ec7102c cmake:bugfix CMake compilation options settings should not use strings
when repeatedly enabling and disabling string-controlled configurations,
the generated toolchain configuration may be incorrect.

Signed-off-by: xuxin19 <xuxin19@xiaomi.com>
2024-05-30 10:02:10 -03:00
Jani Paalijarvi
cfa544357e mpfs_mpu: Check that size is valid for MPUCFG
The size must be power-of-two for NAPOT according to the the PMP spec.

Signed-off-by: Jani Paalijarvi <jani.paalijarvi@unikie.com>
2024-05-24 21:32:55 +08:00
Jani Paalijarvi
9d4bd915eb riscv_pmp.c: Check that size is power of two for NAPOT
The size must be power-of-two according to the the PMP spec.

Signed-off-by: Jani Paalijarvi <jani.paalijarvi@unikie.com>
2024-05-24 21:32:55 +08:00
Eren Terzioglu
ea9eea4096 esp32[c3|c6|h2]: Add MWDT1 support 2024-05-24 13:59:03 +08:00
Eren Terzioglu
aa0bb55529 esp32[c3|c6|h2]: Add RWDT support 2024-05-24 13:59:03 +08:00
Eren Terzioglu
44e118eaf2 esp32[c3]: Add RTC IRQ support 2024-05-24 13:59:03 +08:00
Yanfeng Liu
f8749ef0e0 arch/risc-v: guard tcb->name usage
Add guard for tcb->name field usage as it is not always available.

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
2024-05-22 19:06:07 +08:00
Yanfeng Liu
7db71c8ee4 ci/riscv: fix unused var in esp_twai.c
This is to fix issue in [this log](https://github.com/apache/nuttx/actions/runs/9173629303/job/25222879619):

```
Configuration/Tool: esp32c3-generic/twai esp32c6-devkitm/twai esp32c6-devkitc/twai  esp32h2-devkit/twai
Error: common/espressif/esp_twai.c:242:7: error: variable 'ret' set but not used [-Werror=unused-but-set-variable]
```

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
2024-05-22 16:40:13 +08:00
yinshengkai
20ebe0e64c Replace all asserts in kernel code with ASSERT
Signed-off-by: yinshengkai <yinshengkai@xiaomi.com>
2024-05-17 10:18:16 -03:00
Tiago Medicci Serrano
a00fbbeb9f espressif: Add option to disable the GIT_DEPTH to pull submodules
By default, submodules are cloned with `--depth=1`. This continues
to be true if `DISABLE_GIT_DEPTH` environment variable is not
defined (and it is not defined by default). But, if defined the
submodules will be fully cloned (without the `--depth` parameter).
2024-05-17 19:10:46 +08:00
Jukka Laitinen
9257af55f1 risc-v/mpfs: Change linker symbols _ssbi_ddr and _esbi_ddr into _ssbi_ram and _esbi_ram
The original names are confusing; the symbols' addresses point to the start and end of the
sbi executable ram area. This may also reside in l2lim and not in ddr, depending on the
configuration, and this is defined in the linker script.

Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
2024-05-16 17:14:43 -03:00
Tiago Medicci Serrano
8a37d1ff1c espressif: Minor changes to keep consistency between sources
This commits replicates some changes on files that were originally
written for other Espressif SoCs and inspired new implementations.
Eventually, these new implementations were improved and this commit
replicates these changes on the original sources.
2024-05-14 22:10:45 +08:00
Tiago Medicci Serrano
c412dadcb9 esp32c3/wifi: Add support for the Wi-Fi in ESP32-C3
This commit introduces support for both station and softAP modes.
2024-05-14 22:10:45 +08:00
Tiago Medicci Serrano
7ed64e7234 esp32c3: Substitute / to $(DELIM)
Substitute `/` to `$(DELIM)` to make it compatible with other
implementations.
2024-05-14 22:10:45 +08:00
Tiago Medicci Serrano
2c4963dcd6 esp32c6/wifi: Add support for the Wi-Fi in ESP32-C6
This commit introduces support for both station and softAP modes.
2024-05-14 22:10:45 +08:00
Tiago Medicci Serrano
9e8c9ea47f esp: Update libc stubs to properly acquire/release locks.
Avoid using static mutex and recursive mutex as the resource to be
acquired/release. Instead, create a specific lock for each call if
it does not exist.
2024-05-14 22:10:45 +08:00
Tiago Medicci Serrano
47b0cae778 esp/hr_timer: Fix issue with timed-out timers 2024-05-14 22:10:45 +08:00
simbit18
d1789d84e8 fix nxstyle
fix Relative file path does not match actual file.
2024-05-13 22:24:36 +02:00
Inochi Amaoto
4d2d9ecf39 arch/risc-v: fix idle stack assign order
The bc022f8cd8 introduces a static way to calculate idle stack
address for risc-v platform. However, it uses the reverse order
to access idle stack, which breaks boards with smp configuration.

Correct the idle stack order of g_cpux_idlestack.

Fixes: bc022f8cd8 ("arch/risc-v: unify idle stack calculation")
Signed-off-by: Inochi Amaoto <inochiama@outlook.com>
2024-05-12 15:22:50 +09:00
Inochi Amaoto
bc022f8cd8 arch/risc-v: remove g_cpux_idlestack
As all the board allocate idle stack from _ebss. The idle stack
layout is fix and can be computed directly by using _ebss. There
is no need to use g_cpux_idlestack array anymore, remove it.

Signed-off-by: Inochi Amaoto <inochiama@outlook.com>
2024-05-11 17:57:59 +02:00
Inochi Amaoto
afb5a66847 arch/risc-v: unify idle stack calculation
As the stack layout is unified, it is possible to
use a unify formula to calculate the top of idle
stack.

Signed-off-by: Inochi Amaoto <inochiama@outlook.com>
2024-05-11 17:57:59 +02:00
simbit18
09bfaa7292 fix nxstyle
fix Relative file path does not match actual file.
2024-05-11 01:19:06 +08:00
hujun5
5cee996588 up_putc: int up_putc, enter_critical_section may be called
before kernel has been iniitialized,we use spin_lock_irqsave to replace.

Signed-off-by: hujun5 <hujun5@xiaomi.com>
2024-05-09 13:45:02 +08:00
Inochi Amaoto
f4a38c01df arch/risc-v: Make esp32 SoCs allocate idle stack after ebss
ESP32 SoC use a static allocated array as idle stack. To fit
the existed idle stack allocation, make idle stack allocated
from ebss for the whole esp32 series.

Signed-off-by: Inochi Amaoto <inochiama@outlook.com>
2024-05-08 15:43:41 +08:00
Yanfeng Liu
ef15b5296d riscv/virt: M-mode poweroff support
This adds poweroff support to `rv-virt/nsh` and `rv-virt/nsh64`.

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
2024-05-08 15:39:26 +08:00
Yanfeng Liu
c352b04155 risc-v/sbi: add SRST extenstion usage in S-mode
This adds SBI specfication v0.3 based `riscv_sbi_system_reset()` to
support SBI firmware based system reset in kernel mode.

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
2024-05-07 21:02:49 +08:00
chenwen@espressif.com
3a9d163aae esp32_c3/pm: Fix assert issue in PM mode
1. Adjust code to avoid PM wakelock->count less than or equal to 0.
    2. Fix some document format issues.

Signed-off-by: chenwen@espressif.com <chenwen@espressif.com>
2024-05-07 15:45:32 +08:00
Inochi Amaoto
04e40182ad arch/risc-v: Make bl602 allocate idle stack after ebss
Although almost all board support allocating idle stack after ebss,
bl602 have a different memory layout for idle stack. To unify them,
make idle stack allocated from ebss for bl602.

Signed-off-by: Inochi Amaoto <inochiama@outlook.com>
2024-05-06 15:04:24 -03:00
Ville Juven
0cd5689bcb riscv/pgmap: Fix bug in kernel page directory init
The L2 table was not connected -> results in random crashes. Also add
missing data sync barrier to the end.
2024-05-03 23:49:11 +08:00
Inochi Amaoto
bd895222eb arch/risc-v: implement sbi_ipi_send
And SBI ipi support.

Fixup: 4f63ca1418 ("arch/risc-v: unfiy IPI access)
Signed-off-by: Inochi Amaoto <inochiama@outlook.com>
2024-05-02 16:08:13 +08:00
Inochi Amaoto
b283b949b6 arch/risc-v: implement standard ecall interface for nuttsbi
NuttSBI have a simple ecall interface for the kernel, which make
it hard to add new SBI call for NuttSBI. So implement standard
ecall interface for NuttSBI and make life easier.

Signed-off-by: Inochi Amaoto <inochiama@outlook.com>
2024-05-02 16:08:13 +08:00
chao an
8821a0396a arch/risc-v: correct minor issues regarding comments
The comment in riscv_vpu.S should be vector not floating

Signed-off-by: chao an <anchao@lixiang.com>
2024-04-30 17:26:57 +08:00
Eren Terzioglu
891d67bb5e esp32[c3|h2|c6]: Add support to TWAI/CANBus controller 2024-04-30 10:03:22 +08:00
Philippe Leduc
3dc6b4c9bd Add basic support for locales in order to C++ streams to build and work for simple cases (POSIX / C locale).
Fix build with C++ GCC toolchain
2024-04-29 17:34:10 +08:00
Inochi Amaoto
c148e8f2af arch/risc-v: Fix typo in riscv_set_inital_sp
Set right name for the parameter description of riscv_set_inital_sp.

Signed-off-by: Inochi Amaoto <inochiama@outlook.com>
2024-04-28 17:24:31 +08:00
Inochi Amaoto
49b3f52db1 arch/riscv/qemu-rv: replace M-mode init code with SBI in kernel build
The qemu-rv use a small init code for M mode in kernel build.
It is hard-coding and is difficult to change. Due to the fact,
introduce a already mature SBI implement (e.g OpenSBI) to
replace existing code is a better choice.

This patch introduce some change for qemu-rv:
1. use SSTC to provide time interrupt in kernel build
2. remove uncessary M mode trap.

For simplicity, this patch does not add support for booting
nuttx for any core, but force boot core to start core 0 and
let core 0 do the initialization.

Signed-off-by: Inochi Amaoto <inochiama@outlook.com>
2024-04-27 22:09:22 -03:00
Inochi Amaoto
3cabc92427 arch/risc-v: add risc-v SSTC extension support
SSTC extension allows nuttx to implement S-mode timer directly,
which is useful for starting at S-mode.

Signed-off-by: Inochi Amaoto <inochiama@outlook.com>
2024-04-27 22:09:22 -03:00
Inochi Amaoto
1d7afb571f arch/risc-v: report correct interrupt stack base
As `up_get_intstackbase` supports per cpu stack base, fix
the report value with the cpu specific one.

Signed-off-by: Inochi Amaoto <inochiama@outlook.com>
2024-04-27 22:09:22 -03:00
Inochi Amaoto
a33313413d arch/risc-v: introduce dynamic stack allocation.
It is misleading to allocate stack from static array and heap,
make all stack allocated from heap area.

Signed-off-by: Inochi Amaoto <inochiama@outlook.com>
2024-04-27 22:09:22 -03:00
Inochi Amaoto
1ef3767f85 arch/risc-v: unfiy IPI access
Add ipi process abstract function support.

Signed-off-by: Inochi Amaoto <inochiama@outlook.com>
2024-04-27 22:09:22 -03:00
chao an
1f7147129a arch/risc-v: fix break on kernel mode
merge conflicts lead to incorrect ifdef/endif scope

Signed-off-by: chao an <anchao@lixiang.com>
2024-04-26 12:44:57 +09:00
chao an
a51ebeab4b arch/risc-v: decouple Per-CPU scratch with ARCH_USE_S_MODE
In some special chipsets, multiple CPUs may be bundled in one hardware
thread cluster, which results in hartid and cpuindex not being exactly
the same. The new option will decouple Scratch-based Per-CPU storage
with S-Mode to distinguish the real cpu index.

Signed-off-by: chao an <anchao@lixiang.com>
2024-04-25 09:48:59 -03:00
chao an
da4c229312 arch/riscv: replace atomic operations to AMO
RISC-V provided fetch-and-op style atomic primitives as they scale
to highly parallel systems better than LR/SC or CAS. A simple
microarchitecture can implement AMOs using the LR/SC primitives,
provided the implementation can guarantee the AMO eventually
completes. More complex implementations might also implement AMOs
at memory controllers, and can optimize away fetching the original
value when the destination is x0.

Signed-off-by: chao an <anchao@lixiang.com>
Co-authored-by: Petro Karashchenko <petro.karashchenko@gmail.com>
2024-04-25 18:23:58 +09:00
chao an
6086b1410b arch/risc-v: remove the hard code array of cpu idle stack
Do not limit the number of CPU idle stacks by hard code

Signed-off-by: chao an <anchao@lixiang.com>
2024-04-24 11:58:19 +08:00
Yanfeng Liu
5c3fc2796b tools/export: fix names for app linker script and program entry.
This fixes names of program entry and linker script files so that to
support building kernel mode apps using CMake and export package.

flat and protected mode should be the same as before.

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
2024-04-24 11:40:16 +08:00
chao an
28044f7d5a arch/risc-v: add support of save/restore vector registers
Reference:
https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc
https://github.com/torvalds/linux/blob/master/arch/riscv/include/asm/vector.h

Signed-off-by: chao an <anchao@lixiang.com>
2024-04-23 16:18:46 -03:00
chao an
4b086f595e arch/risc-v: rename local variable name to avoid shadowed declaration
In file included from common/addrenv.h:33,
                 from common/riscv_initialstate.c:36:
common/riscv_initialstate.c: In function 'up_initial_state':
common/riscv_internal.h:136:16: warning: declaration of 'regval' shadows a previous local [-Wshadow]
  136 |      uintptr_t regval; \
      |                ^~~~~~
common/riscv_initialstate.c:74:12: note: in expansion of macro 'READ_CSR'
   74 |   regval = READ_CSR(CSR_VLENB);
      |            ^~~~~~~~
common/riscv_initialstate.c:63:13: note: shadowed declaration is here
   63 |   uintptr_t regval;
      |             ^~~~~~

Signed-off-by: chao an <anchao@lixiang.com>
2024-04-22 16:22:51 +08:00
chao an
d59f9186ca arch/risc-v: add llvm experimental extensions into command line
LLVM supports (to various degrees) a number of experimental extensions.
All experimental extensions have experimental- as a prefix. There is
explicitly no compatibility promised between versions of the toolchain,
and regular users are strongly advised not to make use of experimental
extensions before they reach ratification.

Fix compile error:
riscv64-unknown-elf-clang: error: invalid arch name 'rv64gcv_zfh_zvfh', requires '-menable-experimental-extensions' for experimental extension 'zvfh'

Signed-off-by: chao an <anchao@lixiang.com>
2024-04-19 20:13:54 +08:00
chao an
e863e3dd37 arch/risc-v: add LLVM clang support
Verified on LLVM-Metal:
$ riscv64-unknown-elf-clang --version
(LLVM-Metal 15.9.0-2023.03.0) clang version 15.9.0
Target: riscv64-unknown-unknown-elf
Thread model: posix

Signed-off-by: chao an <anchao@lixiang.com>
2024-04-19 12:27:56 +08:00
Huang Qi
93d75129de riscv: Add Vector CSRs to csr.h
The CSR register definitions from RVV 1.0 spec: https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#vector-registers

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2024-04-19 00:31:07 +08:00
Almir Okato
f4bbe276e1 esp32[c3|c6|h2]: Fix simple boot map_rom_segments
Currently Simple Boot image have fixed 2 ROM segments and
2 RAM segments, then the parsing iterator must stop when all
ROM segments are found.

Signed-off-by: Almir Okato <almir.okato@espressif.com>
2024-04-17 00:09:58 +08:00
Yanfeng Liu
200424e59d arch/risc-v: fix RV32 up_addrenv_destroy
This patch fixes the issue/12122 for RV32, where the scanning should be
limited to user space only.

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
2024-04-14 14:49:36 +08:00
Jakub Janousek
3ce84d1ba0 arch and board esp32c3-legacy: Add optional iCE40 FPGA loading support
Signed-off-by: Jakub Janousek <janouja9@fel.cvut.cz>
2024-04-12 10:19:58 -03:00
Inochi Amaoto
412d2ce113 arch/riscv: add T-HEAD CSR mapping
Add T-HEAD CSR mapping file.

Signed-off-by: Inochi Amaoto <inochiama@outlook.com>
2024-04-11 22:20:39 +08:00
Inochi Amaoto
bae686e127 arch/riscv: force using encoding macro for CSR access
Using CSR name depends on compiler support heavily, but CSR
encoding does not have this problem. It also make it easy to
add new CSR support even if the compiler does not support.

Unify CSR access by using the CSR encoding macro.

Signed-off-by: Inochi Amaoto <inochiama@outlook.com>
2024-04-11 10:43:48 +08:00
Huang Qi
9e78b235fe riscv: Add more debug related CSR definitions
This patch adds more debug related CSR definitions
to arch/risc-v/include/csr.h.

These definitions are from the RISC-V Debug Specification
Version 1.0 rc1 (https://github.com/riscv/riscv-debug-spec).

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2024-04-10 21:10:39 +08:00
ligd
3844efb5b8 stack: update up_get_intstackbase API to support cpu id
For crash dump all the CPU intstack

Signed-off-by: ligd <liguiding1@xiaomi.com>
2024-04-09 16:59:00 -03:00
simbit18
9967989b02 Fix Kconfig style
Remove spaces from Kconfig files
Remove TABs
Add comments
2024-04-09 10:49:23 +08:00
Eren Terzioglu
c0d7419d11 esp32[c3|h2|c6]: Bugfixes for filesystem errors 2024-04-09 10:48:40 +08:00
W-M-R
0ede3fc377 kasan: Implementing global variable out of bounds detection
Extracting global variable information using scripts:
kasan_global.py:
1. Extract the global variable information provided by the -- param asan globals=1 option
2. Generate shadow regions for global variable out of bounds detection
Makefile:
1. Implement multiple links, embed the shadow area into the program, and call it by the Kasan module

Signed-off-by: W-M-R <mike_0528@163.com>
2024-04-07 23:31:13 +08:00
Tiago Medicci Serrano
65bd548521 esp32[c3|c6|h2]: Fix RTC data placement
RTC data was not being correctly placed on RTC's memory data due to
linker issues. Also, the image's RTC memory segment was not being
properly parsed by the bootloader.
2024-04-05 02:50:19 +08:00
Eren Terzioglu
19b58a78da risc-v/espressif: Fix empty cpuint number 2024-04-02 16:40:24 -03:00
Tiago Medicci Serrano
9520edeb16 espressif/rmt: Fix minor issues regarding formatting and comments
This commit only fix minor issues regarding formatting and comments
2024-04-02 14:50:59 -03:00
Yanfeng Liu
3a59644485 build/cmake: kernel mode revision
This fixes kernel mode regression caused by #12011

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
2024-03-30 12:21:59 +08:00
xuxin19
741de4b450 cmake:init protected-mode for CMake build
adjust link options for userspace elf
specify system libs and apps lib to only link with nuttx target in flat build mode

Signed-off-by: xuxin19 <xuxin19@xiaomi.com>
2024-03-27 23:01:08 +08:00
Eren Terzioglu
f5030573b7 esp32[c3|c6|h2]: Fix filesystem test support 2024-03-26 20:56:48 +08:00
Eren Terzioglu
d322140464 boards/esp32c6: Add esp32c6 DevKitM board support 2024-03-26 09:43:08 +08:00
Eren Terzioglu
cfcedab76b arch/espressif: Fix esp32c6 strange characters on boot 2024-03-26 09:39:12 +08:00
Yanfeng Liu
56b125bb82 risc-v/arch.h: revising comments
This revises comments about page tables to help understanding.

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
2024-03-25 20:39:24 +08:00
Jukka Laitinen
1f6079814a arch/risc-v/src/common/supervisor/riscv_perform_syscall.c: Record the currently running task in risc-v syscall
If a context switch occurs in syscall, the g_running_task need to be recorded for assert logic.
This copies the logic from arm platforms

Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
2024-03-21 18:45:41 +08:00