the author has submitted the CLA and the license can be migrated to ASF
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
both co-authors have submitted the CLA and the license can be migrated to ASF
Co-authored-by: Dong Heng <dongheng@espressif.com>
Co-authored-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
Fix CMake-based build system to include the toolchain's libm only
when `CONFIG_LIBM_TOOLCHAIN` is selected. Before this commit, if
the user selected `CONFIG_LIBM_NEWLIB`, for instance, the build
system would still link the toolchain's libm functions instead of
the ones provided by newlib.
reason:
up_set_current_regs initially had two functions:
1: To mark the entry into an interrupt state.
2: To record the context before an interrupt/exception. If we switch to a new task, we need to store the upcoming context regs by calling up_set_current_regs(regs).
Currently, we record the context in other ways, so the second function is obsolete. Therefore, we need to rename up_set_current_regs to better reflect its actual meaning, which is solely to mark an interrupt.
Signed-off-by: hujun5 <hujun5@xiaomi.com>
CC: mqueue.c common/riscv_exit.c: In function 'up_exit':
common/riscv_exit.c:65:33: error: 'tcb' undeclared (first use in this function); did you mean 'tcb_s'?
65 | g_running_tasks[this_cpu()] = tcb;
| ^~~
| tcb_s
Signed-off-by: hujun5 <hujun5@xiaomi.com>
Most tools used for compliance and SBOM generation use SPDX identifiers
This change brings us a step closer to an easy SBOM generation.
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
reason:
simplify context switch
sys_call0(SYS_switch_context)
sys_call0(SYS_restore_context)
size nuttx
before
text data bss dec hex filename
148021 921 26944 175886 2af0e nuttx
after
text data bss dec hex filename
147995 921 26928 175844 2aee4 nuttx
size reduce -42
Signed-off-by: hujun5 <hujun5@xiaomi.com>
Inter-processor interrupts (IPIs) are not cleared via mie/mip registers but
rather, at the MPFS_CLINT_BASE + mhartid * 4 (a word or 4-byte offset for
each hart).
If there's an IPI waiting, the system will continue to boot altough it's
expected to stay at the wfi loop waiting for the IPI.
Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
This CONFIG_MPFS_CLKINIT is set with bootloaders by default. However,
this gives an option to have it unset. In some cases, the clocks
may be already set so it becomes unnecessary to re-initialize them.
Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
From the RISV-V Privileged Spec v1.10 (3.1.14 MIP/MIE):
Only the bits corresponding to lower-privilege software interrupts
(USIP, SSIP), timer interrupts (UTIP, STIP), and external interrupts
(UEIP, SEIP) in mip are writable through this CSR address; the
remaining bits are read-only.
Thus, it is futile to write to the M-mode status bit via the CSR, only
access via RISCV_IPI is valid.
reason:
1: spin_lock_init and spin_initialize have similar functionalities.
2: spin_lock and spin_unlock should be called in matching pairs.
Signed-off-by: hujun5 <hujun5@xiaomi.com>
profile-generate is used to generate compilation feedback optimization data, not just code coverage data
It will rely on the toolchain library:
nuttx/libs/libc/misc/lib_utsname.c:94:(.text.uname+0x2c): undefined reference to `__gcov_indirect_call_profiler_v4'
arm-none-eabi-ld: nuttx/libs/libc/misc/lib_utsname.c:113:(.text.uname+0x178): undefined reference to `__gcov_indirect_call'
arm-none-eabi-ld: nuttx/libs/libc/misc/lib_utsname.c:113:(.text.uname+0x188): undefined reference to `__gcov_time_profiler_counter'
arm-none-eabi-ld: nuttx/staging/libc.a(lib_utsname.o):(.data..LPBX0+0x30): undefined reference to `__gcov_merge_time_profile'
Signed-off-by: yinshengkai <yinshengkai@xiaomi.com>
Add function description for function prototype of `riscv_jump_to_user`
to make it easier to read, and fix some inconsistent comment style in
`riscv_internal.h`.
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
reason:
When entering an exception or interrupt, there are two sets of registers:
one is the "running regs", which we need to save,
and the other is the "ready to running regs", which we may soon use.
For consistency in logic, we can always store the "running regs" in the regs field of g_running_tasks,
otherwise it may lead to errors in the storage location of the "running regs."
When we need to access the "running regs," we should uniformly retrieve them from the regs field of g_running_tasks.
As the next step, we will rename the set_current_regs/up_current_regs functions
for each architecture to more appropriate names, solely for the purpose of identifying interrupts.
Signed-off-by: hujun5 <hujun5@xiaomi.com>
In https://github.com/apache/nuttx/pull/13044,
LIBC_ARCH_ATOMIC was finally removed.
Howerver, the following chips still have the config.
- ARCH_CHIP_ESP32S3
- ARCH_CHIP_ESP32C3_GENERIC
- ARCH_CHIP_ESP32H2
This commit fixes the issue.
`ARCH_HAVE_RAMFUNCS` has no actual effect on the ESP32-C3,
but ESP32-C3 has RAM functions, so select it to mark that is OK,
and then we can also suppress the RWX memory region warning.
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
Suppress the warning message "nuttx has a LOAD segment with RWX permissions" in case of RAM boot mode is selected.
RAM MODE: BOOT_RUNFROMEXTSRAM/BOOT_RUNFROMISRAM/BOOT_RUNFROMSDRAM/BOOT_COPYTORAM
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
There is an enormous error in the system call dispatch logic; if a task
is inside a critical section (local interrupts disabled) there is a chance
that during a context switch when the task resumes, local interrupts are
erroneously ENABLED. This obviously leads to unexpected crashes and such.
This happens when the CPU status has Previous Interrupt Enable (PIE) set
to 1, even though Interrupt Enable (IE) is set to 0.
When the system call returns via ERET, the CPU sets PIE->IE and if PIE=1
interrupts get enabled.
This is fixed easily by explicitly CLEARING PIE from the register save
area, if IE=0 when the system call was started.
This patch fixed userspace headers conflict. Architecture-related definition and API should not be exposed to users.
Signed-off-by: ouyangxiangzhen <ouyangxiangzhen@xiaomi.com>
reason:
Replace "inline" with "inline_function" for "up_interrupt_context" to ensure consistency with other arch
Signed-off-by: hujun5 <hujun5@xiaomi.com>
1. CONFIG_ARCH_COVERAGE has been replaced by CONFIG_SCHED_GCOV
2. Delete the SIM-specific GCOV_ALL configuration and change it to a universal configuration for all architectures
Signed-off-by: wangmingrong1 <wangmingrong1@xiaomi.com>
