1. cmake uses clang++ as a connector, and does not currently support:
clang++: error: unknown argument: '-wl,--print-memory-usage'
clang++: error: no input files
Signed-off-by: wangmingrong1 <wangmingrong1@xiaomi.com>
1. enable CONFIG_BUILTIN_COMPILER_RT to built libclang_rt.builtins-xxx.a and no longer use the compiler's built-in
2. Modify clang version acquisition to get two decimal points
3. It has been ported to support four architectures: ARM, ARM64, RISCV, and x86_64, among which ARM has been validated
Signed-off-by: wangmingrong1 <wangmingrong1@xiaomi.com>
User may set CONFIG_MM_REGIONS=1 on purpose to disable CCM.
This is a completely normal system config and should not be treated as error.
I found this problem trying to run Renode with stm32f4discovery/nsh but
Renode doesn't support CCM so we have to disable it
If the core id needs to be included in the hardware register
calculation, up_cpu_index() should be used instead of this_cpu().
Signed-off-by: chao an <anchao@lixiang.com>
1. Enable timer and irq finally to make sure timer callback was already
registered. When the CPU resets, the values of some generic timer
registers are undefined. Enabling the timer interrupt in advance may
cause the timer to trigger early while the timer callback is not yet
registered. This results in the timer ISR being executed, which masks
the timer interrupt. Since the timer callback is not registered at
this point, the timer interrupt is not unmasked, further causing the
system scheduler to hang.
2. Remove timer mask for one-shot timer and that's in isr,
irq/fiq is disabled. Masking generic timer is not necessary, and it
may introduce risks, otherwise, mask/unmask must be pair in all
situations.
Signed-off-by: Jinliang Li <lijinliang1@lixiang.com>
1. init HSCTLR to enable i-cache/d-cache for EL2
2. init HACTLR to enable all access to implementation defined
registers for EL1.
3. add dsb/isb before switch to EL1 from EL2
Signed-off-by: Jinliang Li <lijinliang1@lixiang.com>
Commit 313d6df7 caused the following build error:
CC: fixedmath/lib_b16atan2.c chip/sam_qspi.c: In function 'qspi_memory':
chip/sam_qspi.c:1552:7: warning: implicit declaration of function 'IS_ALIGNED' [-Wimplicit-function-declaration]
1552 | IS_ALIGNED((uintptr_t)meminfo->buffer, 4) &&
| ^~~~~~~~~~
In file included from chip/sam_qspi.c:41:
chip/sam_qspi.c: In function 'qspi_alloc':
chip/sam_qspi.c:1591:21: warning: implicit declaration of function 'ALIGN_UP' [-Wimplicit-function-declaration]
1591 | return kmm_malloc(ALIGN_UP(buflen, 4));
This was caused by missing include of nuttx.h header defining ALIGN_UP
and IS_ALIGNED.
Signed-off-by: Michal Lenc <michallenc@seznam.cz>
Add --no-warn-rwx-segments in case of RAM boot mode to linker to
suppress the below warning:
"nuttx has a LOAD segment with RWX permissions"
Signed-off-by: Jinliang Li <lijinliang1@lixiang.com>
Summary
add memory map for DDR region
fix arm-v7a/knsh boot dataabort on arm_addrenv_utils.c first time memset
after arm_pgvaddr.
Signed-off-by: qinwei1 <qinwei1@xiaomi.com>
that pr requires chip turn on CONFIG_DRIVERS_BLUETOOTH to use bluetooth,
but not all defconig enable this option, so let's map bt_driver_register
to bt_netdev_register in header file in this case, and revert the unnessary
change in the related chip and board folders.
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
When sig dispatch do up_schedule_sigaction, need to make a new frame to
run arm_sigdeliver. But the exception_direct cannot handle xcp.regs as
we are using c-function exception handler.
Need to use exception_common to handle SMP call.
Signed-off-by: buxiasen <buxiasen@xiaomi.com>
Implement PIC loading in armv8-m qemu,
for example: load address-independent AP ELF in the bootloader,
and the text segment in AP ELF is XIP,
no need to apply for memory and modify it.
Two config:
bootloader abbreviation bl:
use romfs to load ap elf, use the boot command to parse and jump to ap
application abbreviation ap:
run os test
We need to compile ap first, then compile bl.
compile step:
./tools/configure.sh mps3-an547:ap
make -j20
mkdir -p pic
cp boot pic/.
genromfs -a 128 -f ../romfs.img -d pic
make distclean -j20
./tools/configure.sh mps3-an547:bl
make -j20
run qemu:
qemu-system-arm -M mps3-an547 -m 2G -nographic -kernel nuttx.bin \
-gdb tcp::1127 -device loader,file=../romfs.img,addr=0x60000000
nsh> boot /etc/boot
ap> ostest
Signed-off-by: anjiahao <anjiahao@xiaomi.com>
Need to start up a new to setup special registers use
`arm_pic_setupxcp`.
Note that CONFIG_BUILD_PIC compiles the entire NuttX image
as position-independent(PIC), enable CONFIG_PIC to load PIC
application code.
Signed-off-by: anjiahao <anjiahao@xiaomi.com>
Added a flash driver for the STM32G4 series. The primary change here is
the addition of stm32g4xxx_flash.c. This file uses the STM32L4 flash
driver as a template. The primary difference is the accounting for dual
banks with different page sizes.
Fixed error while building b-g474e-dpow1/buckboost. It was possible (technically) to have page be used uninitialzied. Changing the if statement to default to using a flash_page_size == 2048 fixes this issue.
In armv8m the FPSCR[18:16] LTPSIZE field must be set to 0b100 for
"Tail predication not applied" as it's reset value.
Signed-off-by: zhangyuan29 <zhangyuan29@xiaomi.com>
