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ec079bd866
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UART Input works OK yay!
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2023-12-05 13:34:04 +08:00 |
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2e98ebdeba
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Update doc
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2023-12-05 13:08:36 +08:00 |
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c3db75fec4
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Update doc
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2023-12-05 13:01:03 +08:00 |
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55ab5fbea9
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Update doc
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2023-12-05 12:58:28 +08:00 |
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54a2c7952e
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Update doc
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2023-12-05 11:58:56 +08:00 |
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4256fbbf5b
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Update doc
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2023-12-05 11:48:49 +08:00 |
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c86de609a0
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Update doc
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2023-12-05 10:25:14 +08:00 |
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0b4cd53914
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Update doc
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2023-12-05 10:24:33 +08:00 |
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eab8c98a0e
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Update doc
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2023-12-05 09:33:02 +08:00 |
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c1b8727c4d
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Update doc
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2023-12-05 09:20:08 +08:00 |
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15a9e29ad7
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Add article
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2023-12-03 08:02:19 +08:00 |
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12c3d4c38d
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Add article
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2023-12-03 07:54:53 +08:00 |
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1f67be34d4
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Update doc
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2023-12-02 16:59:41 +08:00 |
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0582457f65
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Update doc
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2023-12-02 16:54:51 +08:00 |
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eb1862d27b
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Update doc
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2023-12-01 14:37:23 +08:00 |
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10a5e7a170
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Update doc
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2023-12-01 00:16:08 +08:00 |
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11e2e2f912
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Can't disable MMU. EXCEPTION: Illegal instruction. MCAUSE: 0000000000000002, EPC: 0000000050400112, MTVAL: 0000000000000000
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2023-11-26 14:55:08 +08:00 |
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95f7e90e60
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Disable and re-enable MMU. before1=0, before2=0, after1=1, after2=0
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2023-11-26 14:41:10 +08:00 |
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00137d34be
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Disable and re-enable MMU. before1=0, before2=0, after1=1, after2=0
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2023-11-26 14:40:18 +08:00 |
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c1f38bc937
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Can't set SO Bit because of MXSTATUS
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2023-11-26 14:31:34 +08:00 |
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abad3d01ed
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Can't set SO Bit because of MXSTATUS
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2023-11-26 13:50:05 +08:00 |
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8f81996f49
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Update doc
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2023-11-26 09:59:20 +08:00 |
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c6bae539d1
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Update doc
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2023-11-26 09:45:57 +08:00 |
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62bd627de5
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Update doc
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2023-11-26 09:44:36 +08:00 |
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33eca90ec1
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Update doc
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2023-11-26 09:43:09 +08:00 |
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c1a440491e
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Update doc
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2023-11-26 08:41:07 +08:00 |
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63e0718793
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After MMU Init: before1=0, before2=0, after1=0, after2=0
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2023-11-26 08:29:09 +08:00 |
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574d376e4e
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Before MMU Init: before1=0, before2=0, after1=1, after2=0
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2023-11-26 08:24:26 +08:00 |
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2a44285514
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Add article
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2023-11-26 07:57:36 +08:00 |
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bdb6f8beeb
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Set PLIC Interrupt Priority in RISC-V Assembly. Same problem
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2023-11-25 19:10:00 +08:00 |
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eaaf1fbce8
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sfence doesn't help
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2023-11-25 13:44:53 +08:00 |
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dddaae8de8
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Update doc
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2023-11-25 13:16:13 +08:00 |
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92d6b0175a
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Update doc
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2023-11-25 13:11:52 +08:00 |
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a42f3e4005
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Test the setting of PLIC Interrupt Priority. Doesn't seem right
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2023-11-25 13:11:01 +08:00 |
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51745bea6a
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Update doc
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2023-11-25 12:17:08 +08:00 |
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6278a647ef
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Clear Pending Interrupts. Responds to keypress yay!
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2023-11-25 11:51:18 +08:00 |
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1326447727
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Update doc
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2023-11-25 08:47:36 +08:00 |
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cdede49c39
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Update doc
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2023-11-25 08:46:40 +08:00 |
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648b8def7a
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Update doc
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2023-11-25 08:06:57 +08:00 |
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661146955b
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Claim the Interrupt at startup. Still the same: riscv_dispatch_irq: irq=25, claim=0
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2023-11-25 07:58:19 +08:00 |
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0f100267a8
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Update doc
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2023-11-25 07:49:32 +08:00 |
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2deef1da75
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Claim not working
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2023-11-25 00:16:13 +08:00 |
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74e2b2bfab
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Claim not working
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2023-11-25 00:08:07 +08:00 |
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cc6d203e4b
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Handle Interrupt Pending. riscv_dispatch_irq: Do irq=45
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2023-11-25 00:04:05 +08:00 |
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46a1803f1b
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Update doc
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2023-11-24 22:44:07 +08:00 |
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4ec00371e4
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Log PLIC Interrupt Pending. Interrupt Pending is set!
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2023-11-24 22:43:09 +08:00 |
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44833f6812
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Enable UART IRQ. riscv_dispatch_irq: irq=25, claim=0
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2023-11-24 22:27:38 +08:00 |
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c2a12e2672
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Don't log IRQ 25. Hangs at NuttShell
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2023-11-24 21:32:33 +08:00 |
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6cd204cd62
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Repeated riscv_dispatch_irq: irq=25. Yay!
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2023-11-24 21:21:13 +08:00 |
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b901991789
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Repeated riscv_dispatch_irq: irq=25. Yay!
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2023-11-24 20:54:47 +08:00 |
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