Commit graph

23259 commits

Author SHA1 Message Date
Alin Jerpelea
7693764f34 arch/misoc: migrate to SPDX identifier
Most tools used for compliance and SBOM generation use SPDX identifiers
This change brings us a step closer to an easy SBOM generation.

Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
2024-12-02 22:43:23 +08:00
Alin Jerpelea
35ff0d834e arch/or1k: migrate to SPDX identifier
Most tools used for compliance and SBOM generation use SPDX identifiers
This change brings us a step closer to an easy SBOM generation.

Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
2024-12-02 22:43:23 +08:00
wangmingrong1
9555f9ff55 arm64/mte: Add support for arm64 mte
For details, please refer to the kernel's introduction to this at "https://docs.kernel.org/arch/arm64/memory-tagging-extension.html" and Android's introduction to this at "https://source.android.com/docs/security/test/memory-safety/arm-mte"

Of course, there is also the following detailed principle introduction
https://developer.arm.com/-/media/Arm%20Developer%20Community/PDF/Arm_Memory_Tagging_Extension_Whitepaper.pdf

The modification of this patch is only to merge the simplest MTE function support. In the future, the MTE function will be integrated into the kernel to a greater extent, for example, hardware MTE Kasan will be supported in the future.

Signed-off-by: wangmingrong1 <wangmingrong1@xiaomi.com>
2024-12-02 11:04:11 -03:00
wangmingrong1
1e32122709 arm64/qemu: Add support for arm64 qemu's maximum feature cpu
Signed-off-by: wangmingrong1 <wangmingrong1@xiaomi.com>
2024-12-02 11:04:11 -03:00
hujun5
64c3e972a0 fix compile error
CC:  mqueue.c common/riscv_exit.c: In function 'up_exit':
common/riscv_exit.c:65:33: error: 'tcb' undeclared (first use in this function); did you mean 'tcb_s'?
   65 |   g_running_tasks[this_cpu()] = tcb;
      |                                 ^~~
      |                                 tcb_s

Signed-off-by: hujun5 <hujun5@xiaomi.com>
2024-12-02 20:50:21 +08:00
hujun5
cc96289e2d xtensa: syscall SYS_switch_context and SYS_restore_context use 0 para
reason:
simplify context switch
sys_call0(SYS_switch_context)
sys_call0(SYS_restore_context)

size nuttx

before
   text    data     bss     dec     hex filename
 187620    1436  169296  358352   577d0 nuttx
after
   text    data     bss     dec     hex filename
 187576    1452  169280  358308   577a4 nuttx

size reduce -44

Signed-off-by: hujun5 <hujun5@xiaomi.com>
2024-12-02 20:05:05 +08:00
Michal Lenc
9fbb81e8a4 samv7: fix bytes to words calculation in user signature read
EEFC read sequence requires read length in words instead of bytes,
therefore bytes given by the user has to be recalculated to words.
The calculation however had a mistake in brackets and was just adding
1 to buflen instead of recalculating it to 4 byte words. This caused
global array g_page_buffer to overflow for some reads.

This fixes the calculation.

Signed-off-by: Michal Lenc <michallenc@seznam.cz>
2024-12-02 19:47:43 +08:00
hujun5
400239877d risc-v: remove g_running_tasks[this_cpu()] = NULL
reason:
We hope to keep g_running_tasks valid forever.

Signed-off-by: hujun5 <hujun5@xiaomi.com>
2024-12-02 17:41:16 +08:00
Alin Jerpelea
19e42a8978 arch/tricore: migrate to SPDX identifier
Most tools used for compliance and SBOM generation use SPDX identifiers
This change brings us a step closer to an easy SBOM generation.

Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
2024-12-02 17:23:25 +08:00
Alin Jerpelea
3013ff9ba9 arch/renesas: migrate to SPDX identifier
Most tools used for compliance and SBOM generation use SPDX identifiers
This change brings us a step closer to an easy SBOM generation.

Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
2024-12-02 17:23:25 +08:00
Alin Jerpelea
3dde10adaa arch/risk-v: migrate to SPDX identifier
Most tools used for compliance and SBOM generation use SPDX identifiers
This change brings us a step closer to an easy SBOM generation.

Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
2024-12-02 17:23:25 +08:00
Alin Jerpelea
eea3d77a6e arch/sim: migrate to SPDX identifier
Most tools used for compliance and SBOM generation use SPDX identifiers
This change brings us a step closer to an easy SBOM generation.

Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
2024-12-02 17:23:25 +08:00
Alin Jerpelea
7d3fe64a6a arch/sparc: migrate to SPDX identifier
Most tools used for compliance and SBOM generation use SPDX identifiers
This change brings us a step closer to an easy SBOM generation.

Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
2024-12-02 17:23:25 +08:00
Alin Jerpelea
b6a32301ee arch/x86: migrate to SPDX identifier
Most tools used for compliance and SBOM generation use SPDX identifiers
This change brings us a step closer to an easy SBOM generation.

Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
2024-12-02 17:23:25 +08:00
Alin Jerpelea
5e0347b20a arch/x86_64: migrate to SPDX identifier
Most tools used for compliance and SBOM generation use SPDX identifiers
This change brings us a step closer to an easy SBOM generation.

Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
2024-12-02 17:23:25 +08:00
Alin Jerpelea
8d50457dfc arch/xtensa: migrate to SPDX identifier
Most tools used for compliance and SBOM generation use SPDX identifiers
This change brings us a step closer to an easy SBOM generation.

Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
2024-12-02 17:23:25 +08:00
Alin Jerpelea
b3e1e21c65 arch/z16: migrate to SPDX identifier
Most tools used for compliance and SBOM generation use SPDX identifiers
This change brings us a step closer to an easy SBOM generation.
2024-12-02 17:23:25 +08:00
Alin Jerpelea
99d8641cdd arch/z80: migrate to SPDX identifier
Most tools used for compliance and SBOM generation use SPDX identifiers
This change brings us a step closer to an easy SBOM generation.
2024-12-02 17:23:25 +08:00
hujun5
3c32517b94 riscv: syscall SYS_switch_context and SYS_restore_context use 0 para
reason:
simplify context switch
sys_call0(SYS_switch_context)
sys_call0(SYS_restore_context)

size nuttx
before
   text    data     bss     dec     hex filename
 148021     921   26944  175886   2af0e nuttx

after
   text    data     bss     dec     hex filename
 147995     921   26928  175844   2aee4 nuttx

size reduce -42

Signed-off-by: hujun5 <hujun5@xiaomi.com>
2024-12-02 14:44:37 +08:00
hujun5
8b46a4d916 lc823450_usbdev: use small lock in arch/arm/src/lc823450/lc823450_usbdev.c
Signed-off-by: hujun5 <hujun5@xiaomi.com>
2024-12-02 13:35:14 +08:00
hujun5
c116b6578a max32660_wdt: use small lock in arch/arm/src/max326xx/max32660/max32660_wdt.c
reason:
we plan to remove all instances of spin_lock_irqsave(NULL)

Signed-off-by: hujun5 <hujun5@xiaomi.com>
2024-12-02 13:34:53 +08:00
hujun5
a0420df332 xtensa: remove g_running_tasks[this_cpu()] = NULL
reason:
We hope to keep g_running_tasks valid forever.

Signed-off-by: hujun5 <hujun5@xiaomi.com>
2024-12-02 13:29:59 +08:00
hujun5
30940d9251 imxrt_serial: use small lock in arch/arm/src/imxrt/imxrt_serial.c
Signed-off-by: hujun5 <hujun5@xiaomi.com>
2024-12-01 18:02:10 +08:00
wangjianyu3
074c494f8f nrf91: Support using different nbuffer for each topic
Signed-off-by: wangjianyu3 <wangjianyu3@xiaomi.com>
2024-11-30 14:10:57 +08:00
hujun5
ab0fb80e2b arm64: change some format
fix the comment in https://github.com/apache/nuttx/pull/14980

Signed-off-by: hujun5 <hujun5@xiaomi.com>
2024-11-30 03:15:54 +08:00
hujun5
74dfcdfbd6 cxd56xx: use small lock in arch/arm/src/cxd56xx/cxd56_clock.c
Signed-off-by: hujun5 <hujun5@xiaomi.com>
2024-11-30 03:15:02 +08:00
Eero Nurkkala
53f4216977 risc-v/mpfs: clear IPIs at boot
Inter-processor interrupts (IPIs) are not cleared via mie/mip registers but
rather, at the MPFS_CLINT_BASE + mhartid * 4 (a word or 4-byte offset for
each hart).

If there's an IPI waiting, the system will continue to boot altough it's
expected to stay at the wfi loop waiting for the IPI.

Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
2024-11-30 03:14:10 +08:00
Eero Nurkkala
e111c9a256 risc-v/mpfs: introduce CONFIG_MPFS_CLKINIT flag
This CONFIG_MPFS_CLKINIT is set with bootloaders by default. However,
this gives an option to have it unset. In some cases, the clocks
may be already set so it becomes unnecessary to re-initialize them.

Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
2024-11-30 03:14:10 +08:00
buxiasen
7a4fac0df6 coredump: add BOARD_CRASHDUMP_CUSTOM support
For only board specific crashdump and no syslog/blk/mtd coredump

Signed-off-by: buxiasen <buxiasen@xiaomi.com>
2024-11-30 03:08:35 +08:00
hujun5
321419491e missing update running_task
This commit fixes the regression from https://github.com/apache/nuttx/pull/14865

Signed-off-by: hujun5 <hujun5@xiaomi.com>
2024-11-30 02:48:58 +08:00
hujun5
635da96bae xtensa: remove up_set_current_regs/up_current_regs
reason:
up_set_current_regs initially had two functions:

1: To mark the entry into an interrupt state.
2: To record the context before an interrupt/exception. If we switch to a new task, we need to store the upcoming context regs by calling up_set_current_regs(regs).

Currently, we record the context in other ways, so the second function is obsolete. Therefore, we need to rename up_set_current_regs to better reflect its actual meaning, which is solely to mark an interrupt.

Signed-off-by: hujun5 <hujun5@xiaomi.com>
2024-11-30 02:48:58 +08:00
wangmingrong1
137ca05249 arm64/toolchain: Cmake alignment makefile writing
They should be a relationship of choice:
ifeq ($(CONFIG_ARCH_CORTEX_A53),y)
  ARCHCPUFLAGS += -mcpu=cortex-a53
else ifeq ($(CONFIG_ARCH_CORTEX_A55),y)
  ARCHCPUFLAGS += -mcpu=cortex-a55
else ifeq ($(CONFIG_ARCH_CORTEX_A57),y)
  ARCHCPUFLAGS += -mcpu=cortex-a57
else ifeq ($(CONFIG_ARCH_CORTEX_A72),y)
  ARCHCPUFLAGS += -mcpu=cortex-a72
else ifeq ($(CONFIG_ARCH_CORTEX_R82),y)
  ARCHCPUFLAGS += -mcpu=cortex-r82
else ifeq ($(CONFIG_ARCH_ARMV8A),y)
  ARCHCPUFLAGS += -march=armv8-a
else ifeq ($(CONFIG_ARCH_ARMV8R),y)
  ARCHCPUFLAGS += -march=armv8-r
endif

Signed-off-by: wangmingrong1 <wangmingrong1@xiaomi.com>
2024-11-29 18:37:21 +08:00
chao an
8257b11944 arm/isr: move up_set_interrupt_context() to chip define
up_set_interrupt_context() is chip specific implement, move this function to correct place

Signed-off-by: chao an <anchao@lixiang.com>
2024-11-29 18:37:08 +08:00
hujun5
d89f22eb98 arm64: remove g_running_tasks[this_cpu()] = NULL
reason:
We hope to keep g_running_tasks valid forever.

Signed-off-by: hujun5 <hujun5@xiaomi.com>
2024-11-29 10:04:50 +01:00
Jouni Ukkonen
1bfe8bcf71 arch/arm64/imx9: Boot, move mmu init to correct place
MMU init must be after ddrinit.

Signed-off-by: Jouni Ukkonen <jouni.ukkonen@unikie.com>
2024-11-29 10:03:28 +01:00
simbit18
9c9b945876 fix nxstyle
Removed extra spaces from .h and .c files
2024-11-28 20:40:13 +08:00
YAMAMOTO Takashi
388ab6c2db esp32s3: don't clear pending interrupts on eg. up_putc
Fixes https://github.com/apache/nuttx/issues/14872
2024-11-28 19:00:21 +08:00
hujun5
0bba53ce12 remove redundant scheduling records
reason:
Since the scheduling records have already been moved to the interrupt exit in this submission,
we need to delete the original records' locations.
This commit fixes the regression from https://github.com/apache/nuttx/pull/13651

Signed-off-by: hujun5 <hujun5@xiaomi.com>
2024-11-28 18:56:13 +08:00
guoshichao
a2fcd9862c nuttx/arch: remove the custom board check in up_testset implementation
the up_testset implementation is common code, should not add custom
board check

Signed-off-by: guoshichao <guoshichao@xiaomi.com>
2024-11-28 15:06:57 +08:00
Jouni Ukkonen
6b38b83331 arch/arm64/imx9: Clear DMA channel interrupts on init
Avoid spurious interrupts on reboot

Signed-off-by: Jouni Ukkonen <jouni.ukkonen@unikie.com>
2024-11-28 15:02:15 +08:00
Jouni Ukkonen
1d23baaa63 arch/arm64/imx9/imx9_flexspi: Replace memcpy by while loop
libc memcpy cannot access fspi memory space correctly
remove unnecessary debugassert and cache operations

Signed-off-by: Jouni Ukkonen <jouni.ukkonen@unikie.com>
2024-11-28 15:00:33 +08:00
simbit18
0476895c0d fix nxstyle
Remove TABs
2024-11-28 09:14:49 +08:00
Ville Juven
51171d66f2 riscv/riscv_ipi.h: Do not write to CSR_MIP.MSIP as it is read-only
From the RISV-V Privileged Spec v1.10 (3.1.14 MIP/MIE):

Only the bits corresponding to lower-privilege software interrupts
(USIP, SSIP), timer interrupts (UTIP, STIP), and external interrupts
(UEIP, SEIP) in mip are writable through this CSR address; the
remaining bits are read-only.

Thus, it is futile to write to the M-mode status bit via the CSR, only
access via RISCV_IPI is valid.
2024-11-28 09:14:07 +08:00
p-szafonimateusz
eca40ff053 arch/x86_64/intel64: re-enable interrupts before syscall handle
arch/x86_64/intel64: re-enable interrupts before syscall handle
2024-11-27 13:32:23 -03:00
p-szafonimateusz
908ac756ea arch/x86_64/intel64: remove unnecessary nested syscalls logic
remove unnecessary nested syscalls logic, it's already handled different way
2024-11-27 13:32:23 -03:00
p-szafonimateusz
e7d6f2c044 arch/x86_64/intel64_irq.c: remove some magic numbers
arch/x86_64/intel64_irq.c: remove some magic numbers

Signed-off-by: p-szafonimateusz <p-szafonimateusz@xiaomi.com>
2024-11-27 13:32:23 -03:00
p-szafonimateusz
e95ea6fbc4 arch/x86_64: handle TLB shootdown
arch/x86_64: handle TLB shootdown

Signed-off-by: p-szafonimateusz <p-szafonimateusz@xiaomi.com>
2024-11-27 13:32:23 -03:00
p-szafonimateusz
ce22c28e88 arch/x86_64: add kernel stack support
arch/x86_64: add kernel stack support

Signed-off-by: p-szafonimateusz <p-szafonimateusz@xiaomi.com>
2024-11-27 13:32:23 -03:00
p-szafonimateusz
712e8d9cc7 arch/x86_64: add kernel build support
arch/x86_64: add kernel build support

Signed-off-by: p-szafonimateusz <p-szafonimateusz@xiaomi.com>
2024-11-27 13:32:23 -03:00
p-szafonimateusz
8702fbef8d arch/x86_64/include/intel64/arch.h: align definitions
arch/x86_64/include/intel64/arch.h: align definitions

Signed-off-by: p-szafonimateusz <p-szafonimateusz@xiaomi.com>
2024-11-27 13:32:23 -03:00
p-szafonimateusz
d51ceccd7b arch/x86_64: add syscalls support
arch/x86_64: add syscalls support

Signed-off-by: p-szafonimateusz <p-szafonimateusz@xiaomi.com>
2024-11-27 13:32:23 -03:00
p-szafonimateusz
7f4279b8af arch/x86_64/: fix broken set_cr3()
arch/x86_64/: fix broken set_cr3()

Signed-off-by: p-szafonimateusz <p-szafonimateusz@xiaomi.com>
2024-11-27 13:32:23 -03:00
Jinliang Li
37a0445ddb armv8-r/gicv3: support fiq
1. support fiq decoding and dispatch
2. replace CONFIG_ARMV8R_DECODEFIQ with CONFIG_ARCH_HIPRI_INTERRUPT

Signed-off-by: Jinliang Li <lijinliang1@lixiang.com>
2024-11-27 14:28:27 +08:00
p-szafonimateusz
825ba8ed7b arch/x86_64/intel64: fix revoke_low_memory
fix revoke_low_memory, problem found by Xiangzhen Ouyang.

g_pt_low mapping is removed during revoke_low_memory so we can't access this memory area with 1:1 mapping.
This logic has been broken for a long time, but for some reason it worked without any crash at boot.

Signed-off-by: p-szafonimateusz <p-szafonimateusz@xiaomi.com>
2024-11-27 03:28:37 +08:00
p-szafonimateusz
894b0f956b arch/x86_64/intel64: up_disable_irq should work from any CPU
simplify interrupt logic and allow any CPU
to disable interrupt, not only CPU that enabled it.

Signed-off-by: p-szafonimateusz <p-szafonimateusz@xiaomi.com>
2024-11-27 03:03:05 +08:00
hujun5
ef313755e7 sched: replace up_cpu_index with this_cpu
Make this_cpu is arch independent and up_cpu_index do that.
In AMP mode, up_cpu_index() may return the index of the physical core.

Signed-off-by: hujun5 <hujun5@xiaomi.com>
2024-11-27 03:00:32 +08:00
simbit18
430c2ecf46 arch/risc-v/src/cmake/Toolchain.cmake: Msys2 Cmake fixed nuttx/config.h: No such file or directory
fixed
/qemu-rv/qemu_rv_head.S:25:10: fatal error: nuttx/config.h: No such file or directory
   25 | #include <nuttx/config.h>
      |          ^~~~~~~~~~~~~~~~
compilation terminated.

added

# override the responsible file flag

if(CMAKE_GENERATOR MATCHES "Ninja")
  set(CMAKE_C_RESPONSE_FILE_FLAG "$DEFINES $INCLUDES $FLAGS @")
  set(CMAKE_CXX_RESPONSE_FILE_FLAG "$DEFINES $INCLUDES $FLAGS @")
  set(CMAKE_ASM_RESPONSE_FILE_FLAG "$DEFINES $INCLUDES $FLAGS @")
endif()
2024-11-27 02:35:48 +08:00
hujun5
610efc8f1a arm: remove up_set_current_regs/up_current_regs
reason:
up_set_current_regs initially had two functions:

1: To mark the entry into an interrupt state.
2: To record the context before an interrupt/exception. If we switch to
   a new task, we need to store the upcoming context regs by calling up_set_current_regs(regs).

Currently, we record the context in other ways, so the second function is obsolete.
Therefore, we need to rename up_set_current_regs to better reflect its actual meaning,
which is solely to mark an interrupt.

Signed-off-by: hujun5 <hujun5@xiaomi.com>
2024-11-26 20:04:54 +08:00
chao an
4dda9800b4 espressif/mcpwm: fix compile error
continue work of PR #14938

Signed-off-by: chao an <anchao@lixiang.com>
2024-11-26 16:34:19 +08:00
hujun5
111a0746c2 arm64: change name saved_reg to saved_regs
reason:
saved_regs is more meaningful and used by all other arch

Signed-off-by: hujun5 <hujun5@xiaomi.com>
2024-11-26 10:09:31 +08:00
hujun5
53548509b1 fix build error
common/espressif/esp_rmt.c: In function 'rmt_set_tx_thr_intr_en':
common/espressif/esp_rmt.c:654:48: error: passing argument 1 of 'spin_lock_irqsave' makes pointer from integer without a cast [-Werror=int-conversion]
  654 |       flags = spin_lock_irqsave(g_rmtdev_common.rmt_spinlock);
      |                                 ~~~~~~~~~~~~~~~^~~~~~~~~~~~~
      |                                                |
      |                                                spinlock_t {aka unsigned char}
/home/hujun5/downloads1/vela_sim/nuttx/include/nuttx/spinlock.h:617:55: note: expected 'volatile spinlock_t *' {aka 'volatile unsigned char *'} but argument is of type 'spinlock_t' {aka 'unsigned char'}
  617 | irqstate_t spin_lock_irqsave(FAR volatile spinlock_t *lock)
      |                                  ~~~~~~~~~~~~~~~~~~~~~^~~~
CC:  nsh_script.c common/espressif/esp_rmt.c:662:48: error: passing argument 1 of 'spin_lock_irqsave' makes pointer from integer without a cast [-Werror=int-conversion]
  662 |       flags = spin_lock_irqsave(g_rmtdev_common.rmt_spinlock);
      |                                 ~~~~~~~~~~~~~~~^~~~~~~~~~~~~
      |                                                |
      |                                                spinlock_t {aka unsigned char}
/home/hujun5/downloads1/vela_sim/nuttx/include/nuttx/spinlock.h:617:55: note: expected '

Signed-off-by: hujun5 <hujun5@xiaomi.com>
2024-11-26 09:03:29 +08:00
hujun5
34e79f9618 spinlock: use spin_lock_init replace spin_initialize
reason:
1: spin_lock_init and spin_initialize have similar functionalities.
2: spin_lock and spin_unlock should be called in matching pairs.

Signed-off-by: hujun5 <hujun5@xiaomi.com>
2024-11-26 00:02:44 +08:00
hujun5
03f430edf7 fix some build error
hujun5@hujun5-OptiPlex-7070:~/downloads1/vela_sim/nuttx$ make -j12
chip/qemu_boot.c: In function 'up_cpu_start':
chip/qemu_boot.c:102:3: warning: implicit declaration of function 'sched_note_cpu_start' [-Wimplicit-function-declaration]
  102 |   sched_note_cpu_start(this_task(), cpu);
      |   ^~~~~~~~~~~~~~~~~~~~
chip/qemu_boot.c:102:24: warning: implicit declaration of function 'this_task' [-Wimplicit-function-declaration]
  102 |   sched_note_cpu_start(this_task(), cpu);
      |                        ^~~~~~~~~

Signed-off-by: hujun5 <hujun5@xiaomi.com>
2024-11-25 17:10:50 +08:00
hujun5
fccd908114 arch/arm64: syscall SYS_switch_context and SYS_restore_context use 0 para
reason:
simplify context switch
sys_call0(SYS_switch_context)
sys_call0(SYS_restore_context)

Signed-off-by: hujun5 <hujun5@xiaomi.com>
2024-11-23 12:22:21 +08:00
hujun5
f4d212fd6d arm64: remove up_set_current_regs/up_current_regs
reason:
up_set_current_regs initially had two functions:

1: To mark the entry into an interrupt state.
2: To record the context before an interrupt/exception. If we switch to
a new task, we need to store the upcoming context regs by calling up_set_current_regs(regs).

Currently, we record the context in other ways, so the second function is obsolete. Therefore,
we need to rename up_set_current_regs to better reflect its actual meaning, which is solely to mark an interrupt.

Signed-off-by: hujun5 <hujun5@xiaomi.com>
2024-11-23 02:05:56 +02:00
cuiziwei
8e58245524 sim: Fix sim m32 start up crash issue.
After compilation, when starting nsh, the following crash occurs.
==2500151==Shadow memory range interleaves with an existing memory mapping. ASan cannot proceed correctly. ABORTING.
==2500151==ASan shadow was supposed to be located in the [0x1ffff000-0x3fffffff] range.
==2500151==Process memory map follows:
0x30000000-0x33dd4000 /nuttx/nuttx

To avoid overlaps, change the starting address of the text segment.

Using Ttext-segment=0x30000000 causes a crash when starting the 32-bit SIM.
Using -Ttext-segment=0x50000000 causes a crash when starting the 64-bit SIM.
Setting -Ttext-segment=0x40000000 resolves all issues perfectly.

Signed-off-by: cuiziwei <cuiziwei@xiaomi.com>
2024-11-23 01:47:34 +08:00
yinshengkai
0194c2f88a gcov: update gcov compilation parameters
profile-generate is used to generate compilation feedback optimization data, not just code coverage data

It will rely on the toolchain library:
nuttx/libs/libc/misc/lib_utsname.c:94:(.text.uname+0x2c): undefined reference to `__gcov_indirect_call_profiler_v4'
arm-none-eabi-ld: nuttx/libs/libc/misc/lib_utsname.c:113:(.text.uname+0x178): undefined reference to `__gcov_indirect_call'
arm-none-eabi-ld: nuttx/libs/libc/misc/lib_utsname.c:113:(.text.uname+0x188): undefined reference to `__gcov_time_profiler_counter'
arm-none-eabi-ld: nuttx/staging/libc.a(lib_utsname.o):(.data..LPBX0+0x30): undefined reference to `__gcov_merge_time_profile'

Signed-off-by: yinshengkai <yinshengkai@xiaomi.com>
2024-11-22 19:08:08 +08:00
wangmingrong1
1f2d1e97e8 x86-64: Added KASan compilation options
Sorry for this commit: 6cd43777c3
This is the real x86-64 modification, and this patch is x86
Fortunately, except for the error in the previous modification, the actual architecture is supported

Signed-off-by: wangmingrong1 <wangmingrong1@xiaomi.com>
2024-11-22 15:06:02 +08:00
simbit18
d16de91e39 [MSYS2] CMake+Ninja Fix arm-none-eabi-ar: Argument list too long
This issue is related to the Arm toolchain for Windows which is available for x86 host architecture only (compatible with x86_64)

Windows (mingw-w64-i686) hosted cross toolchains
AArch32 bare-metal target (arm-none-eabi)

Issue
/bin/sh: line 1: /home/nuttx/nuttxnew/tools/gcc-arm-none-eabi/bin/arm-none-eabi-ar: Argument list too long

On Windows, arm-none-eabi-ar can only accept strings up to a maximum length of 32,768 characters.

We could suppress the 32K include string limitation by setting the CMake variable CMAKE_NINJA_FORCE_RESPONSE_FILE to ON.

This is unfortunately not enough!!! ): In the build phase this error comes out

$ cmake --build build
[2/1025] Building ASM object arch/CMakeFiles/arch.dir/arm/src/armv7-m/arm_exception.S.obj
FAILED: arch/CMakeFiles/arch.dir/arm/src/armv7-m/arm_exception.S.obj
/home/nuttx/nuttxnew/tools/gcc-arm-none-eabi/bin/arm-none-eabi-gcc.exe @arch/CMakeFiles/arch.dir/arm/src/armv7-m/arm_exception.S.obj.rsp -MD -MT arch/CMakeFiles/arch.dir/arm/src/armv7-m/arm_exception.S.obj -MF arch/CMakeFiles/arch.dir/arm/src/armv7-m/arm_exception.S.obj.d -o arch/CMakeFiles/arch.dir/arm/src/armv7-m/arm_exception.S.obj -c /home/nuttx/nxninja/nuttx/arch/arm/src/armv7-m/arm_exception.S
C:/msys64/home/nuttx/nxninja/nuttx/arch/arm/src/armv7-m/arm_exception.S:42:10: fatal error: nuttx/config.h: No such file or directory
   42 | #include <nuttx/config.h>
      |          ^~~~~~~~~~~~~~~~
compilation terminated.

The Workround I found to solve this problem is to overwrite
the responsible file flag CMAKE_${lang}_RESPONSE_FILE_FLAG with $DEFINES $INCLUDES $FLAGS

Maybe there is a better solution but this one it works. :)
2024-11-21 19:18:38 -03:00
wangmingrong1
6cd43777c3 x86-64: Support symbol table and kasan global variables cross-border detection
1. Add kasan compilation options
2. Modify the link process to support symbol tables and kasan global variables cross-border detection

Signed-off-by: wangmingrong1 <wangmingrong1@xiaomi.com>
2024-11-22 00:01:36 +08:00
Jouni Ukkonen
085830612c arch/arm64/imx9: Fix cntfrq_el0 to correct value
Read base frequency from system counter0 and write it
to arm core register. This corrects timers to work properly
Then enable counting.

Signed-off-by: Jouni Ukkonen <jouni.ukkonen@unikie.com>
2024-11-21 11:26:45 -03:00
guoshichao
f6cfcfa39f armv6-m: fix the incorrect stub-function entry address of svc call
the stub-function entry address is stored in r4, we should branch to the
stub-function with blx r4, not r5

Signed-off-by: guoshichao <guoshichao@xiaomi.com>
2024-11-21 20:08:42 +08:00
Peter Bee
3e6913775d fix(rp2350): should copy data before init clock
Signed-off-by: Peter Bee <peter@PeterdeMac-mini.local>
2024-11-21 20:00:17 +08:00
cuiziwei
f0e03f6c3c Unify the linking options for 32-bit and 64-bit to text-segment=0x30000000.
In order to be compatible with 32-bit and 64-bit compilation, set the text-segment to 0x30000000.

Signed-off-by: cuiziwei <cuiziwei@xiaomi.com>
2024-11-21 16:13:52 +08:00
cuiziwei
feb38c43f2 sim/m64: Fix ld error.
/usr/bin/ld: nuttx.rel: relocation R_X86_64_32S against `.rodata' can not be used when making a PIE object; recompile with -fPIE
/usr/bin/ld: failed to set dynamic section sizes: bad value

Signed-off-by: cuiziwei <cuiziwei@xiaomi.com>
2024-11-21 12:13:14 +08:00
stbenn
9cd0ea32ea arch/stm32h5: Add timer register hardware file
This commit adds register definitions for advanced, basic, and general purpose timers. Formatting convention was taken from the H7 hardware timer header.
2024-11-21 10:54:10 +08:00
simbit18
7df0e945ad Fix Kconfig style
Remove spaces from Kconfig files
Add TABs
Replace help => ---help---
Remove extra TABs
Add comments
2024-11-20 16:45:40 -03:00
Peter Bee
c0f776dbc3 follow upstream change & fix minor things
Signed-off-by: Peter Bee <pbjd97@gmail.com>
2024-11-20 16:32:05 -03:00
Peter Bee
48ded21e30 refine driver
Signed-off-by: Peter Bee <pbjd97@gmail.com>
2024-11-20 16:32:05 -03:00
Marco Casaroli
c5b81401d8 arch(rp23xx): add files 2024-11-20 16:32:05 -03:00
Marco Casaroli
047b832f24 rp23xx: add pico-sdk files
These files were copied from a config of pico-sdk 2.0.0.

They provide struct address mapped access to peripherals, along
with register definitions. It also provides some compiler helpers
that are partially used by the port.
2024-11-20 16:32:05 -03:00
Jouni Ukkonen
9aa9ee28cd arch/arm64/imx9/lspi: improve spi initialization
Hardware initialization is based refcount, not
spi enable bit and add interface to unitialize bus

Signed-off-by: Jouni Ukkonen <jouni.ukkonen@unikie.com>
2024-11-20 12:49:12 -03:00
Huang Qi
fb92b60000 arch/risc-v: Minor document improvement
Add function description for function prototype of `riscv_jump_to_user`
to make it easier to read, and fix some inconsistent comment style in
`riscv_internal.h`.

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2024-11-20 20:40:09 +08:00
Huang Qi
3a6de58904 riscv/syscall.h: Update comment for syscall
Change RV64GC to RISC-V since this file is for all RISC-V based platform.

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2024-11-20 10:50:50 +01:00
YAMAMOTO Takashi
788f8fc495 esp32s3_partition.c: Appease a compiler warning (-Wdiscarded-qualifiers) 2024-11-20 17:43:12 +08:00
Jukka Laitinen
b088369014 arch/arm64/src/imx9/imx9_lpi2c.c: Clear NACK properly on last RX byte
Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
2024-11-20 17:36:00 +08:00
Jukka Laitinen
02a3437289 arch/arm64/src/imx9/imx9_lpi2c.c: Add error recovery on timeout
Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
2024-11-20 17:36:00 +08:00
Jukka Laitinen
3afa58cdda arch/arm64/src/imx9/imx9_lpi2c.c: Clean up the irq handling logic
Both RX and TX interrupts can be enabled after the setup of the transfer; the TX interrupt
must be enabled after queuing the first byte as done before. It is not possible to miss the
RX interrupts, as it pends as long as the byte gets read from the FIFO

When starting the TX, the first byte can be queued instantly, it won't be sent out to the
bus if there is NACK to the address. This also prevents spurious TX interrupts in error
cases, since the TX queue is not empty after initiating a transfer.

In some error cases controller sends STOP by itself even if AUTOSTOP is disabled.
It is better to tell the controller to ABORT, which will also generate STOP only when needed.

Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
2024-11-20 17:36:00 +08:00
wangmingrong1
d41e3da911 Fix ALIGN_UP duplicate definition error
ALIGN_UP has been defined in nuttx.h

Signed-off-by: wangmingrong1 <wangmingrong1@xiaomi.com>
2024-11-20 14:51:54 +08:00
Ville Juven
3146ea04b8 risc-v/up_testset: Implement test-and-set with AMOSWAP
It should be a bit more efficient to do compared to the LR/SC pair.
2024-11-20 13:27:40 +08:00
stbenn
8def1764a4 arch/stm32h5: add basic ADC support
Adds ADC support with minimal feature set (no DMA or Timers etc). A new nucleo-h563zi configuration was added to
provide easy testing with the adc example NSH addon.

Fix Kconfig spacing to tabs
2024-11-20 08:51:27 +08:00
BitBender334
bd7074460c arch/risc-v/src/mpfs/mpfs_irq.c: Default global interrupt priorities 2024-11-19 22:24:39 +08:00
liamHowatt
27e587b179 arch/esp32s3: fb add pandisplay
Signed-off-by: liamHowatt <liamjmh0@gmail.com>
2024-11-19 20:51:50 +08:00
chao an
f8ccfc3f7f arm/efm32: fix regression by PR#14810
itm syslog should use syslog_write() not up_putc()

Signed-off-by: chao an <anchao@lixiang.com>
2024-11-19 20:50:33 +08:00
chao an
c328650aa5 arm/cortex-m: itm syslog should select SYSLOG_REGISTER
Signed-off-by: chao an <anchao@lixiang.com>
2024-11-19 20:50:33 +08:00
chao an
5582134c04 arm/efm: fix build warning
chip/efm32_start.c:150:3: warning: implicit declaration of function 'itm_syslog_initialize';
                                   did you mean 'syslog_initialize'? [-Wimplicit-function-declaration]
  150 |   itm_syslog_initialize();
      |   ^~~~~~~~~~~~~~~~~~~~~
      |   syslog_initialize

Signed-off-by: chao an <anchao@lixiang.com>
2024-11-19 20:50:33 +08:00
SPRESENSE
f142d04b91 arch: cxd56xx: Fix compile error of cxd56_gnss.c
Fix error: 'g_rtc_enabled' undeclared (first use in this function).
2024-11-19 15:37:42 +08:00
Masayuki Ishikawa
1d6ece71b8 arch: arm: Fix cxd56xx for SMP
Summary:
- In https://github.com/apache/nuttx/pull/14465,
  atomic_compare_exchange_weak_explicit() was newly introduced
  in semaphore. However, cxd56xx has an issue with the API
  if SMP is enabled (see up_testset2 in cxd56_testset.c).
- This commit fixes the issue by using LIBC_ARCH_ATOMIC.

Impact:
- Only cxd56xx SoCs in SMP mode.

Testing:
- Tested with spresense:smp, spresense:wifi_smp
- NOTE: If DEBUG_ASSERTIONS is enabled assert would be happend.
  I think this might be another issue.

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
2024-11-19 15:17:28 +08:00
YAMAMOTO Takashi
ae5df0e06c esp32s3_serial.c: make a comment match the code 2024-11-18 19:10:24 +08:00
YAMAMOTO Takashi
fd6eccb00e arch/xtensa/src/esp32/esp32_serial.c: fix a comment 2024-11-18 19:10:24 +08:00
ligd
a88652fe53 arm64: fix compile failed 'tpidr_el1' undeclared
time/lib_localtime.c: In function 'tz_lock':
time/lib_localtime.c:396:7: error: 'tpidr_el1' undeclared (first use in this function)
  396 |   if (up_interrupt_context() || (sched_idletask() && OSINIT_IDLELOOP()))
      |       ^~~~~~~~~~~~~~~~~~~~

Signed-off-by: ligd <liguiding1@xiaomi.com>
2024-11-17 20:03:44 +08:00
Xiang Xiao
b41d96ea67 sim/win: Replace nuttx_mode_t with int
align with the posix implementation

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2024-11-17 08:31:08 -03:00
guoshichao
2d7b19b359 ghs: add thumb mode detection support for ghs compiler
Signed-off-by: guoshichao <guoshichao@xiaomi.com>
2024-11-17 15:43:18 +08:00
hujun5
707f0ce719 arm64: remove unused code
Signed-off-by: hujun5 <hujun5@xiaomi.com>
2024-11-17 10:07:27 +08:00
stbenn
caaee545b1 arch/stm32h5: Simplify PLL configuration.
The PLL clock configuration was simplified on the assumption the clocks are correctly set in the board.h file. Instead of seperate conditions
for register components, assume the relevant PLL registers are fully defined in board.h. This should result in easier to understand defines in board.h
and simpler code flow in the standard clock configuration function.

Changes were mad in the board file alongside changing the arch files. Changes to board/stm32h5:
  - PLL1 has been configured to use integer instead of fractional mode to reach the 250 MHz target. PLL2 and PLL3 configurations were
    removed since they are currently unused in the H5 configuration.
  - PLL1 output was verified by testing for changes in serial baud rate.
2024-11-16 01:55:32 +08:00
chao an
238cddde3a drivers/syslog: remove implement of syslog_putc()
syslog_putc() have a lot of duplicate logic with syslog_write().
remove syslog_putc() and reuse syslog_write() to simplify syslog printing.

Signed-off-by: chao an <anchao@lixiang.com>
2024-11-15 19:46:36 +08:00
hujun5
19b4911d7f arch: remove up_current_regs in common code
reason:

When entering an exception or interrupt, there are two sets of registers:
one is the "running regs", which we need to save,
and the other is the "ready to running regs", which we may soon use.
For consistency in logic, we can always store the "running regs" in the regs field of g_running_tasks,
otherwise it may lead to errors in the storage location of the "running regs."

When we need to access the "running regs," we should uniformly retrieve them from the regs field of g_running_tasks.

As the next step, we will rename the set_current_regs/up_current_regs functions
for each architecture to more appropriate names, solely for the purpose of identifying interrupts.

Signed-off-by: hujun5 <hujun5@xiaomi.com>
2024-11-15 18:25:35 +08:00
hujun5
5300d77398 fix some arch miss update g_running_tasks
Signed-off-by: hujun5 <hujun5@xiaomi.com>
2024-11-15 18:25:35 +08:00
Takuya Miyasita
2275138dcf arch_atomic : Introduce CONFIG_LIBC_ARCH_ATOMIC
Some armv7-m-based SoCs do not work with atomic instructions,
even though armv7-m supports them.

To avoid using atomic instructions generated by gcc,
CONFIG_LIBC_ARCH_ATOMIC is newly introduced with which
arch_atomic.c is linked explicitly.

However, the function names need to be changed to avoid
build errors, since the functions described in stdatomic.h
are gcc built-in and inlined when the code is compiled.

About libcxx with CONFIG_LIBC_ARCH_ATOMIC, it still
does not work. It is also needed to call nx_atomic_ ver
instead of __atomic ver in
libcxx/include/__atomic/cxx_atomic_lmpl.h.

Signed-off-by: Takuya Miyasita <Takuya.Miyashita@sony.com>
2024-11-15 14:01:56 +08:00
Eero Nurkkala
f2949f84a3 arm64/imx9: add imx93-evk ddr training
This performs the DDR training for imx93-evk. In addition to the source code,
it downloads binaries which are included in the final image. The bootloader
must be ARCH_CORTEX_A53 instead of A55 due to atomic instructions that don't
work with the OCRAM / EL3 combination.

Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
2024-11-15 09:56:31 +08:00
Pressl, Štěpán
fe4f7a3a16 arch/arm/src/samv7/sam_afec.c: AFEC1 actually has 12 physical inputs
This commit adds a max_pins field into the private struct.
AFEC0 has 11, AFEC1 has 12. The 12th pin of AFEC0 is an internal
pin connected to a temperature sensor, which we don't use.

Signed-off-by: Stepan Pressl <pressste@fel.cvut.cz>
2024-11-15 08:43:07 +08:00
wangmingrong1
81f060b8d5 sim: Add compiler selection
Use gcc by default

Signed-off-by: wangmingrong1 <wangmingrong1@xiaomi.com>
2024-11-15 01:05:16 +08:00
wangmingrong1
9b0df45d1c gcov: arm,arm64 add coverage global
Signed-off-by: wangmingrong1 <wangmingrong1@xiaomi.com>
2024-11-15 01:05:16 +08:00
wangmingrong1
17ce9b86c1 gcov: Correct existing gcov configuration
1. add CONFIG_COVERAGE_ALL to replace CONFIG_SCHED_GCOV_ALL
2. Correct all SCHED_GCOV, SCHED_GCOV_ALL

Signed-off-by: wangmingrong1 <wangmingrong1@xiaomi.com>
2024-11-15 01:05:16 +08:00
wangmingrong1
b6f6cadf93 gprof: Remove duplicate content
1. arch/arm/src/cmake/gcc.cmake: The same judgment has been made in line 164
2. boards/sim/sim/sim/scripts/Make.defs: arch/sim/src/Makefile also has in line 147

Signed-off-by: wangmingrong1 <wangmingrong1@xiaomi.com>
2024-11-15 01:05:16 +08:00
p-szafonimateusz
bb98911a11 arch/x86_64/intel64: add support for framebuffer
arch/x86_64/intel64: add support for framebuffer

Signed-off-by: p-szafonimateusz <p-szafonimateusz@xiaomi.com>
2024-11-15 01:04:52 +08:00
wangmingrong1
656883fec5 arch/toochain: Add toochain to gcc
1. Modify the select the gcc compiler

Signed-off-by: wangmingrong1 <wangmingrong1@xiaomi.com>
2024-11-14 15:45:24 +08:00
Kyle Wilson
d4f6cc229d STM32H5 I2C Driver
Added I2C driver for the STM32H5. This driver uses the STM32H7 I2C driver as a base. The primary difference is setclock dynamically sets the I2C TIMINGR register instead of using hardcoded values. This allows the I2C peripherals to use any of the input clocks and set to any speed 0-1MHz. Additionally, Kconfig options were made available to set the Digital Noise Filter (DNF), Analog Noise Filter, I2C Clock source (i2c_ker_ck), as well as set i2c rise/fall times which are crucial to timing. Care must be taken when setting the clock source and filters, as not all settings are compatible with all i2c clock frequencies.
2024-11-14 08:50:28 +08:00
stbenn
5d87319cb6 arch/stm32h5: Add ADC hardware register file
This change defines macros for the ADC register map from ST document RM0481.
2024-11-13 16:33:22 -03:00
Davi Diogo
d6a73a46e8 riscv/espressif/bootloader/mcuboot: Sign image with MCUBoot version
Add version signature to MCUBoot compatible image on espressif RISC-V architecture

Signed-off-by: Davi Diogo  <eng.davidiogo@gmail.com>
2024-11-13 20:28:17 +01:00
chenxiaoyi
9cd1c81149 xtensa: use up_interrupt_context() to determine if in interrupt context
Signed-off-by: chenxiaoyi <chenxiaoyi@xiaomi.com>
2024-11-13 19:24:22 +08:00
Jouni Ukkonen
e2a9c84260 arch/arm64/imx9: Add trdc support
Trdc is configured in EL3 bootloader
Clock pre-initialization is also executed there.
Trdc board configuration for imx93evk included

Signed-off-by: Jouni Ukkonen <jouni.ukkonen@unikie.com>
2024-11-13 16:46:04 +08:00
lipengfei28
daab676db9 arch/arm64: syscall SYS_switch_context and SYS_restore_context use tcb as
parm

sys_call2(SYS_switch_context, (uintptr_t)rtcb, (uintptr_t)tcb)
sys_call1(SYS_restore_context, (uintptr_t)next)

Signed-off-by: lipengfei28 <lipengfei28@xiaomi.com>
2024-11-13 16:35:15 +08:00
Takuya Miyasita
6847eb0c25 risc-v and xtensa Kconfig : Remove LIBC_ARCH_ATOMIC
In https://github.com/apache/nuttx/pull/13044,
LIBC_ARCH_ATOMIC was finally removed.

Howerver, the following chips still have the config.
- ARCH_CHIP_ESP32S3
- ARCH_CHIP_ESP32C3_GENERIC
- ARCH_CHIP_ESP32H2

This commit fixes the issue.
2024-11-13 15:30:53 +08:00
Masayuki Ishikawa
bbf2bbf37d Revert "arch_atomic : Introduce CONFIG_LIBC_ARCH_ATOMIC"
This reverts commit 81e7b13a05.
2024-11-13 10:45:12 +09:00
wangmingrong1
b59e3616f4 gcov: Support for the most streamlined profile of LLVM-embedded-toolchain-for-Arm
1. Excerpted from: https://github.com/ARM-software/LLVM-embedded-toolchain-for-Arm/blob/main/samples/src/cpp-baremetal-semihosting-prof/proflib.c
2. Since llvm profile supports more than just gcov, and some features have not yet been explored, two clang gcov implementations are supported after this patch
3. Using this lib only supports the gcov compilation options of "-fprofile-instr-generate -fcoverage-mapping"
4. This file is heavily dependent on the compiler clang version, and is currently aligned with ci, supporting 17.0.1 and below. 18 and above are not supported by this library due to different internal implementations of the compiler

Signed-off-by: wangmingrong1 <wangmingrong1@xiaomi.com>
2024-11-13 05:33:00 +08:00
wangmingrong1
bf93c7840a gprof: move gprof function from sched to libbuiltin/libgcc
1. Enable interrupt gprof please config CONFIG_PROFILE_MINI
2. Enable instuction gprof please add compile opt "-pg" or config CONFIG_PROFILE_ALL

Signed-off-by: wangmingrong1 <wangmingrong1@xiaomi.com>
2024-11-13 02:42:31 +08:00
Huang Qi
039c79717c arch/risc-v: Add ARCH_HAVE_RAMFUNCS option for ESP32-C3
`ARCH_HAVE_RAMFUNCS` has no actual effect on the ESP32-C3,
but ESP32-C3 has RAM functions, so select it to mark that is OK,
and then we can also suppress the RWX memory region warning.

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2024-11-12 21:33:22 +08:00
lipengfei28
d8bdf23e8a arch/arm64: bug fix,arm64_fatal_handler need regs parms
Signed-off-by: lipengfei28 <lipengfei28@xiaomi.com>
2024-11-12 17:35:47 +08:00
chenrun1
2cf26036a5 Use lib_get_pathbuffer instead of stack variables
Summary:
  Modified the usage logic, mainly introduced lib_get_pathbuffer and lib_put_pathbuffer

Signed-off-by: chenrun1 <chenrun1@xiaomi.com>
2024-11-12 17:21:42 +08:00
Takuya Miyasita
81e7b13a05 arch_atomic : Introduce CONFIG_LIBC_ARCH_ATOMIC
Some armv7-m-based SoCs do not work with atomic instructions,
even though armv7-m supports them.

To avoid using atomic instructions generated by gcc,
CONFIG_LIBC_ARCH_ATOMIC is newly introduced with which
arch_atomic.c is linked explicitly.

However, the function names need to be changed to avoid
build errors, since the functions described in stdatomic.h
are gcc built-in and inlined when the code is compiled.

Signed-off-by: Takuya Miyasita <Takuya.Miyashita@sony.com>
2024-11-12 14:27:42 +09:00
Huang Qi
8a6e8320cf riscv: Suppress LOAD RWX linker warning
Suppress the warning message "nuttx has a LOAD segment with RWX permissions" in case of RAM boot mode is selected.
RAM MODE: BOOT_RUNFROMEXTSRAM/BOOT_RUNFROMISRAM/BOOT_RUNFROMSDRAM/BOOT_COPYTORAM

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2024-11-11 23:44:41 +08:00
guoshichao
6036a318f4 compiler: add __ARM_ARCH, __ARM_FEATURE_DSP macro definition in ghs
when we build mbedtls in vela with ghs compiler, the mbedtls need to
access __ARM_ARCH and __ARM_FEATURE_DSP, and to construct the inline asm
code based on these two macros.
With ghs compiler, these two macros are not defined, and will be
evaluated as 0 by default, and thus will using to wrong inline asm code,
in order to handle this issue, we need to add conversion between the ghs
and gcc with __ARM_ARCH, __ARM_FEATURE_DSP

Signed-off-by: guoshichao <guoshichao@xiaomi.com>
2024-11-11 22:18:05 +08:00
guoshichao
0679d45d5b nuttx/qemu: Fix funciton up_idle multiple definition
Signed-off-by: guoshichao <guoshichao@xiaomi.com>
2024-11-11 19:56:40 +08:00
guoshichao
a044e1896f arm_svcall: fix the naked_function function non-compatible issue
when build with greenhills_202354, the naked_function should only
contains the basic asm statements, so if the naked_function contains the
statements that using to accept params from C lang runtime, then build
error will reported:

error #101112: Only basic asm expressions are allowed for functions
with __attribute__((naked)): dispatch_syscall

Signed-off-by: guoshichao <guoshichao@xiaomi.com>
2024-11-11 19:56:13 +08:00
robert
5e8f1eefb0 Bluetooth: improved pairing process and host layer now successfully receives ACL packets 2024-11-10 14:33:52 -03:00
stbenn
cd479f6752 arch/stm32h5: Add ethernet hardware support files
This commit adds files in preperation of adding ethernet drivers for the STM32H563 and Nucleo-H563ZI board.
It also modifies the pinmap to include ethernet pins (and cleaned up leftover comments from L5 file), as well as
add those pins to the board.h for the nucleo-h563zi.

Files added:
  - arch/arm/src/stm32h5/hardware/stm32_ethernet.h
  - arch/arm/src/stm32h5/hardware/stm32_sbs.h
    - Not fully implemented, just register necessary for ethernet driver.
2024-11-10 01:11:10 +08:00
Kyle Wilson
19fc0628ae Update BOARD_USExxx naming, input clock selection, and setting of HSIDIV
The naming scheme in board.h changed from STM32H5_ to STM32_. As a result we needed to adjust the naming of the STM32H5_BOARD_USExxx variables in stm32h5xx_rcc.c. Also made changes to allow the enabling of all 3 of HSI, CSI, or HSE in stm32_stdclockconfig. Lastly, the HSIDIV bits in RCC_CR were not being cleared before being set. Added logic to clear these bits.

defined CSIRDY_TIMEOUT
2024-11-09 11:36:09 +01:00
Ville Juven
65cfd8a6ca riscv_syscall.S: Fix a massive bug in syscall dispatch logic
There is an enormous error in the system call dispatch logic; if a task
is inside a critical section (local interrupts disabled) there is a chance
that during a context switch when the task resumes, local interrupts are
erroneously ENABLED. This obviously leads to unexpected crashes and such.

This happens when the CPU status has Previous Interrupt Enable (PIE) set
to 1, even though Interrupt Enable (IE) is set to 0.

When the system call returns via ERET, the CPU sets PIE->IE and if PIE=1
interrupts get enabled.

This is fixed easily by explicitly CLEARING PIE from the register save
area, if IE=0 when the system call was started.
2024-11-08 12:51:39 -03:00
ouyangxiangzhen
f7abf7446f arch/arm64: Optimized SGI to avoid VM exit.
In the virtualized environment, each time an SGI is sent, the value of IGROUPR0 needs to be read once. Since the GIC Redistributor is a purely emulated device, each read of IGROUPR0 will cause a VM exit, causing serious performance degradation. This patch replaces the read with the value previously set in `gicv3_cpuif_init`, and we assume that this value has not been modified after initialization.

Signed-off-by: ouyangxiangzhen <ouyangxiangzhen@xiaomi.com>
2024-11-08 01:23:46 +08:00
Jouni Ukkonen
ed8bfdd26a arch/arm64/imx9: Reset rx fifo in mode change
instead of looping just reset rxfifo

Signed-off-by: Jouni Ukkonen <jouni.ukkonen@unikie.com>
2024-11-07 21:34:04 +08:00
Jouni Ukkonen
8c98194182 arc/arm64/imx9: Improve flexspi nor performance
-Increase clock to 133MHz
-Enable prefetch

Signed-off-by: Jouni Ukkonen <jouni.ukkonen@unikie.com>
2024-11-07 16:51:13 +08:00
Jouni Ukkonen
a3d1b06214 arch/arm64/imx9 4byte addressing to nor
-Use 4byte addressing in flexpi nor
-report 4k blocksize to userland
-increase clock to 100MHz
-some cleanup

Signed-off-by: Jouni Ukkonen <jouni.ukkonen@unikie.com>
2024-11-07 16:51:13 +08:00
Jouni Ukkonen
d260e7f59e imx9/flexcan: Add disable/enable cycle
Add enable/disable cycle to initialize
function to speed up soft reset

Signed-off-by: Jouni Ukkonen <jouni.ukkonen@unikie.com>
2024-11-07 16:20:29 +08:00
lipengfei28
e29258391f arch/arm64: add have fork config
Signed-off-by: lipengfei28 <lipengfei28@xiaomi.com>
2024-11-07 15:21:10 +08:00
Kyle Wilson
ad2db7a387 Fix Serial APB Clock Sources
The apbclock sources for lpuart1, usart6, usart10, and usart11 were set to the wrong PCLK (default).
2024-11-07 11:37:28 +08:00
stbenn
ca74d81a04 H5 Kconfig add ethernet, cleanup comments.
This is a combination of 2 commits:

H5 Kconfig ethernet options added.
  - This commit cleans up unecessary comments in the Kconfig and adds the the Ethernet/MAC menu.
    The menu is copied from the H7 menu, since the peripheral IP is identical.

Remove trailing whitespaces.

Update suggested mask
2024-11-07 09:55:01 +08:00
Kyle Wilson
400f2960e6 Added PLLxFRACN definitions. Updated board.h to use them. Updated board.h to set SYSCLK to 250 MHz properly.
PLL1FRACN was being set improperly. stm32h5xxx_rcc.c does not shift the value provided by board.h. So it was being set wrong. The defintions in stm32h5xxx_rcc.h shift the FRACN value and are now used by board.h. Also, board.h was not setting PLL1P properly. PLL1P can not have odd divisors. Therefore a value of 0 was invalid. Set it to a value of 1 (divide by 2), then adjust PLL1N to 31 and PLL1FRAC1 to 2048 to actually set SYSCLK to 250MHz.
2024-11-06 16:25:09 -03:00
Jukka Laitinen
4ba8723ab8 arch/arm64/src/common/arm64_fatal.c: Fix compilation warning with -Wextra
Wextra complains on some silly issues, like this one. Work around the issue in code directly.

Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
2024-11-07 00:56:40 +08:00
Eren Terzioglu
3f77e97b03 esp32[s2|s3]: Add SPI bitbang support 2024-11-06 19:47:42 +08:00
Eren Terzioglu
243a2adcaf esp32[c3|c6|h2]: Add SPI bitbang support 2024-11-06 19:47:42 +08:00
wangmingrong1
f32f25c31e ci: Fix ci problem
Signed-off-by: wangmingrong1 <wangmingrong1@xiaomi.com>
2024-11-06 17:30:27 +08:00
stbenn
904b6ff85b H5 with NSH support for Nucleo-H563ZI.
Made fixes to issues from CI. Nxstyle and defconfig syntax.

This is a combination of 6 commits.

Adding STM32H5 arch files. With comments addressed.

Created stm32h5 directory to add support for the H5 chip, and used a Nucleo-H563ZI dev board during development. The goal was to get a working nutshell through the STLink connector on the board.

Remove board/docs changes for PR update.

Squash commits into one for PR guideline conformity.

trying to fix build issues

Fix format from review

Nucleo-H563ZI support for NSH.

Created stm32h5 directory to add support for the H5 chip, and used a Nucleo-H563ZI dev board during development. The goal was to get a working nutshell through the STLink connector on the board.

Fix switch default case placement.

NXstyle fixes

Renaming files

rename stm32h5_gpio.x files

rename h5 hsi48 files

Rename h5 idle file

rename stm32h5_irq.c

Rename some rcc functions and stm32h5_rcc.c

rename stm32h5_rcc.h

Rename stm32h5_pwr.x

lowputc renames

timerisr renames

uart renamed

rename serial file

rename start

Turn off the defines that enable DMA on serial

remove DMA Kconfig options

Remove H5 documentation. Will add in a future PR.

Fix styling and defconfig improper syntax.
2024-11-06 10:28:49 +08:00
parallels
2b110ab64e Adding STM32H5 arch files. With comments addressed.
Created stm32h5 directory to add support for the H5 chip, and used a Nucleo-H563ZI dev board during development. The goal was to get a working nutshell through the STLink connector on the board.

Remove board/docs changes for PR update.

Squash commits into one for PR guideline conformity.

trying to fix build issues

Fix format from review
2024-11-06 03:17:45 +08:00
Jouni Ukkonen
6a0c239c8e arch/arm64/imx9: Clear edma4 mux conf before set
Warm boot might fail if edma4 channel mux is
not written to default value

Signed-off-by: Jouni Ukkonen <jouni.ukkonen@unikie.com>
2024-11-06 02:56:52 +08:00
cuiziwei
f1d180d56e nuttx/sim: Remove math.h in sim.
The reason for removing math.h is that undefining __GLIBC__ does not take effect. By default, sim will use the toolchain's math library and undef __GLIBC__ in the source file.

Signed-off-by: cuiziwei <cuiziwei@xiaomi.com>
2024-11-06 02:56:24 +08:00
wangmingrong1
6381685a8b toolchains: Compiler versioning adds --print-memory-usage
1. The "-print-memory-usage" parameter introduced in GNU Link version 2.26

Signed-off-by: wangmingrong1 <wangmingrong1@xiaomi.com>
2024-11-06 01:57:38 +08:00
Felipe Moura
0fad2ee73f riscv/common/espressif: Fix spi slave driver
Fix defconfigs and documentation
2024-11-05 14:59:37 +08:00
wangmingrong1
3e605c1f46 clang/cmake: Fix clang cmake can't find libgcc, align with makefile
makefile:
ifeq ($(CONFIG_BUILTIN_TOOLCHAIN),y)
  COMPILER_RT_LIB = $(shell $(CC) $(ARCHCPUFLAGS) --print-libgcc-file-name)
  ifeq ($(CONFIG_ARCH_TOOLCHAIN_CLANG),y)
    ifeq ($(wildcard $(COMPILER_RT_LIB)),)
      # if "--print-libgcc-file-name" unable to find the correct libgcc PATH
      # then go ahead and try "--print-file-name"
      COMPILER_RT_LIB := $(wildcard $(shell $(CC) $(ARCHCPUFLAGS) --print-file-name $(notdir $(COMPILER_RT_LIB))))
    endif
  endif
endif

Signed-off-by: wangmingrong1 <wangmingrong1@xiaomi.com>
2024-11-04 22:39:40 +08:00
ligd
561e1fc879 x86_64: fix compile warning
In function ‘void* std::__1::__libcpp_operator_new(_Args ...) [with _Args = {long unsigned int}]’,
    inlined from ‘void* std::__1::__libcpp_allocate(size_t, size_t)’ at /home/ligd/platform/trunk/nuttx/include/libcxx/new:294:31,
    inlined from ‘_Tp* std::__1::allocator<_Tp>::allocate(size_t) [with _Tp = char]’ at /home/ligd/platform/trunk/nuttx/include/libcxx/__memory/allocator.h:114:62,
    inlined from ‘constexpr std::__1::__allocation_result<typename std::__1::allocator_traits<_Alloc>::pointer> std::__1::__allocate_at_least(_Alloc&, size_t) [with _Alloc = allocator<char>]’ at /home/ligd/platform/trunk/nuttx/include/libcxx/__memory/allocate_at_least.h:55:27,
    inlined from ‘void std::__1::basic_string<_CharT, _Traits, _Allocator>::__grow_by_and_replace(size_type, size_type, size_type, size_type, size_type, size_type, const value_type*) [with _CharT = char; _Traits = std::__1::char_traits<char>; _Allocator = std::__1::allocator<char>]’ at /home/ligd/platform/trunk/nuttx/include/libcxx/string:2325:49,
    inlined from ‘std::__1::basic_string<_CharT, _Traits, _Allocator>& std::__1::basic_string<_CharT, _Traits, _Allocator>::__assign_external(const value_type*, size_type) [with _CharT = char; _Traits = std::__1::char_traits<char>; _Allocator = std::__1::allocator<char>]’ at /home/ligd/platform/trunk/nuttx/include/libcxx/string:2431:26,
    inlined from ‘std::__1::basic_string<_CharT, _Traits, _Allocator>& std::__1::basic_string<_CharT, _Traits, _Allocator>::assign(const value_type*, size_type) [with _CharT = char; _Traits = std::__1::char_traits<char>; _Allocator = std::__1::allocator<char>]’ at /home/ligd/platform/trunk/nuttx/include/libcxx/string:2444:35:
/home/ligd/platform/trunk/nuttx/include/libcxx/new:270:24: warning: argument 1 value ‘18446744073709551599’ exceeds maximum object size 9223372036854775807 [-Walloc-size-larger-than=]
  270 |   return ::operator new(__args...);

Signed-off-by: ligd <liguiding1@xiaomi.com>
2024-11-04 18:06:09 +08:00
ligd
91b228fcdd arm64: fix compile failed when build ELF apps
aarch64-none-elf-gcc -c -D_LDBL_EQ_DBL -fno-common -Wall -Wstrict-prototypes -Wshadow -Wundef -Werror -Wno-attributes -Wno-unknown-pragmas -Wno-psabi "-O3" -fno-strict-aliasing -fno-omit-frame-pointer -fno-optimize-sibling-calls -fstack-protector-all -fsanitize=kernel-address --param asan-globals=1 -ffunction-sections -fdata-sections "-g3" -mcpu=cortex-a53 -isystem /home/ligd/platform/trunk/nuttx/include -D__NuttX__  -pipe -I /home/ligd/platform/trunk/apps/crypto/mbedtls/include -I /home/ligd/platform/trunk/apps/crypto/mbedtls/mbedtls/include -I /home/ligd/platform/trunk/apps/crypto/openssl_mbedtls_wrapper/include -I /home/ligd/platform/trunk/apps/external/android/frameworks/native/libs/binder/include_rpc_unstable -I /home/ligd/platform/trunk/apps/external/android/frameworks/native/libs/binder/ndk/include_ndk -I /home/ligd/platform/trunk/apps/external/android/frameworks/native/libs/binder/ndk/include_platform -I /home/ligd/platform/trunk/apps/external/android/system/chre/chre/chre_api/include/chre_api -DCHRE_MESSAGE_TO_HOST_MAX_SIZE=2048 -I /home/ligd/platform/trunk/apps/external/android/system/core/libcutils/include -I /home/ligd/platform/trunk/apps/frameworks/graphics/uikit/include -I /home/ligd/platform/trunk/apps/frameworks/runtimes/feature/include -I /home/ligd/platform/trunk/apps/frameworks/runtimes/feature/src -I /home/ligd/platform/trunk/apps/frameworks/security/include -I /home/ligd/platform/trunk/apps/frameworks/system/dfx/include -I /home/ligd/platform/trunk/apps/frameworks/system/topics/include -I /home/ligd/platform/trunk/apps/frameworks/system/utils/include -I /home/ligd/platform/trunk/apps/graphics/lvgl -I /home/ligd/platform/trunk/apps/graphics/lvgl/lvgl -I "/home/ligd/platform/trunk/apps/system/argtable3/argtable3/src" -I /home/ligd/platform/trunk/apps/system/libuv/libuv/include -DUV_HANDLE_BACKTRACE=CONFIG_LIBUV_HANDLE_BACKTRACE -I /home/ligd/platform/trunk/apps/system/uorb/ -I /home/ligd/platform/trunk/nuttx/arch/arm64/src/board/include -I /home/ligd/platform/trunk/nuttx/arch/arm64/src/chip -I /home/ligd/platform/trunk/apps/vendor/bes/drivers/best1600_ep/miwear_drivers/display -I /home/ligd/platform/trunk/apps/vendor/bes/drivers/best1600_ep/miwear_drivers/boards -I /home/ligd/platform/trunk/apps/vendor/bes/drivers/best1600_ep/miwear_drivers/include -I "/home/ligd/platform/trunk/apps/include" -fvisibility=hidden -mlong-calls    modprint.c -o  modprint.c.home.ligd.platform.trunk.apps.examples.sotest.modprint.o

aarch64-none-elf-gcc: error: unrecognized command-line option '-mlong-calls'

Signed-off-by: ligd <liguiding1@xiaomi.com>
2024-11-04 16:24:29 +08:00
xuxin19
1bb01d40fd cmake(build):add the specified armclang compiler to the cmake Toolchain file
Signed-off-by: xuxin19 <xuxin19@xiaomi.com>
2024-11-03 14:06:40 +08:00
Xiang Xiao
e777234714 Fix Error: implicit declaration of function 'enter_critical_section'
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2024-11-03 11:26:44 +08:00
xuxin19
6e81b1ed91 cmake:implement CMake build of xtensa arch
configure:cmake -B build -DBOARD_CONFIG=iss-hifi4:nsh
build:cmake --build build
run:xt-run build/nuttx

Signed-off-by: xuxin19 <xuxin19@xiaomi.com>
2024-11-02 18:08:38 +08:00
Eren Terzioglu
3796f56748 esp32[s2|s3]: Add I2C bitbang support 2024-11-01 11:41:46 -03:00
Eren Terzioglu
4afaef1a30 esp32[c3|c6|h2]: Add I2C bitbang supoort 2024-11-01 11:41:46 -03:00
ouyangxiangzhen
17c51c0667 userspace: Exclude nuttx/arch.h
This patch fixed userspace headers conflict. Architecture-related definition and API should not be exposed to users.

Signed-off-by: ouyangxiangzhen <ouyangxiangzhen@xiaomi.com>
2024-11-01 16:59:37 +08:00
xuxin19
b8523280c2 cmake(bugfix):fix cxx build error on fastDDS X86_64
Signed-off-by: xuxin19 <xuxin19@xiaomi.com>
2024-10-31 17:55:13 +08:00
xuxin19
8da0206a40 cmake:fix sim gc-section option build failed
Signed-off-by: xuxin19 <xuxin19@xiaomi.com>
2024-10-31 17:55:13 +08:00
Jukka Laitinen
da19d79656 arch/arm64/src/imx9/imx9_lpuart.c: Fix parity get in TCGETS
This is a partial revert / fix for regression from 44d1811ebb

Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
2024-10-31 17:54:22 +08:00
hujun5
9b1800d043 irq: force inline up_interrupt_context
reason:
Replace "inline" with "inline_function" for "up_interrupt_context" to ensure consistency with other arch

Signed-off-by: hujun5 <hujun5@xiaomi.com>
2024-10-31 15:43:41 +08:00
Ville Juven
f36dff8105 riscv/syscall: Fix sched_note instrumentation for BUILD_KERNEL
The sched_note calls were missing from riscv_perform_syscall().
2024-10-30 23:18:07 +08:00
xuxin19
e60c60b691 cmake(sync):fix cmake SIM build error build nuttx upstream
/usr/lib/x86_64-linux-gnu/libSM.so  /usr/lib/x86_64-linux-gnu/libICE.so  /usr/lib/x86_64-linux-gnu/libX11.so  /usr/lib/x86_64-linux-gnu/libXext.so  -lpthread  -lrt  -lm  -lasound  -lmad  -lv4l2 && :
/usr/bin/ld: /usr/lib/x86_64-linux-gnu/libSM.so: error adding symbols: file in wrong format

Signed-off-by: xuxin19 <xuxin19@xiaomi.com>
2024-10-30 22:14:40 +08:00
xuxin19
c60b980968 cmake(bugfix):fix robot openlibm cmake build missing source error
Signed-off-by: xuxin19 <xuxin19@xiaomi.com>
2024-10-30 22:14:40 +08:00
Ville Juven
9d4218666c mpfs/smp: Add riscv_macros to mpfs_shead
To get definition for riscv_set_inital_sp macro
2024-10-30 22:09:01 +08:00
YAMAMOTO Takashi
761ee81956 move readv/writev to the kernel
currently, nuttx implements readv/writev on the top of read/write.
while it might work for the simplest cases, it's broken by design.
for example, it's impossible to make it work correctly for files
which need to preserve data boundaries without allocating a single
contiguous buffer. (udp socket, some character devices, etc)

this change is a start of the migration to a better design.
that is, implement read/write on the top of readv/writev.

to avoid a single huge change, following things will NOT be done in
this commit:

* fix actual bugs caused by the original readv-based-on-read design.
  (cf. https://github.com/apache/nuttx/pull/12674)

* adapt filesystems/drivers to actually benefit from the new interface.
  (except a few trivial examples)

* eventually retire the old interface.

* retire read/write syscalls. implement them in libc instead.

* pread/pwrite/preadv/pwritev (except the introduction of struct uio,
  which is a preparation to back these variations with the new
  interface.)
2024-10-30 17:07:54 +08:00
wangmingrong1
e3d7d23618 gcov: Fix typographical errors
1. CONFIG_ARCH_COVERAGE has been replaced by CONFIG_SCHED_GCOV
2. Delete the SIM-specific GCOV_ALL configuration and change it to a universal configuration for all architectures

Signed-off-by: wangmingrong1 <wangmingrong1@xiaomi.com>
2024-10-30 14:45:23 +08:00
nuttxs
0c5381a0a1 xtensa/esp32s3: add esp32s3 reset reasons interface 2024-10-29 23:03:37 +08:00
Gao Feng
782ab3b248 xtensa/esp32s3: enable encrypted flag based on partition and device
If device encryption is not enabled by eFuse, and partiton mark as
encrypted flag, then encrypted MTD is used.

That is no problem in write and read operation, but failed while
using spi_flash_mmap(...) since de-encrypt is not processed.

So, back to use non-encrypted MTD following API Guide:
If flash encryption is not enabled, the flag "encrypted" has no effect
2024-10-29 23:02:35 +08:00
cuiziwei
d42f16939e nuttx: Fix build warning with can't found xt-g++
Signed-off-by: cuiziwei <cuiziwei@xiaomi.com>
2024-10-29 22:27:58 +08:00
Jukka Laitinen
62194400f9 imx9/serial: Take proper use of RX/TX FIFOs, clean up interrupt service routine
- i.MX93 LPUARTs have 16-byte RX and TX FIFOs. Take those into use and correct some related register definitions
- There is no reason to loop inside interrupt handler, remove the looping

Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
2024-10-29 22:24:48 +08:00
Jukka Laitinen
44d1811ebb imx9/serial: Clean up the flow control code
- Remove GPIO (SW) based flow control. It didn't work, and pure HW flow control seems to work fine
- Remove some unneeded ifdefs and change bit-field flags to booleans to clean up the code

Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
2024-10-29 22:24:48 +08:00
wangmingrong1
083f9d162e clang/ld.lld: clang17 and above support the option --print-memory-usage
1. cmake uses clang++ as a connector, and does not currently support:
	clang++: error: unknown argument: '-wl,--print-memory-usage'
	clang++: error: no input files

Signed-off-by: wangmingrong1 <wangmingrong1@xiaomi.com>
2024-10-29 20:43:35 +08:00
chao an
e3689cbb2f CMake/preprocess: fix typo PREPROCES -> PREPROCESS
correct the marco define from PREPROCES to PREPROCESS

Signed-off-by: chao an <anchao@lixiang.com>
2024-10-29 17:41:01 +08:00
raiden00pl
716d898dda arch/arm/stm32/stm32_dumpgpio.c: fix print warnings
fix print warnings for stm32_dumpgpio.c
2024-10-29 02:23:36 +08:00
raiden00pl
7ebb8af454 arch/arm/stm32/Kconfig: fix Kconfig error
fix Kconfig error related to STM32_HAVE_HRTIM1_PLLCLK
2024-10-28 19:36:17 +08:00
wangmingrong1
e174d73cd9 clang:libclang_rt.builtins-xxx.a supports builtin
1. enable CONFIG_BUILTIN_COMPILER_RT  to built libclang_rt.builtins-xxx.a and no longer use the compiler's built-in
2. Modify clang version acquisition to get two decimal points
3. It has been ported to support four architectures: ARM, ARM64, RISCV, and x86_64, among which ARM has been validated

Signed-off-by: wangmingrong1 <wangmingrong1@xiaomi.com>
2024-10-28 16:38:45 +08:00
Xiang Xiao
69100ef0e4 arch: Fix minor style issue
not real behaviour change

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2024-10-28 09:24:55 +01:00
raiden00pl
b5e5cdd851 arch/arm/stm32h7: add workaround for Renode
Add an option to disable busy wait PWR_CSR1_ACTVOSRDY during boot
which doesn't work with Renode simulation
2024-10-26 20:49:49 +08:00
chao an
c6591c0f49 driver/serial: remove return value of up_putc()
modify the prototype of up_putc(): remove the return value

The architecture code does not care about the return value of up_putc(), so removing it saves two statements:

Before:                                                    After:
de4c: e52de004  push  {lr}    @ (str lr, [sp, #-4]!)    |  de4c: e52de004  push  {lr}    @ (str lr, [sp, #-4]!)
de50: e24dd014  sub sp, sp, #20                         |  de50: e24dd014  sub sp, sp, #20
de54: e58d0004  str r0, [sp, #4]                        |  de54: e58d0004  str r0, [sp, #4]
de58: e30030f8  movw  r3, #248  @ 0xf8                  |  de58: e30030f8  movw  r3, #248  @ 0xf8
de5c: e3423000  movt  r3, #8192 @ 0x2000                |  de5c: e3423000  movt  r3, #8192 @ 0x2000
de60: e58d300c  str r3, [sp, #12]                       |  de60: e58d300c  str r3, [sp, #12]
de64: e59d1004  ldr r1, [sp, #4]                        |  de64: e59d1004  ldr r1, [sp, #4]
de68: e59d000c  ldr r0, [sp, #12]                       |  de68: e59d000c  ldr r0, [sp, #12]
de6c: ebfffe66  bl  d80c <pl011_putc>                   |  de6c: ebfffe66  bl  d80c <pl011_putc>
de70: e59d3004  ldr r3, [sp, #4]                        |  de70: e28dd014  add sp, sp, #20
de74: e1a00003  mov r0, r3                              |  de74: e49df004  pop {pc}    @ (ldr pc, [sp], #4)
de78: e28dd014  add sp, sp, #20                         |
de7c: e49df004  pop {pc}    @ (ldr pc, [sp], #4)        |

Signed-off-by: chao an <anchao@lixiang.com>
2024-10-26 13:21:29 +08:00
Haiyue Wang
d0f957ae85 qemu-intel64: Fixes the linker 'noexecstack' warning
Fix the linker warning based on these two commits:

 ld: warning: fork.o: missing .note.GNU-stack section implies executable stack
 ld: NOTE: This behaviour is deprecated and will be removed in a future version of the linker

commit 36ac812114 ("sim: Fixes the following linker warning:"),
commit b5d640acc5 ("fix Cygwin/MSYS2  ld: unrecognized option '-z'")
2024-10-26 11:10:43 +08:00
raiden00pl
da1ff4cf77 arch/arm/stm32: convert error to warning when CCM is not enabled
User may set CONFIG_MM_REGIONS=1 on purpose to disable CCM.
This is a completely normal system config and should not be treated as error.

I found this problem trying to run Renode with stm32f4discovery/nsh but
Renode doesn't support CCM so we have to disable it
2024-10-26 11:02:19 +08:00
YAMAMOTO Takashi
6a2e21dd07 esp32: Fix a heap corruption bug with SPIRAM
Don't add SPIRAM ("HEAP2") to both of kernel/user heaps.

Sync with the corresponding logic in esp32s3.
2024-10-25 19:03:22 +08:00
chao an
b28f87e3f0 arm/gicv3: replace this_cpu() to up_cpu_index()
If the core id needs to be included in the hardware register
calculation, up_cpu_index() should be used instead of this_cpu().

Signed-off-by: chao an <anchao@lixiang.com>
2024-10-25 14:27:34 +08:00
Jinliang Li
5fb0c44f38 arm/armv8-r: optimize generic timer initialization
1. Enable timer and irq finally to make sure timer callback was already
   registered. When the CPU resets, the values of some generic timer
   registers are undefined. Enabling the timer interrupt in advance may
   cause the timer to trigger early while the timer callback is not yet
   registered. This results in the timer ISR being executed, which masks
   the timer interrupt. Since the timer callback is not registered at
   this point, the timer interrupt is not unmasked, further causing the
   system scheduler to hang.
2. Remove timer mask for one-shot timer and that's in isr,
   irq/fiq is disabled. Masking generic timer is not necessary, and it
   may introduce risks, otherwise, mask/unmask must be pair in all
   situations.

Signed-off-by: Jinliang Li <lijinliang1@lixiang.com>
2024-10-25 13:17:08 +08:00
Jinliang Li
40bbe7f3e9 arm/armv8-r: init HSCTLR and HACTLR for EL2
1. init HSCTLR to enable i-cache/d-cache for EL2
2. init HACTLR to enable all access to implementation defined
   registers for EL1.
3. add dsb/isb before switch to EL1 from EL2

Signed-off-by: Jinliang Li <lijinliang1@lixiang.com>
2024-10-25 12:09:47 +08:00
chao an
ea4c4ef36a arm/armv8-r: fix unable to switch context in ISR context
Regression by:
| commit 35c8c80a00
| Author: ligd <liguiding1@xiaomi.com>
| Date:   Fri Jul 26 23:14:13 2024 +0800
|
| arch: change nxsched_suspend/resume_scheduler() called position

Signed-off-by: chao an <anchao@lixiang.com>
2024-10-25 09:47:37 +08:00
Tim Hardisty
517c66daf8 sam_sfc.c incorrect EFUSEIOC name used 2024-10-25 08:42:40 +08:00
wangmingrong1
f11b04fc61 kconfig: Add link parameters that can print remaining memory information
LD: nuttx
Memory region         Used Size  Region Size  %age Used
           flash:      284272 B       512 KB     54.22%
           sram1:       13296 B         2 MB      0.63%
           sram2:          0 GB         2 MB      0.00%
CP: nuttx.hex
CP: nuttx.bin

Signed-off-by: wangmingrong1 <wangmingrong1@xiaomi.com>
2024-10-25 00:55:50 +08:00
buxiasen
974db76cb9 sim/cmake: compatible when nuttx COMPILE_OPTIONS is not set yet
Signed-off-by: buxiasen <buxiasen@xiaomi.com>
2024-10-24 21:42:06 +08:00
wangmingrong1
d007193eef armv8m/clang.cmake: add armv8m clang config
Its makefile is implemented in arch/arm/src/armv8-m/Toolchain.defs as follows:
ifeq ($(CONFIG_ARM_TOOLCHAIN_CLANG),y)

  ifeq ($(CONFIG_ARCH_CORTEXM23),y)
    TOOLCHAIN_CLANG_CONFIG = armv8m.main_soft_nofp
  else ifeq ($(CONFIG_ARCH_CORTEXM33),y)
    ifeq ($(CONFIG_ARCH_FPU),y)
      TOOLCHAIN_CLANG_CONFIG = armv8m.main_hard_fp
    else
      TOOLCHAIN_CLANG_CONFIG = armv8m.main_soft_nofp
    endif
  else ifeq ($(CONFIG_ARCH_CORTEXM35P),y)
    ifeq ($(CONFIG_ARCH_FPU),y)
      TOOLCHAIN_CLANG_CONFIG = armv8m.main_hard_fp
    else
      TOOLCHAIN_CLANG_CONFIG = armv8m.main_soft_nofp
    endif
  else ifeq ($(CONFIG_ARCH_CORTEXM55),y)
    ifeq ($(CONFIG_ARCH_FPU),y)
      TOOLCHAIN_CLANG_CONFIG = armv8.1m.main_hard_fp
    else
      TOOLCHAIN_CLANG_CONFIG = armv8.1m.main_soft_nofp_nomve
    endif
  else ifeq ($(CONFIG_ARCH_CORTEXM85),y)
    ifeq ($(CONFIG_ARCH_FPU),y)
      TOOLCHAIN_CLANG_CONFIG = armv8.1m.main_hard_fp
    else
      TOOLCHAIN_CLANG_CONFIG = armv8.1m.main_soft_nofp_nomve
    endif
  endif

Signed-off-by: wangmingrong1 <wangmingrong1@xiaomi.com>
2024-10-24 18:41:11 +08:00
Michal Lenc
d8ed88c8a6 samv7: fix QSPI build
Commit 313d6df7 caused the following build error:

CC:  fixedmath/lib_b16atan2.c chip/sam_qspi.c: In function 'qspi_memory':
chip/sam_qspi.c:1552:7: warning: implicit declaration of function 'IS_ALIGNED' [-Wimplicit-function-declaration]
 1552 |       IS_ALIGNED((uintptr_t)meminfo->buffer, 4) &&
      |       ^~~~~~~~~~
In file included from chip/sam_qspi.c:41:
chip/sam_qspi.c: In function 'qspi_alloc':
chip/sam_qspi.c:1591:21: warning: implicit declaration of function 'ALIGN_UP' [-Wimplicit-function-declaration]
 1591 |   return kmm_malloc(ALIGN_UP(buflen, 4));

This was caused by missing include of nuttx.h header defining ALIGN_UP
and IS_ALIGNED.

Signed-off-by: Michal Lenc <michallenc@seznam.cz>
2024-10-24 18:00:05 +08:00
zhanghongyu
c3a0155374 arch/Kconfig: remove ARCH_MATH_H if LIBCXX
Because some libraries do require a full libm implementation.

Signed-off-by: zhanghongyu <zhanghongyu@xiaomi.com>
2024-10-24 17:44:22 +08:00
hujun5
9395669ac0 arm64: fix fvp smp faild to boot
reason:
we should give a busy wait addr

This commit fixes the regression from https://github.com/apache/nuttx/pull/13640

Signed-off-by: hujun5 <hujun5@xiaomi.com>
2024-10-24 10:17:48 +08:00
cuiziwei
12fd5ec472 nuttx: Add LIBSUPCXX_TOOLCHAIN to link the prebuilt library provide by toolchain.
Signed-off-by: cuiziwei <cuiziwei@xiaomi.com>
2024-10-24 01:38:03 +08:00
Tiago Medicci Serrano
d1fd1ed8f6 boards/esp32s3: Merge MCUboot and "simple-boot" linker scripts
To make it easier to keep the linker scripts updated for both
MCUboot and "simple-boot", this commit merges them into a single
linker script with macros to enable/disable specific sections.
2024-10-23 22:26:39 +08:00
cuiziwei
60e7a0074d nuttx/arch:Enabling ARCH_MATH_H is required when compiling sim with the 13.2 version of the toolchain.
Signed-off-by: cuiziwei <cuiziwei@xiaomi.com>
Signed-off-by: ligd <liguiding1@xiaomi.com>
2024-10-23 20:10:43 +08:00
Jukka Laitinen
cdd11112fd arch/arm64/src/imx9/imx9_lpspi.c: Small cache operation optimization
There is no need to invalidate the RX buffer before every transfer.
It is never gets dirty, so it is good to invalidate initially after allocation,
and after each transfer.

Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
2024-10-23 19:46:42 +08:00
Jukka Laitinen
6cadfc16cd arch/arm64/src/imx9/imx9_lpspi.c: Fix 9-16 bit transfers
Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
2024-10-23 19:46:42 +08:00
Jinliang Li
52995452e5 arm/build: suppress LOAD RWX linker warning
Add --no-warn-rwx-segments in case of RAM boot mode to linker to
suppress the below warning:
"nuttx has a LOAD segment with RWX permissions"

Signed-off-by: Jinliang Li <lijinliang1@lixiang.com>
2024-10-23 19:38:31 +08:00
lipengfei28
3225aa853f arch/arm64: vector table 2K align
Signed-off-by: lipengfei28 <lipengfei28@xiaomi.com>
2024-10-23 15:15:12 +08:00
liwenxiang1
eb722794b5 arch/x86_64:Fix variable used before assignment
Signed-off-by: liwenxiang1 <liwenxiang1@xiaomi.com>
2024-10-23 14:28:59 +08:00
lipengfei28
877f42cde5 remove unused variable 'cpu_freq'
Signed-off-by: lipengfei28 <lipengfei28@xiaomi.com>
2024-10-23 10:53:27 +08:00
wangmingrong1
45c5d3c143 arm64/toolchains:Add the following kasan compilation options
Signed-off-by: wangmingrong1 <wangmingrong1@xiaomi.com>
2024-10-23 10:53:16 +08:00
lipengfei28
c95ed45ccc arhc/arm64: vector table may be far away form arm64_fatal_handle
use 33-bit (+/-4GB) pc-relative addressing to load
the address of arm64_fatal_handle

Signed-off-by: lipengfei28 <lipengfei28@xiaomi.com>
2024-10-23 10:09:17 +08:00
buxiasen
105d47b9a6 arch/sim/cmake: remove the host specific -U when HOSTSRCS
fix macos compile hostfs.c compile issue.
/Applications/Xcode.app/Contents/Developer/Platforms/MacOSX.platform/Developer/SDKs/MacOSX15.0.sdk/usr/include/_string.h:131:62: error: expected function body after function declarator
  131 | char    *stpncpy(char *__dst, const char *__src, size_t __n) __OSX_AVAILABLE_STARTING(__MAC_10_7, __IPHONE_4_3);
      |                                                              ^

Signed-off-by: buxiasen <buxiasen@gmail.com>
2024-10-23 10:08:23 +08:00
yangsong8
5b5f148178 sim_uart: rm LF to CRLF convertion
LF to CRLF has been converted in syslog framework

Signed-off-by: yangsong8 <yangsong8@xiaomi.com>
2024-10-23 00:37:43 +08:00
qinwei1
9b0fc1277b arm: add memory map for DDR region
Summary
  add memory map for DDR region

fix arm-v7a/knsh boot dataabort on arm_addrenv_utils.c first time memset
after arm_pgvaddr.

Signed-off-by: qinwei1 <qinwei1@xiaomi.com>
2024-10-22 13:33:39 +08:00
cuiziwei
8e95f6800b fix GCCVER cmake define.
Signed-off-by: cuiziwei <cuiziwei@xiaomi.com>
2024-10-21 18:03:23 +02:00
xuxin19
82677145ed cmake(bugfix):Fixed the issue that the host toolchain version cannot be specified
SIM arch does not need to execute find_program

Signed-off-by: xuxin19 <xuxin19@xiaomi.com>
2024-10-21 18:28:39 +08:00
Felipe Moura
0496f357c9 Fix spi slave communication issue 2024-10-21 12:21:39 +08:00
dongjiuzhu1
c4780f1a69 drivers/spi_slave: call SPIS_DEV_NOTIFY when rx or tx complete for all spi slave driver
Signed-off-by: dongjiuzhu1 <dongjiuzhu1@xiaomi.com>
2024-10-20 15:48:00 -03:00
guoshichao
65aa5415a7 cmake: fix the fdiagnostics-color handle issue
Signed-off-by: guoshichao <guoshichao@xiaomi.com>
2024-10-19 14:32:35 +08:00
cuiziwei
9614e1fed5 Add GCCVER define to Toolchain.cmake
Since GCCVER will also be used in the toolchain, it needs to be defined in advance.

Signed-off-by: cuiziwei <cuiziwei@xiaomi.com>
2024-10-19 14:32:08 +08:00
cuiziwei
541f30878a arch/x86_64:Add CXX configuration for enabling x86_64 support for C++ applications.
Signed-off-by: cuiziwei <cuiziwei@xiaomi.com>
2024-10-18 23:53:35 +08:00
Eren Terzioglu
05ba822c41 esp32[c3]: Add BLE support 2024-10-18 21:33:58 +08:00
Ville Juven
5de9d957e6 ricv/riscv_cpuid: Return meaningful values for CPU/Hart ID when SMP=no
Return 0 for CPU ID for any hart ID, and return the current Hart ID for
any CPU ID. At least these values are somewhat usable / meaningful in
non-SMP configurations.
2024-10-18 21:31:17 +08:00
Ville Juven
cf95305934 mpfs/mpfs_plic: Add procedure to initialize per hart PLIC state
MPFS implements external interrupt control on a per-hart basis i.e. there
are PLIC control registers for each hart separately. This means we need
a procedure to initialize such registers for each hart individually,
instead of only for the boot hart like it is now.

Fix this by implementing mpfs_plic_init_hart which can be called by each
hart as needed.

Note: it is not a good idea to initialize all harts from the boot hart,
as the boot hart may not know which harts are used by NuttX in AMP
configuration. It is better that the hart initializes itself.

Note: The hartid must be provided as explicit parameter, as it cannot
be queried via riscv_mhartid() yet; the per-cpu structure is initialized
later on which means riscv_mhartid() would return 0 for all harts except
the boot hart.
2024-10-18 19:34:57 +08:00
Ville Juven
a33e63097a riscv/mpfs: Add boilerplate code for SMP 2024-10-18 19:34:57 +08:00
Ville Juven
c99de98995 mpfs_start: Initialize percpu as soon as possible
Otherwise querying for hartid doesn't work.
2024-10-18 19:34:57 +08:00
Xiang Xiao
24cb8c25ab bluetooth: Fix the incompatibility made by https://github.com/apache/nuttx/pull/14224
that pr requires chip turn on CONFIG_DRIVERS_BLUETOOTH to use bluetooth,
but not all defconig enable this option, so let's map bt_driver_register
to bt_netdev_register in header file in this case, and revert the unnessary
change in the related chip and board folders.

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2024-10-18 09:05:54 +08:00
buxiasen
bc019cb913 arm/lc823450: use custom vectors to make smp_call work with exception_common
Signed-off-by: buxiasen <buxiasen@xiaomi.com>
2024-10-17 22:57:14 +08:00
buxiasen
15804c340a arm/sam4cm: use custom vectors to make smp_call work with exception_common
Signed-off-by: buxiasen <buxiasen@xiaomi.com>
2024-10-17 22:57:14 +08:00
buxiasen
d410eedfde arm/rp2040: use custom vectors to make smp_call work with exception_common
Signed-off-by: buxiasen <buxiasen@xiaomi.com>
2024-10-17 22:57:14 +08:00
buxiasen
9a73b28973 arm/cxd56: use chip specific vectors to allow smpcall update regs
When sig dispatch do up_schedule_sigaction, need to make a new frame to
run arm_sigdeliver. But the exception_direct cannot handle xcp.regs as
we are using c-function exception handler.
Need to use exception_common to handle SMP call.

Signed-off-by: buxiasen <buxiasen@xiaomi.com>
2024-10-17 22:57:14 +08:00
buxiasen
4e2b77cb04 arch/arm: add support for chip to replace the default vector table
Signed-off-by: buxiasen <buxiasen@xiaomi.com>
2024-10-17 22:57:14 +08:00
Ville Juven
25b33f202e riscv_cpuindex.c: Fix usage of CONFIG_ARCH_RV_HARTID_BASE
The offset was supposed to assume hartid > cpuid, so when converting from
hartid we must subtract the offset to get the cpuid and vice versa.
2024-10-17 22:54:06 +08:00
chengkai
6aeb2e2996 Add space before error, bt_driver_register_internal not trigger error, add defconfig DRIVERS_BLUETOOTH.
Signed-off-by: chengkai <chengkai@xiaomi.com>
2024-10-17 18:09:32 +08:00
chengkai
31605b6335 bluetooth: call bt_driver_register common interface
Signed-off-by: chengkai <chengkai@xiaomi.com>
2024-10-17 18:09:32 +08:00
chengkai
113b660aa6 bluetooth: fix dev->rxlen is considered to have possibly overflowed
rootcause: fix the expression dev->rxlen is considered to
have possibly overflowed.

Signed-off-by: chengkai <chengkai@xiaomi.com>
2024-10-17 18:09:32 +08:00
chengkai
933841d985 bluetooth:support read imcompleted hci data from blueooth socket
hci data from bluetooth socket maybe imcompleted hci data.

Signed-off-by: chengkai <chengkai@xiaomi.com>
2024-10-17 18:09:32 +08:00
Ville Juven
8811eee0f4 riscv_cpustart.c: Fix reading of interrupt status
Let's read the interrupt status correctly, by checking for the interrupt
source bit instead of assuming no other status bit is set.
2024-10-17 18:08:10 +08:00
Ville Juven
8fe3ab3e39 arch/arm64: Remove arm64_copystate.c
The file is not referenced from anywhere and is obsolete / dead code anyway
-> remove it from the index.
2024-10-17 18:07:54 +08:00
Ville Juven
737dc4fcdd arch/riscv: Implement cpuid mapping
Implement hartid<->cpuid mapping for RISC-V. This is necessary for some
platforms which cannot use 1:1 mapping between logical and physical CPU /
core IDs. One example is MPFS where hart0 cannot be used for NuttX SMP as
it is a less capable "monitor" core (E51) compared to the application
cores hart1...3 (E54).

Why not just use a generic offset then? We also need the physical hart ID
for many things:
- Communication between harts (IPI)
- External interrupt acknowledgment (interrupt claim for specific CPU)
- Communication to SBI

Thus, create procedures that can do this translation:
- The default mapping is still logical=physical.
- Another flavor is to use the existing CONFIG_ARCH_RV_HARTID_BASE config
  variable, which is just a simple offset
- The final flavor is to overload hartid<->cpuid on a per chip basis (no
  example for this is provided yet)
2024-10-17 13:43:06 +08:00
Ville Juven
2195b47655 smp: Implement empty macro for obtaining logical CPU index
This implements empty hooks to the arch/chip layer, which can implement
an optional translation between logical<->physical CPU/core id.

The default mapping is 1:1 i.e. logical=physical.
2024-10-17 13:43:06 +08:00
Ville Juven
f47c0a1953 arch/riscv: Remove CONFIG_ARCH_RV_HARTID_BASE offset from riscv_mhartid
The function is supposed to return the physical hart ID. It is needed
for e.g. external interrupt acknowledgment (see mpfs_plic.c).

This offset is moved initially to up_cpu_index (which is also wrong, but
less wrong than the current implementation). Finally, a translation
between physical <-> logical shall be provided.
2024-10-17 13:43:06 +08:00
lipengfei28
ef350afd28 Revert "arch/arm64: add CONFIG_ARCH_VMA_MAPPING"
This reverts commit e7326cfa62.
2024-10-17 12:28:58 +08:00
Petro Karashchenko
2048715134 serial: remove 'TIOCSLINID'
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
2024-10-17 09:08:58 +08:00
Petro Karashchenko
919242d8b9 arch/arm/samv7: fix warnings in rswdt
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
2024-10-17 09:08:01 +08:00
Petro Karashchenko
beda2abe3b arch/arm/samv7: fix preprocessor logic for ethernet
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
2024-10-17 09:08:01 +08:00