By default in SMP, obtaining this_task requires disabling interrupts, obtaining the current CPU index, accessing a global variable, and re-enabling interrupts. Storing this_task in percpu makes retrieval faster.
Signed-off-by: liwenxiang1 <liwenxiang1@xiaomi.com>
1. Change the CONFIG_RPMSG_VIRTIO to CONFIG_RPMSG_VIRTIO_LITE
2. fix the error when modify the sim_rpmsg_virtio to port to
rpsmg_virtio_lite;
Signed-off-by: Bowen Wang <wangbowen6@xiaomi.com>
Because rpmsg_virtio_lite is a better name to inform user that the
rpmsg virtio (original name) is a lite implementation of rpmsg virtio.
Signed-off-by: Bowen Wang <wangbowen6@xiaomi.com>
Register addresses are defined. Bit defintions are still needed.
Bitmaps for OCTOSPI peripheral register
Incremental updates to qspi files
Redefined QSPI/OCTOSPI registers for STM32H5
Fixed register definitions for the STM32H5. However, more work still needs to be done. Some bits that shared registers on the STM32H7 have different register locations on the H5. This still needs to be accounted for.
Fixed more differences vs STM32H7 qspi
Added ifdef for including stm32_dma.h in stm32_qspi.c. Added stm32_qspi.c to Make.defs.
Register fixes. SPI activity but not able to format device yet.
Fixed DCYC mask
Set HCLK frequency to correct value. Undid ccrconfig debug.
Tested Interrupt Mode (single SPI). Added alternate bytes to meminfo and cmdinfo structures. Updated Kconfig variables for STM32H5.
Fixed base register in hardware/stm32_qspi.h. Updated qspi_dumpregs.
The base register was previously set to STM32_QUADSPI_BASE, changed to the correctly named STM32_OCTOSPI1_BASE. However, these defines for the OCTOSPI registers are not even used. Instead qspi_putreg and qspi_getreg utilize the priv->base value to access OCTOSPI registers.
Removed altbytes code, left as before. Moved QSPI clock selection to stm32h5xx_rcc.c
Changed STM32H5_QUADSPI to STM32H5_QSPI1
Added hook to define QSPI_CLK_FREQUENCY as STM32_QSPI_FREQUENCY from board.h
Removed changes to nuttx qspi.h
style fixes
chip/efm32_leserial.c: In function 'efm32_restoreuartint':
Error: chip/efm32_leserial.c:329:37: error: 'len' undeclared (first use in this function); did you mean 'ien'?
329 | efm32_restoreuartint_nolock(priv, len);
| ^~~
| ien
Signed-off-by: hujun5 <hujun5@xiaomi.com>
There were two simple errors when running ci tests on pull #15351. These errors were unrelated to that pull. After investigating I found two simple errors. 1. The len variable was likely a typo that should have been the function argument, ien. 2. The spinlock_t lock was defined in a section dependent on CONFIG_SERIAL_TERMIOS. However, the spinlock_t lock was used in code that did not require the SERIAL_TERMIOS config. Therefore errors resulted.
imxrt_edma_s missing lock variable
CI build tests noted that the variable g_edma was referencing a lock variable that did not exist in the structure. This change adds that missing lock as a spinlock_t type.
Remove unused flags variable from imxrt_dmach_stop
Removed extra =
Before the MPU initialization, the up_update_task(this_cpu()) function is called at a time when hardware cache coherency is not yet enabled.
In certain critical scenarios, Core 1 reads a zero value for tcb from the global variable g_assignedtask and stores this zero value into the tpidr
register. This results in subsequent interrupt handlers reading a zero tcb, causing an exception.
Signed-off-by: hujun5 <hujun5@xiaomi.com>
Fixed comments and indent
Add commit log to OCTOSPI HW PR
Summary
hardware/stm32_qspi.h - Defines for the STM32H5 QSPI driver. The peripheral on the STM32H5 is actually an OCTOSPI peripheral, however it was decided to use it as a QSPI peripheral for the following reasons:
There is currently support for QSPI within Nuttx.
The STM32H7 QSPI register set is very similar to the STM32H5 OCTOSPI register set and the STM32H7 series has an existing QSPI driver.
OCTOSPI devices are rare as of now and are not part of our use case.
hardware/stm32h56xxx_pinmap.h - Added pin mappings for OCTOSPI GPIOs.
Impact
This change will not impact any architectures outside of the STM32H5 series. Even for the STM32H5 series, these changes will only have an impact if they are utilized.
Testing
No testing yet for these files other than ensuring that we can still build Nuttx. Further testing will be documented in a future pull request when the STM32H5 QSPI driver is added.
The fake audio driver aims to easily simulate the functions of audio driver through reading and writing files.
With it, you can conveniently customize and define various capture or playback audio drivers for debugging or automated testing.
Signed-off-by: yaojingwei <yaojingwei@xiaomi.com>
